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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Flora Fu, MediaTek
0005  */
0006 #include <linux/clk.h>
0007 #include <linux/interrupt.h>
0008 #include <linux/io.h>
0009 #include <linux/kernel.h>
0010 #include <linux/module.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/regmap.h>
0014 #include <linux/reset.h>
0015 
0016 #define PWRAP_POLL_DELAY_US 10
0017 #define PWRAP_POLL_TIMEOUT_US   10000
0018 
0019 #define PWRAP_MT8135_BRIDGE_IORD_ARB_EN     0x4
0020 #define PWRAP_MT8135_BRIDGE_WACS3_EN        0x10
0021 #define PWRAP_MT8135_BRIDGE_INIT_DONE3      0x14
0022 #define PWRAP_MT8135_BRIDGE_WACS4_EN        0x24
0023 #define PWRAP_MT8135_BRIDGE_INIT_DONE4      0x28
0024 #define PWRAP_MT8135_BRIDGE_INT_EN      0x38
0025 #define PWRAP_MT8135_BRIDGE_TIMER_EN        0x48
0026 #define PWRAP_MT8135_BRIDGE_WDT_UNIT        0x50
0027 #define PWRAP_MT8135_BRIDGE_WDT_SRC_EN      0x54
0028 
0029 /* macro for wrapper status */
0030 #define PWRAP_GET_WACS_RDATA(x)     (((x) >> 0) & 0x0000ffff)
0031 #define PWRAP_GET_WACS_ARB_FSM(x)   (((x) >> 1) & 0x00000007)
0032 #define PWRAP_GET_WACS_FSM(x)       (((x) >> 16) & 0x00000007)
0033 #define PWRAP_GET_WACS_REQ(x)       (((x) >> 19) & 0x00000001)
0034 #define PWRAP_STATE_SYNC_IDLE0      BIT(20)
0035 #define PWRAP_STATE_INIT_DONE0      BIT(21)
0036 #define PWRAP_STATE_INIT_DONE0_MT8186   BIT(22)
0037 #define PWRAP_STATE_INIT_DONE1      BIT(15)
0038 
0039 /* macro for WACS FSM */
0040 #define PWRAP_WACS_FSM_IDLE     0x00
0041 #define PWRAP_WACS_FSM_REQ      0x02
0042 #define PWRAP_WACS_FSM_WFDLE        0x04
0043 #define PWRAP_WACS_FSM_WFVLDCLR     0x06
0044 #define PWRAP_WACS_INIT_DONE        0x01
0045 #define PWRAP_WACS_WACS_SYNC_IDLE   0x01
0046 #define PWRAP_WACS_SYNC_BUSY        0x00
0047 
0048 /* macro for device wrapper default value */
0049 #define PWRAP_DEW_READ_TEST_VAL     0x5aa5
0050 #define PWRAP_DEW_WRITE_TEST_VAL    0xa55a
0051 
0052 /* macro for manual command */
0053 #define PWRAP_MAN_CMD_SPI_WRITE_NEW (1 << 14)
0054 #define PWRAP_MAN_CMD_SPI_WRITE     (1 << 13)
0055 #define PWRAP_MAN_CMD_OP_CSH        (0x0 << 8)
0056 #define PWRAP_MAN_CMD_OP_CSL        (0x1 << 8)
0057 #define PWRAP_MAN_CMD_OP_CK     (0x2 << 8)
0058 #define PWRAP_MAN_CMD_OP_OUTS       (0x8 << 8)
0059 #define PWRAP_MAN_CMD_OP_OUTD       (0x9 << 8)
0060 #define PWRAP_MAN_CMD_OP_OUTQ       (0xa << 8)
0061 
0062 /* macro for Watch Dog Timer Source */
0063 #define PWRAP_WDT_SRC_EN_STAUPD_TRIG        (1 << 25)
0064 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE    (1 << 20)
0065 #define PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE    (1 << 6)
0066 #define PWRAP_WDT_SRC_MASK_ALL          0xffffffff
0067 #define PWRAP_WDT_SRC_MASK_NO_STAUPD    ~(PWRAP_WDT_SRC_EN_STAUPD_TRIG | \
0068                       PWRAP_WDT_SRC_EN_HARB_STAUPD_DLE | \
0069                       PWRAP_WDT_SRC_EN_HARB_STAUPD_ALE)
0070 
0071 /* Group of bits used for shown slave capability */
0072 #define PWRAP_SLV_CAP_SPI   BIT(0)
0073 #define PWRAP_SLV_CAP_DUALIO    BIT(1)
0074 #define PWRAP_SLV_CAP_SECURITY  BIT(2)
0075 #define HAS_CAP(_c, _x) (((_c) & (_x)) == (_x))
0076 
0077 /* Group of bits used for shown pwrap capability */
0078 #define PWRAP_CAP_BRIDGE    BIT(0)
0079 #define PWRAP_CAP_RESET     BIT(1)
0080 #define PWRAP_CAP_DCM       BIT(2)
0081 #define PWRAP_CAP_INT1_EN   BIT(3)
0082 #define PWRAP_CAP_WDT_SRC1  BIT(4)
0083 #define PWRAP_CAP_ARB       BIT(5)
0084 #define PWRAP_CAP_ARB_MT8186    BIT(8)
0085 
0086 /* defines for slave device wrapper registers */
0087 enum dew_regs {
0088     PWRAP_DEW_BASE,
0089     PWRAP_DEW_DIO_EN,
0090     PWRAP_DEW_READ_TEST,
0091     PWRAP_DEW_WRITE_TEST,
0092     PWRAP_DEW_CRC_EN,
0093     PWRAP_DEW_CRC_VAL,
0094     PWRAP_DEW_MON_GRP_SEL,
0095     PWRAP_DEW_CIPHER_KEY_SEL,
0096     PWRAP_DEW_CIPHER_IV_SEL,
0097     PWRAP_DEW_CIPHER_RDY,
0098     PWRAP_DEW_CIPHER_MODE,
0099     PWRAP_DEW_CIPHER_SWRST,
0100 
0101     /* MT6323 only regs */
0102     PWRAP_DEW_CIPHER_EN,
0103     PWRAP_DEW_RDDMY_NO,
0104 
0105     /* MT6358 only regs */
0106     PWRAP_SMT_CON1,
0107     PWRAP_DRV_CON1,
0108     PWRAP_FILTER_CON0,
0109     PWRAP_GPIO_PULLEN0_CLR,
0110     PWRAP_RG_SPI_CON0,
0111     PWRAP_RG_SPI_RECORD0,
0112     PWRAP_RG_SPI_CON2,
0113     PWRAP_RG_SPI_CON3,
0114     PWRAP_RG_SPI_CON4,
0115     PWRAP_RG_SPI_CON5,
0116     PWRAP_RG_SPI_CON6,
0117     PWRAP_RG_SPI_CON7,
0118     PWRAP_RG_SPI_CON8,
0119     PWRAP_RG_SPI_CON13,
0120     PWRAP_SPISLV_KEY,
0121 
0122     /* MT6359 only regs */
0123     PWRAP_DEW_CRC_SWRST,
0124     PWRAP_DEW_RG_EN_RECORD,
0125     PWRAP_DEW_RECORD_CMD0,
0126     PWRAP_DEW_RECORD_CMD1,
0127     PWRAP_DEW_RECORD_CMD2,
0128     PWRAP_DEW_RECORD_CMD3,
0129     PWRAP_DEW_RECORD_CMD4,
0130     PWRAP_DEW_RECORD_CMD5,
0131     PWRAP_DEW_RECORD_WDATA0,
0132     PWRAP_DEW_RECORD_WDATA1,
0133     PWRAP_DEW_RECORD_WDATA2,
0134     PWRAP_DEW_RECORD_WDATA3,
0135     PWRAP_DEW_RECORD_WDATA4,
0136     PWRAP_DEW_RECORD_WDATA5,
0137     PWRAP_DEW_RG_ADDR_TARGET,
0138     PWRAP_DEW_RG_ADDR_MASK,
0139     PWRAP_DEW_RG_WDATA_TARGET,
0140     PWRAP_DEW_RG_WDATA_MASK,
0141     PWRAP_DEW_RG_SPI_RECORD_CLR,
0142     PWRAP_DEW_RG_CMD_ALERT_CLR,
0143 
0144     /* MT6397 only regs */
0145     PWRAP_DEW_EVENT_OUT_EN,
0146     PWRAP_DEW_EVENT_SRC_EN,
0147     PWRAP_DEW_EVENT_SRC,
0148     PWRAP_DEW_EVENT_FLAG,
0149     PWRAP_DEW_MON_FLAG_SEL,
0150     PWRAP_DEW_EVENT_TEST,
0151     PWRAP_DEW_CIPHER_LOAD,
0152     PWRAP_DEW_CIPHER_START,
0153 };
0154 
0155 static const u32 mt6323_regs[] = {
0156     [PWRAP_DEW_BASE] =      0x0000,
0157     [PWRAP_DEW_DIO_EN] =        0x018a,
0158     [PWRAP_DEW_READ_TEST] =     0x018c,
0159     [PWRAP_DEW_WRITE_TEST] =    0x018e,
0160     [PWRAP_DEW_CRC_EN] =        0x0192,
0161     [PWRAP_DEW_CRC_VAL] =       0x0194,
0162     [PWRAP_DEW_MON_GRP_SEL] =   0x0196,
0163     [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0198,
0164     [PWRAP_DEW_CIPHER_IV_SEL] = 0x019a,
0165     [PWRAP_DEW_CIPHER_EN] =     0x019c,
0166     [PWRAP_DEW_CIPHER_RDY] =    0x019e,
0167     [PWRAP_DEW_CIPHER_MODE] =   0x01a0,
0168     [PWRAP_DEW_CIPHER_SWRST] =  0x01a2,
0169     [PWRAP_DEW_RDDMY_NO] =      0x01a4,
0170 };
0171 
0172 static const u32 mt6351_regs[] = {
0173     [PWRAP_DEW_DIO_EN] =        0x02F2,
0174     [PWRAP_DEW_READ_TEST] =     0x02F4,
0175     [PWRAP_DEW_WRITE_TEST] =    0x02F6,
0176     [PWRAP_DEW_CRC_EN] =        0x02FA,
0177     [PWRAP_DEW_CRC_VAL] =       0x02FC,
0178     [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0300,
0179     [PWRAP_DEW_CIPHER_IV_SEL] = 0x0302,
0180     [PWRAP_DEW_CIPHER_EN] =     0x0304,
0181     [PWRAP_DEW_CIPHER_RDY] =    0x0306,
0182     [PWRAP_DEW_CIPHER_MODE] =   0x0308,
0183     [PWRAP_DEW_CIPHER_SWRST] =  0x030A,
0184     [PWRAP_DEW_RDDMY_NO] =      0x030C,
0185 };
0186 
0187 static const u32 mt6357_regs[] = {
0188     [PWRAP_DEW_DIO_EN] =            0x040A,
0189     [PWRAP_DEW_READ_TEST] =         0x040C,
0190     [PWRAP_DEW_WRITE_TEST] =        0x040E,
0191     [PWRAP_DEW_CRC_EN] =            0x0412,
0192     [PWRAP_DEW_CRC_VAL] =           0x0414,
0193     [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
0194     [PWRAP_DEW_CIPHER_IV_SEL] =     0x041A,
0195     [PWRAP_DEW_CIPHER_EN] =         0x041C,
0196     [PWRAP_DEW_CIPHER_RDY] =        0x041E,
0197     [PWRAP_DEW_CIPHER_MODE] =       0x0420,
0198     [PWRAP_DEW_CIPHER_SWRST] =      0x0422,
0199     [PWRAP_DEW_RDDMY_NO] =          0x0424,
0200 };
0201 
0202 static const u32 mt6358_regs[] = {
0203     [PWRAP_SMT_CON1] =      0x0030,
0204     [PWRAP_DRV_CON1] =      0x0038,
0205     [PWRAP_FILTER_CON0] =       0x0040,
0206     [PWRAP_GPIO_PULLEN0_CLR] =  0x0098,
0207     [PWRAP_RG_SPI_CON0] =       0x0408,
0208     [PWRAP_RG_SPI_RECORD0] =    0x040a,
0209     [PWRAP_DEW_DIO_EN] =        0x040c,
0210     [PWRAP_DEW_READ_TEST]   =   0x040e,
0211     [PWRAP_DEW_WRITE_TEST]  =   0x0410,
0212     [PWRAP_DEW_CRC_EN] =        0x0414,
0213     [PWRAP_DEW_CIPHER_KEY_SEL] =    0x041a,
0214     [PWRAP_DEW_CIPHER_IV_SEL] = 0x041c,
0215     [PWRAP_DEW_CIPHER_EN]   =   0x041e,
0216     [PWRAP_DEW_CIPHER_RDY] =    0x0420,
0217     [PWRAP_DEW_CIPHER_MODE] =   0x0422,
0218     [PWRAP_DEW_CIPHER_SWRST] =  0x0424,
0219     [PWRAP_RG_SPI_CON2] =       0x0432,
0220     [PWRAP_RG_SPI_CON3] =       0x0434,
0221     [PWRAP_RG_SPI_CON4] =       0x0436,
0222     [PWRAP_RG_SPI_CON5] =       0x0438,
0223     [PWRAP_RG_SPI_CON6] =       0x043a,
0224     [PWRAP_RG_SPI_CON7] =       0x043c,
0225     [PWRAP_RG_SPI_CON8] =       0x043e,
0226     [PWRAP_RG_SPI_CON13] =      0x0448,
0227     [PWRAP_SPISLV_KEY] =        0x044a,
0228 };
0229 
0230 static const u32 mt6359_regs[] = {
0231     [PWRAP_DEW_RG_EN_RECORD] =  0x040a,
0232     [PWRAP_DEW_DIO_EN] =        0x040c,
0233     [PWRAP_DEW_READ_TEST] =     0x040e,
0234     [PWRAP_DEW_WRITE_TEST] =    0x0410,
0235     [PWRAP_DEW_CRC_SWRST] =     0x0412,
0236     [PWRAP_DEW_CRC_EN] =        0x0414,
0237     [PWRAP_DEW_CRC_VAL] =       0x0416,
0238     [PWRAP_DEW_CIPHER_KEY_SEL] =    0x0418,
0239     [PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
0240     [PWRAP_DEW_CIPHER_EN] =     0x041c,
0241     [PWRAP_DEW_CIPHER_RDY] =    0x041e,
0242     [PWRAP_DEW_CIPHER_MODE] =   0x0420,
0243     [PWRAP_DEW_CIPHER_SWRST] =  0x0422,
0244     [PWRAP_DEW_RDDMY_NO] =      0x0424,
0245     [PWRAP_DEW_RECORD_CMD0] =   0x0428,
0246     [PWRAP_DEW_RECORD_CMD1] =   0x042a,
0247     [PWRAP_DEW_RECORD_CMD2] =   0x042c,
0248     [PWRAP_DEW_RECORD_CMD3] =   0x042e,
0249     [PWRAP_DEW_RECORD_CMD4] =   0x0430,
0250     [PWRAP_DEW_RECORD_CMD5] =   0x0432,
0251     [PWRAP_DEW_RECORD_WDATA0] = 0x0434,
0252     [PWRAP_DEW_RECORD_WDATA1] = 0x0436,
0253     [PWRAP_DEW_RECORD_WDATA2] = 0x0438,
0254     [PWRAP_DEW_RECORD_WDATA3] = 0x043a,
0255     [PWRAP_DEW_RECORD_WDATA4] = 0x043c,
0256     [PWRAP_DEW_RECORD_WDATA5] = 0x043e,
0257     [PWRAP_DEW_RG_ADDR_TARGET] =    0x0440,
0258     [PWRAP_DEW_RG_ADDR_MASK] =  0x0442,
0259     [PWRAP_DEW_RG_WDATA_TARGET] =   0x0444,
0260     [PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
0261     [PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
0262     [PWRAP_DEW_RG_CMD_ALERT_CLR] =  0x0448,
0263     [PWRAP_SPISLV_KEY] =        0x044a,
0264 };
0265 
0266 static const u32 mt6397_regs[] = {
0267     [PWRAP_DEW_BASE] =      0xbc00,
0268     [PWRAP_DEW_EVENT_OUT_EN] =  0xbc00,
0269     [PWRAP_DEW_DIO_EN] =        0xbc02,
0270     [PWRAP_DEW_EVENT_SRC_EN] =  0xbc04,
0271     [PWRAP_DEW_EVENT_SRC] =     0xbc06,
0272     [PWRAP_DEW_EVENT_FLAG] =    0xbc08,
0273     [PWRAP_DEW_READ_TEST] =     0xbc0a,
0274     [PWRAP_DEW_WRITE_TEST] =    0xbc0c,
0275     [PWRAP_DEW_CRC_EN] =        0xbc0e,
0276     [PWRAP_DEW_CRC_VAL] =       0xbc10,
0277     [PWRAP_DEW_MON_GRP_SEL] =   0xbc12,
0278     [PWRAP_DEW_MON_FLAG_SEL] =  0xbc14,
0279     [PWRAP_DEW_EVENT_TEST] =    0xbc16,
0280     [PWRAP_DEW_CIPHER_KEY_SEL] =    0xbc18,
0281     [PWRAP_DEW_CIPHER_IV_SEL] = 0xbc1a,
0282     [PWRAP_DEW_CIPHER_LOAD] =   0xbc1c,
0283     [PWRAP_DEW_CIPHER_START] =  0xbc1e,
0284     [PWRAP_DEW_CIPHER_RDY] =    0xbc20,
0285     [PWRAP_DEW_CIPHER_MODE] =   0xbc22,
0286     [PWRAP_DEW_CIPHER_SWRST] =  0xbc24,
0287 };
0288 
0289 enum pwrap_regs {
0290     PWRAP_MUX_SEL,
0291     PWRAP_WRAP_EN,
0292     PWRAP_DIO_EN,
0293     PWRAP_SIDLY,
0294     PWRAP_CSHEXT_WRITE,
0295     PWRAP_CSHEXT_READ,
0296     PWRAP_CSLEXT_START,
0297     PWRAP_CSLEXT_END,
0298     PWRAP_STAUPD_PRD,
0299     PWRAP_STAUPD_GRPEN,
0300     PWRAP_STAUPD_MAN_TRIG,
0301     PWRAP_STAUPD_STA,
0302     PWRAP_WRAP_STA,
0303     PWRAP_HARB_INIT,
0304     PWRAP_HARB_HPRIO,
0305     PWRAP_HIPRIO_ARB_EN,
0306     PWRAP_HARB_STA0,
0307     PWRAP_HARB_STA1,
0308     PWRAP_MAN_EN,
0309     PWRAP_MAN_CMD,
0310     PWRAP_MAN_RDATA,
0311     PWRAP_MAN_VLDCLR,
0312     PWRAP_WACS0_EN,
0313     PWRAP_INIT_DONE0,
0314     PWRAP_WACS0_CMD,
0315     PWRAP_WACS0_RDATA,
0316     PWRAP_WACS0_VLDCLR,
0317     PWRAP_WACS1_EN,
0318     PWRAP_INIT_DONE1,
0319     PWRAP_WACS1_CMD,
0320     PWRAP_WACS1_RDATA,
0321     PWRAP_WACS1_VLDCLR,
0322     PWRAP_WACS2_EN,
0323     PWRAP_INIT_DONE2,
0324     PWRAP_WACS2_CMD,
0325     PWRAP_WACS2_RDATA,
0326     PWRAP_WACS2_VLDCLR,
0327     PWRAP_INT_EN,
0328     PWRAP_INT_FLG_RAW,
0329     PWRAP_INT_FLG,
0330     PWRAP_INT_CLR,
0331     PWRAP_SIG_ADR,
0332     PWRAP_SIG_MODE,
0333     PWRAP_SIG_VALUE,
0334     PWRAP_SIG_ERRVAL,
0335     PWRAP_CRC_EN,
0336     PWRAP_TIMER_EN,
0337     PWRAP_TIMER_STA,
0338     PWRAP_WDT_UNIT,
0339     PWRAP_WDT_SRC_EN,
0340     PWRAP_WDT_FLG,
0341     PWRAP_DEBUG_INT_SEL,
0342     PWRAP_CIPHER_KEY_SEL,
0343     PWRAP_CIPHER_IV_SEL,
0344     PWRAP_CIPHER_RDY,
0345     PWRAP_CIPHER_MODE,
0346     PWRAP_CIPHER_SWRST,
0347     PWRAP_DCM_EN,
0348     PWRAP_DCM_DBC_PRD,
0349     PWRAP_EINT_STA0_ADR,
0350     PWRAP_EINT_STA1_ADR,
0351     PWRAP_SWINF_2_WDATA_31_0,
0352     PWRAP_SWINF_2_RDATA_31_0,
0353 
0354     /* MT2701 only regs */
0355     PWRAP_ADC_CMD_ADDR,
0356     PWRAP_PWRAP_ADC_CMD,
0357     PWRAP_ADC_RDY_ADDR,
0358     PWRAP_ADC_RDATA_ADDR1,
0359     PWRAP_ADC_RDATA_ADDR2,
0360 
0361     /* MT7622 only regs */
0362     PWRAP_STA,
0363     PWRAP_CLR,
0364     PWRAP_DVFS_ADR8,
0365     PWRAP_DVFS_WDATA8,
0366     PWRAP_DVFS_ADR9,
0367     PWRAP_DVFS_WDATA9,
0368     PWRAP_DVFS_ADR10,
0369     PWRAP_DVFS_WDATA10,
0370     PWRAP_DVFS_ADR11,
0371     PWRAP_DVFS_WDATA11,
0372     PWRAP_DVFS_ADR12,
0373     PWRAP_DVFS_WDATA12,
0374     PWRAP_DVFS_ADR13,
0375     PWRAP_DVFS_WDATA13,
0376     PWRAP_DVFS_ADR14,
0377     PWRAP_DVFS_WDATA14,
0378     PWRAP_DVFS_ADR15,
0379     PWRAP_DVFS_WDATA15,
0380     PWRAP_EXT_CK,
0381     PWRAP_ADC_RDATA_ADDR,
0382     PWRAP_GPS_STA,
0383     PWRAP_SW_RST,
0384     PWRAP_DVFS_STEP_CTRL0,
0385     PWRAP_DVFS_STEP_CTRL1,
0386     PWRAP_DVFS_STEP_CTRL2,
0387     PWRAP_SPI2_CTRL,
0388 
0389     /* MT8135 only regs */
0390     PWRAP_CSHEXT,
0391     PWRAP_EVENT_IN_EN,
0392     PWRAP_EVENT_DST_EN,
0393     PWRAP_RRARB_INIT,
0394     PWRAP_RRARB_EN,
0395     PWRAP_RRARB_STA0,
0396     PWRAP_RRARB_STA1,
0397     PWRAP_EVENT_STA,
0398     PWRAP_EVENT_STACLR,
0399     PWRAP_CIPHER_LOAD,
0400     PWRAP_CIPHER_START,
0401 
0402     /* MT8173 only regs */
0403     PWRAP_RDDMY,
0404     PWRAP_SI_CK_CON,
0405     PWRAP_DVFS_ADR0,
0406     PWRAP_DVFS_WDATA0,
0407     PWRAP_DVFS_ADR1,
0408     PWRAP_DVFS_WDATA1,
0409     PWRAP_DVFS_ADR2,
0410     PWRAP_DVFS_WDATA2,
0411     PWRAP_DVFS_ADR3,
0412     PWRAP_DVFS_WDATA3,
0413     PWRAP_DVFS_ADR4,
0414     PWRAP_DVFS_WDATA4,
0415     PWRAP_DVFS_ADR5,
0416     PWRAP_DVFS_WDATA5,
0417     PWRAP_DVFS_ADR6,
0418     PWRAP_DVFS_WDATA6,
0419     PWRAP_DVFS_ADR7,
0420     PWRAP_DVFS_WDATA7,
0421     PWRAP_SPMINF_STA,
0422     PWRAP_CIPHER_EN,
0423 
0424     /* MT8183 only regs */
0425     PWRAP_SI_SAMPLE_CTRL,
0426     PWRAP_CSLEXT_WRITE,
0427     PWRAP_CSLEXT_READ,
0428     PWRAP_EXT_CK_WRITE,
0429     PWRAP_STAUPD_CTRL,
0430     PWRAP_WACS_P2P_EN,
0431     PWRAP_INIT_DONE_P2P,
0432     PWRAP_WACS_MD32_EN,
0433     PWRAP_INIT_DONE_MD32,
0434     PWRAP_INT1_EN,
0435     PWRAP_INT1_FLG,
0436     PWRAP_INT1_CLR,
0437     PWRAP_WDT_SRC_EN_1,
0438     PWRAP_INT_GPS_AUXADC_CMD_ADDR,
0439     PWRAP_INT_GPS_AUXADC_CMD,
0440     PWRAP_INT_GPS_AUXADC_RDATA_ADDR,
0441     PWRAP_EXT_GPS_AUXADC_RDATA_ADDR,
0442     PWRAP_GPSINF_0_STA,
0443     PWRAP_GPSINF_1_STA,
0444 
0445     /* MT8516 only regs */
0446     PWRAP_OP_TYPE,
0447     PWRAP_MSB_FIRST,
0448 };
0449 
0450 static int mt2701_regs[] = {
0451     [PWRAP_MUX_SEL] =       0x0,
0452     [PWRAP_WRAP_EN] =       0x4,
0453     [PWRAP_DIO_EN] =        0x8,
0454     [PWRAP_SIDLY] =         0xc,
0455     [PWRAP_RDDMY] =         0x18,
0456     [PWRAP_SI_CK_CON] =     0x1c,
0457     [PWRAP_CSHEXT_WRITE] =      0x20,
0458     [PWRAP_CSHEXT_READ] =       0x24,
0459     [PWRAP_CSLEXT_START] =      0x28,
0460     [PWRAP_CSLEXT_END] =        0x2c,
0461     [PWRAP_STAUPD_PRD] =        0x30,
0462     [PWRAP_STAUPD_GRPEN] =      0x34,
0463     [PWRAP_STAUPD_MAN_TRIG] =   0x38,
0464     [PWRAP_STAUPD_STA] =        0x3c,
0465     [PWRAP_WRAP_STA] =      0x44,
0466     [PWRAP_HARB_INIT] =     0x48,
0467     [PWRAP_HARB_HPRIO] =        0x4c,
0468     [PWRAP_HIPRIO_ARB_EN] =     0x50,
0469     [PWRAP_HARB_STA0] =     0x54,
0470     [PWRAP_HARB_STA1] =     0x58,
0471     [PWRAP_MAN_EN] =        0x5c,
0472     [PWRAP_MAN_CMD] =       0x60,
0473     [PWRAP_MAN_RDATA] =     0x64,
0474     [PWRAP_MAN_VLDCLR] =        0x68,
0475     [PWRAP_WACS0_EN] =      0x6c,
0476     [PWRAP_INIT_DONE0] =        0x70,
0477     [PWRAP_WACS0_CMD] =     0x74,
0478     [PWRAP_WACS0_RDATA] =       0x78,
0479     [PWRAP_WACS0_VLDCLR] =      0x7c,
0480     [PWRAP_WACS1_EN] =      0x80,
0481     [PWRAP_INIT_DONE1] =        0x84,
0482     [PWRAP_WACS1_CMD] =     0x88,
0483     [PWRAP_WACS1_RDATA] =       0x8c,
0484     [PWRAP_WACS1_VLDCLR] =      0x90,
0485     [PWRAP_WACS2_EN] =      0x94,
0486     [PWRAP_INIT_DONE2] =        0x98,
0487     [PWRAP_WACS2_CMD] =     0x9c,
0488     [PWRAP_WACS2_RDATA] =       0xa0,
0489     [PWRAP_WACS2_VLDCLR] =      0xa4,
0490     [PWRAP_INT_EN] =        0xa8,
0491     [PWRAP_INT_FLG_RAW] =       0xac,
0492     [PWRAP_INT_FLG] =       0xb0,
0493     [PWRAP_INT_CLR] =       0xb4,
0494     [PWRAP_SIG_ADR] =       0xb8,
0495     [PWRAP_SIG_MODE] =      0xbc,
0496     [PWRAP_SIG_VALUE] =     0xc0,
0497     [PWRAP_SIG_ERRVAL] =        0xc4,
0498     [PWRAP_CRC_EN] =        0xc8,
0499     [PWRAP_TIMER_EN] =      0xcc,
0500     [PWRAP_TIMER_STA] =     0xd0,
0501     [PWRAP_WDT_UNIT] =      0xd4,
0502     [PWRAP_WDT_SRC_EN] =        0xd8,
0503     [PWRAP_WDT_FLG] =       0xdc,
0504     [PWRAP_DEBUG_INT_SEL] =     0xe0,
0505     [PWRAP_DVFS_ADR0] =     0xe4,
0506     [PWRAP_DVFS_WDATA0] =       0xe8,
0507     [PWRAP_DVFS_ADR1] =     0xec,
0508     [PWRAP_DVFS_WDATA1] =       0xf0,
0509     [PWRAP_DVFS_ADR2] =     0xf4,
0510     [PWRAP_DVFS_WDATA2] =       0xf8,
0511     [PWRAP_DVFS_ADR3] =     0xfc,
0512     [PWRAP_DVFS_WDATA3] =       0x100,
0513     [PWRAP_DVFS_ADR4] =     0x104,
0514     [PWRAP_DVFS_WDATA4] =       0x108,
0515     [PWRAP_DVFS_ADR5] =     0x10c,
0516     [PWRAP_DVFS_WDATA5] =       0x110,
0517     [PWRAP_DVFS_ADR6] =     0x114,
0518     [PWRAP_DVFS_WDATA6] =       0x118,
0519     [PWRAP_DVFS_ADR7] =     0x11c,
0520     [PWRAP_DVFS_WDATA7] =       0x120,
0521     [PWRAP_CIPHER_KEY_SEL] =    0x124,
0522     [PWRAP_CIPHER_IV_SEL] =     0x128,
0523     [PWRAP_CIPHER_EN] =     0x12c,
0524     [PWRAP_CIPHER_RDY] =        0x130,
0525     [PWRAP_CIPHER_MODE] =       0x134,
0526     [PWRAP_CIPHER_SWRST] =      0x138,
0527     [PWRAP_DCM_EN] =        0x13c,
0528     [PWRAP_DCM_DBC_PRD] =       0x140,
0529     [PWRAP_ADC_CMD_ADDR] =      0x144,
0530     [PWRAP_PWRAP_ADC_CMD] =     0x148,
0531     [PWRAP_ADC_RDY_ADDR] =      0x14c,
0532     [PWRAP_ADC_RDATA_ADDR1] =   0x150,
0533     [PWRAP_ADC_RDATA_ADDR2] =   0x154,
0534 };
0535 
0536 static int mt6765_regs[] = {
0537     [PWRAP_MUX_SEL] =       0x0,
0538     [PWRAP_WRAP_EN] =       0x4,
0539     [PWRAP_DIO_EN] =        0x8,
0540     [PWRAP_RDDMY] =         0x20,
0541     [PWRAP_CSHEXT_WRITE] =      0x24,
0542     [PWRAP_CSHEXT_READ] =       0x28,
0543     [PWRAP_CSLEXT_START] =      0x2C,
0544     [PWRAP_CSLEXT_END] =        0x30,
0545     [PWRAP_STAUPD_PRD] =        0x3C,
0546     [PWRAP_HARB_HPRIO] =        0x68,
0547     [PWRAP_HIPRIO_ARB_EN] =     0x6C,
0548     [PWRAP_MAN_EN] =        0x7C,
0549     [PWRAP_MAN_CMD] =       0x80,
0550     [PWRAP_WACS0_EN] =      0x8C,
0551     [PWRAP_WACS1_EN] =      0x94,
0552     [PWRAP_WACS2_EN] =      0x9C,
0553     [PWRAP_INIT_DONE2] =        0xA0,
0554     [PWRAP_WACS2_CMD] =     0xC20,
0555     [PWRAP_WACS2_RDATA] =       0xC24,
0556     [PWRAP_WACS2_VLDCLR] =      0xC28,
0557     [PWRAP_INT_EN] =        0xB4,
0558     [PWRAP_INT_FLG_RAW] =       0xB8,
0559     [PWRAP_INT_FLG] =       0xBC,
0560     [PWRAP_INT_CLR] =       0xC0,
0561     [PWRAP_TIMER_EN] =      0xE8,
0562     [PWRAP_WDT_UNIT] =      0xF0,
0563     [PWRAP_WDT_SRC_EN] =        0xF4,
0564     [PWRAP_DCM_EN] =        0x1DC,
0565     [PWRAP_DCM_DBC_PRD] =       0x1E0,
0566 };
0567 
0568 static int mt6779_regs[] = {
0569     [PWRAP_MUX_SEL] =       0x0,
0570     [PWRAP_WRAP_EN] =       0x4,
0571     [PWRAP_DIO_EN] =        0x8,
0572     [PWRAP_RDDMY] =         0x20,
0573     [PWRAP_CSHEXT_WRITE] =      0x24,
0574     [PWRAP_CSHEXT_READ] =       0x28,
0575     [PWRAP_CSLEXT_WRITE] =      0x2C,
0576     [PWRAP_CSLEXT_READ] =       0x30,
0577     [PWRAP_EXT_CK_WRITE] =      0x34,
0578     [PWRAP_STAUPD_CTRL] =       0x3C,
0579     [PWRAP_STAUPD_GRPEN] =      0x40,
0580     [PWRAP_EINT_STA0_ADR] =     0x44,
0581     [PWRAP_HARB_HPRIO] =        0x68,
0582     [PWRAP_HIPRIO_ARB_EN] =     0x6C,
0583     [PWRAP_MAN_EN] =        0x7C,
0584     [PWRAP_MAN_CMD] =       0x80,
0585     [PWRAP_WACS0_EN] =      0x8C,
0586     [PWRAP_INIT_DONE0] =        0x90,
0587     [PWRAP_WACS1_EN] =      0x94,
0588     [PWRAP_WACS2_EN] =      0x9C,
0589     [PWRAP_INIT_DONE1] =        0x98,
0590     [PWRAP_INIT_DONE2] =        0xA0,
0591     [PWRAP_INT_EN] =        0xBC,
0592     [PWRAP_INT_FLG_RAW] =       0xC0,
0593     [PWRAP_INT_FLG] =       0xC4,
0594     [PWRAP_INT_CLR] =       0xC8,
0595     [PWRAP_INT1_EN] =       0xCC,
0596     [PWRAP_INT1_FLG] =      0xD4,
0597     [PWRAP_INT1_CLR] =      0xD8,
0598     [PWRAP_TIMER_EN] =      0xF0,
0599     [PWRAP_WDT_UNIT] =      0xF8,
0600     [PWRAP_WDT_SRC_EN] =        0xFC,
0601     [PWRAP_WDT_SRC_EN_1] =      0x100,
0602     [PWRAP_WACS2_CMD] =     0xC20,
0603     [PWRAP_WACS2_RDATA] =       0xC24,
0604     [PWRAP_WACS2_VLDCLR] =      0xC28,
0605 };
0606 
0607 static int mt6797_regs[] = {
0608     [PWRAP_MUX_SEL] =       0x0,
0609     [PWRAP_WRAP_EN] =       0x4,
0610     [PWRAP_DIO_EN] =        0x8,
0611     [PWRAP_SIDLY] =         0xC,
0612     [PWRAP_RDDMY] =         0x10,
0613     [PWRAP_CSHEXT_WRITE] =      0x18,
0614     [PWRAP_CSHEXT_READ] =       0x1C,
0615     [PWRAP_CSLEXT_START] =      0x20,
0616     [PWRAP_CSLEXT_END] =        0x24,
0617     [PWRAP_STAUPD_PRD] =        0x28,
0618     [PWRAP_HARB_HPRIO] =        0x50,
0619     [PWRAP_HIPRIO_ARB_EN] =     0x54,
0620     [PWRAP_MAN_EN] =        0x60,
0621     [PWRAP_MAN_CMD] =       0x64,
0622     [PWRAP_WACS0_EN] =      0x70,
0623     [PWRAP_WACS1_EN] =      0x84,
0624     [PWRAP_WACS2_EN] =      0x98,
0625     [PWRAP_INIT_DONE2] =        0x9C,
0626     [PWRAP_WACS2_CMD] =     0xA0,
0627     [PWRAP_WACS2_RDATA] =       0xA4,
0628     [PWRAP_WACS2_VLDCLR] =      0xA8,
0629     [PWRAP_INT_EN] =        0xC0,
0630     [PWRAP_INT_FLG_RAW] =       0xC4,
0631     [PWRAP_INT_FLG] =       0xC8,
0632     [PWRAP_INT_CLR] =       0xCC,
0633     [PWRAP_TIMER_EN] =      0xF4,
0634     [PWRAP_WDT_UNIT] =      0xFC,
0635     [PWRAP_WDT_SRC_EN] =        0x100,
0636     [PWRAP_DCM_EN] =        0x1CC,
0637     [PWRAP_DCM_DBC_PRD] =       0x1D4,
0638 };
0639 
0640 static int mt6873_regs[] = {
0641     [PWRAP_INIT_DONE2] =        0x0,
0642     [PWRAP_TIMER_EN] =      0x3E0,
0643     [PWRAP_INT_EN] =        0x448,
0644     [PWRAP_WACS2_CMD] =     0xC80,
0645     [PWRAP_SWINF_2_WDATA_31_0] =    0xC84,
0646     [PWRAP_SWINF_2_RDATA_31_0] =    0xC94,
0647     [PWRAP_WACS2_VLDCLR] =      0xCA4,
0648     [PWRAP_WACS2_RDATA] =       0xCA8,
0649 };
0650 
0651 static int mt7622_regs[] = {
0652     [PWRAP_MUX_SEL] =       0x0,
0653     [PWRAP_WRAP_EN] =       0x4,
0654     [PWRAP_DIO_EN] =        0x8,
0655     [PWRAP_SIDLY] =         0xC,
0656     [PWRAP_RDDMY] =         0x10,
0657     [PWRAP_SI_CK_CON] =     0x14,
0658     [PWRAP_CSHEXT_WRITE] =      0x18,
0659     [PWRAP_CSHEXT_READ] =       0x1C,
0660     [PWRAP_CSLEXT_START] =      0x20,
0661     [PWRAP_CSLEXT_END] =        0x24,
0662     [PWRAP_STAUPD_PRD] =        0x28,
0663     [PWRAP_STAUPD_GRPEN] =      0x2C,
0664     [PWRAP_EINT_STA0_ADR] =     0x30,
0665     [PWRAP_EINT_STA1_ADR] =     0x34,
0666     [PWRAP_STA] =           0x38,
0667     [PWRAP_CLR] =           0x3C,
0668     [PWRAP_STAUPD_MAN_TRIG] =   0x40,
0669     [PWRAP_STAUPD_STA] =        0x44,
0670     [PWRAP_WRAP_STA] =      0x48,
0671     [PWRAP_HARB_INIT] =     0x4C,
0672     [PWRAP_HARB_HPRIO] =        0x50,
0673     [PWRAP_HIPRIO_ARB_EN] =     0x54,
0674     [PWRAP_HARB_STA0] =     0x58,
0675     [PWRAP_HARB_STA1] =     0x5C,
0676     [PWRAP_MAN_EN] =        0x60,
0677     [PWRAP_MAN_CMD] =       0x64,
0678     [PWRAP_MAN_RDATA] =     0x68,
0679     [PWRAP_MAN_VLDCLR] =        0x6C,
0680     [PWRAP_WACS0_EN] =      0x70,
0681     [PWRAP_INIT_DONE0] =        0x74,
0682     [PWRAP_WACS0_CMD] =     0x78,
0683     [PWRAP_WACS0_RDATA] =       0x7C,
0684     [PWRAP_WACS0_VLDCLR] =      0x80,
0685     [PWRAP_WACS1_EN] =      0x84,
0686     [PWRAP_INIT_DONE1] =        0x88,
0687     [PWRAP_WACS1_CMD] =     0x8C,
0688     [PWRAP_WACS1_RDATA] =       0x90,
0689     [PWRAP_WACS1_VLDCLR] =      0x94,
0690     [PWRAP_WACS2_EN] =      0x98,
0691     [PWRAP_INIT_DONE2] =        0x9C,
0692     [PWRAP_WACS2_CMD] =     0xA0,
0693     [PWRAP_WACS2_RDATA] =       0xA4,
0694     [PWRAP_WACS2_VLDCLR] =      0xA8,
0695     [PWRAP_INT_EN] =        0xAC,
0696     [PWRAP_INT_FLG_RAW] =       0xB0,
0697     [PWRAP_INT_FLG] =       0xB4,
0698     [PWRAP_INT_CLR] =       0xB8,
0699     [PWRAP_SIG_ADR] =       0xBC,
0700     [PWRAP_SIG_MODE] =      0xC0,
0701     [PWRAP_SIG_VALUE] =     0xC4,
0702     [PWRAP_SIG_ERRVAL] =        0xC8,
0703     [PWRAP_CRC_EN] =        0xCC,
0704     [PWRAP_TIMER_EN] =      0xD0,
0705     [PWRAP_TIMER_STA] =     0xD4,
0706     [PWRAP_WDT_UNIT] =      0xD8,
0707     [PWRAP_WDT_SRC_EN] =        0xDC,
0708     [PWRAP_WDT_FLG] =       0xE0,
0709     [PWRAP_DEBUG_INT_SEL] =     0xE4,
0710     [PWRAP_DVFS_ADR0] =     0xE8,
0711     [PWRAP_DVFS_WDATA0] =       0xEC,
0712     [PWRAP_DVFS_ADR1] =     0xF0,
0713     [PWRAP_DVFS_WDATA1] =       0xF4,
0714     [PWRAP_DVFS_ADR2] =     0xF8,
0715     [PWRAP_DVFS_WDATA2] =       0xFC,
0716     [PWRAP_DVFS_ADR3] =     0x100,
0717     [PWRAP_DVFS_WDATA3] =       0x104,
0718     [PWRAP_DVFS_ADR4] =     0x108,
0719     [PWRAP_DVFS_WDATA4] =       0x10C,
0720     [PWRAP_DVFS_ADR5] =     0x110,
0721     [PWRAP_DVFS_WDATA5] =       0x114,
0722     [PWRAP_DVFS_ADR6] =     0x118,
0723     [PWRAP_DVFS_WDATA6] =       0x11C,
0724     [PWRAP_DVFS_ADR7] =     0x120,
0725     [PWRAP_DVFS_WDATA7] =       0x124,
0726     [PWRAP_DVFS_ADR8] =     0x128,
0727     [PWRAP_DVFS_WDATA8] =       0x12C,
0728     [PWRAP_DVFS_ADR9] =     0x130,
0729     [PWRAP_DVFS_WDATA9] =       0x134,
0730     [PWRAP_DVFS_ADR10] =        0x138,
0731     [PWRAP_DVFS_WDATA10] =      0x13C,
0732     [PWRAP_DVFS_ADR11] =        0x140,
0733     [PWRAP_DVFS_WDATA11] =      0x144,
0734     [PWRAP_DVFS_ADR12] =        0x148,
0735     [PWRAP_DVFS_WDATA12] =      0x14C,
0736     [PWRAP_DVFS_ADR13] =        0x150,
0737     [PWRAP_DVFS_WDATA13] =      0x154,
0738     [PWRAP_DVFS_ADR14] =        0x158,
0739     [PWRAP_DVFS_WDATA14] =      0x15C,
0740     [PWRAP_DVFS_ADR15] =        0x160,
0741     [PWRAP_DVFS_WDATA15] =      0x164,
0742     [PWRAP_SPMINF_STA] =        0x168,
0743     [PWRAP_CIPHER_KEY_SEL] =    0x16C,
0744     [PWRAP_CIPHER_IV_SEL] =     0x170,
0745     [PWRAP_CIPHER_EN] =     0x174,
0746     [PWRAP_CIPHER_RDY] =        0x178,
0747     [PWRAP_CIPHER_MODE] =       0x17C,
0748     [PWRAP_CIPHER_SWRST] =      0x180,
0749     [PWRAP_DCM_EN] =        0x184,
0750     [PWRAP_DCM_DBC_PRD] =       0x188,
0751     [PWRAP_EXT_CK] =        0x18C,
0752     [PWRAP_ADC_CMD_ADDR] =      0x190,
0753     [PWRAP_PWRAP_ADC_CMD] =     0x194,
0754     [PWRAP_ADC_RDATA_ADDR] =    0x198,
0755     [PWRAP_GPS_STA] =       0x19C,
0756     [PWRAP_SW_RST] =        0x1A0,
0757     [PWRAP_DVFS_STEP_CTRL0] =   0x238,
0758     [PWRAP_DVFS_STEP_CTRL1] =   0x23C,
0759     [PWRAP_DVFS_STEP_CTRL2] =   0x240,
0760     [PWRAP_SPI2_CTRL] =     0x244,
0761 };
0762 
0763 static int mt8135_regs[] = {
0764     [PWRAP_MUX_SEL] =       0x0,
0765     [PWRAP_WRAP_EN] =       0x4,
0766     [PWRAP_DIO_EN] =        0x8,
0767     [PWRAP_SIDLY] =         0xc,
0768     [PWRAP_CSHEXT] =        0x10,
0769     [PWRAP_CSHEXT_WRITE] =      0x14,
0770     [PWRAP_CSHEXT_READ] =       0x18,
0771     [PWRAP_CSLEXT_START] =      0x1c,
0772     [PWRAP_CSLEXT_END] =        0x20,
0773     [PWRAP_STAUPD_PRD] =        0x24,
0774     [PWRAP_STAUPD_GRPEN] =      0x28,
0775     [PWRAP_STAUPD_MAN_TRIG] =   0x2c,
0776     [PWRAP_STAUPD_STA] =        0x30,
0777     [PWRAP_EVENT_IN_EN] =       0x34,
0778     [PWRAP_EVENT_DST_EN] =      0x38,
0779     [PWRAP_WRAP_STA] =      0x3c,
0780     [PWRAP_RRARB_INIT] =        0x40,
0781     [PWRAP_RRARB_EN] =      0x44,
0782     [PWRAP_RRARB_STA0] =        0x48,
0783     [PWRAP_RRARB_STA1] =        0x4c,
0784     [PWRAP_HARB_INIT] =     0x50,
0785     [PWRAP_HARB_HPRIO] =        0x54,
0786     [PWRAP_HIPRIO_ARB_EN] =     0x58,
0787     [PWRAP_HARB_STA0] =     0x5c,
0788     [PWRAP_HARB_STA1] =     0x60,
0789     [PWRAP_MAN_EN] =        0x64,
0790     [PWRAP_MAN_CMD] =       0x68,
0791     [PWRAP_MAN_RDATA] =     0x6c,
0792     [PWRAP_MAN_VLDCLR] =        0x70,
0793     [PWRAP_WACS0_EN] =      0x74,
0794     [PWRAP_INIT_DONE0] =        0x78,
0795     [PWRAP_WACS0_CMD] =     0x7c,
0796     [PWRAP_WACS0_RDATA] =       0x80,
0797     [PWRAP_WACS0_VLDCLR] =      0x84,
0798     [PWRAP_WACS1_EN] =      0x88,
0799     [PWRAP_INIT_DONE1] =        0x8c,
0800     [PWRAP_WACS1_CMD] =     0x90,
0801     [PWRAP_WACS1_RDATA] =       0x94,
0802     [PWRAP_WACS1_VLDCLR] =      0x98,
0803     [PWRAP_WACS2_EN] =      0x9c,
0804     [PWRAP_INIT_DONE2] =        0xa0,
0805     [PWRAP_WACS2_CMD] =     0xa4,
0806     [PWRAP_WACS2_RDATA] =       0xa8,
0807     [PWRAP_WACS2_VLDCLR] =      0xac,
0808     [PWRAP_INT_EN] =        0xb0,
0809     [PWRAP_INT_FLG_RAW] =       0xb4,
0810     [PWRAP_INT_FLG] =       0xb8,
0811     [PWRAP_INT_CLR] =       0xbc,
0812     [PWRAP_SIG_ADR] =       0xc0,
0813     [PWRAP_SIG_MODE] =      0xc4,
0814     [PWRAP_SIG_VALUE] =     0xc8,
0815     [PWRAP_SIG_ERRVAL] =        0xcc,
0816     [PWRAP_CRC_EN] =        0xd0,
0817     [PWRAP_EVENT_STA] =     0xd4,
0818     [PWRAP_EVENT_STACLR] =      0xd8,
0819     [PWRAP_TIMER_EN] =      0xdc,
0820     [PWRAP_TIMER_STA] =     0xe0,
0821     [PWRAP_WDT_UNIT] =      0xe4,
0822     [PWRAP_WDT_SRC_EN] =        0xe8,
0823     [PWRAP_WDT_FLG] =       0xec,
0824     [PWRAP_DEBUG_INT_SEL] =     0xf0,
0825     [PWRAP_CIPHER_KEY_SEL] =    0x134,
0826     [PWRAP_CIPHER_IV_SEL] =     0x138,
0827     [PWRAP_CIPHER_LOAD] =       0x13c,
0828     [PWRAP_CIPHER_START] =      0x140,
0829     [PWRAP_CIPHER_RDY] =        0x144,
0830     [PWRAP_CIPHER_MODE] =       0x148,
0831     [PWRAP_CIPHER_SWRST] =      0x14c,
0832     [PWRAP_DCM_EN] =        0x15c,
0833     [PWRAP_DCM_DBC_PRD] =       0x160,
0834 };
0835 
0836 static int mt8173_regs[] = {
0837     [PWRAP_MUX_SEL] =       0x0,
0838     [PWRAP_WRAP_EN] =       0x4,
0839     [PWRAP_DIO_EN] =        0x8,
0840     [PWRAP_SIDLY] =         0xc,
0841     [PWRAP_RDDMY] =         0x10,
0842     [PWRAP_SI_CK_CON] =     0x14,
0843     [PWRAP_CSHEXT_WRITE] =      0x18,
0844     [PWRAP_CSHEXT_READ] =       0x1c,
0845     [PWRAP_CSLEXT_START] =      0x20,
0846     [PWRAP_CSLEXT_END] =        0x24,
0847     [PWRAP_STAUPD_PRD] =        0x28,
0848     [PWRAP_STAUPD_GRPEN] =      0x2c,
0849     [PWRAP_STAUPD_MAN_TRIG] =   0x40,
0850     [PWRAP_STAUPD_STA] =        0x44,
0851     [PWRAP_WRAP_STA] =      0x48,
0852     [PWRAP_HARB_INIT] =     0x4c,
0853     [PWRAP_HARB_HPRIO] =        0x50,
0854     [PWRAP_HIPRIO_ARB_EN] =     0x54,
0855     [PWRAP_HARB_STA0] =     0x58,
0856     [PWRAP_HARB_STA1] =     0x5c,
0857     [PWRAP_MAN_EN] =        0x60,
0858     [PWRAP_MAN_CMD] =       0x64,
0859     [PWRAP_MAN_RDATA] =     0x68,
0860     [PWRAP_MAN_VLDCLR] =        0x6c,
0861     [PWRAP_WACS0_EN] =      0x70,
0862     [PWRAP_INIT_DONE0] =        0x74,
0863     [PWRAP_WACS0_CMD] =     0x78,
0864     [PWRAP_WACS0_RDATA] =       0x7c,
0865     [PWRAP_WACS0_VLDCLR] =      0x80,
0866     [PWRAP_WACS1_EN] =      0x84,
0867     [PWRAP_INIT_DONE1] =        0x88,
0868     [PWRAP_WACS1_CMD] =     0x8c,
0869     [PWRAP_WACS1_RDATA] =       0x90,
0870     [PWRAP_WACS1_VLDCLR] =      0x94,
0871     [PWRAP_WACS2_EN] =      0x98,
0872     [PWRAP_INIT_DONE2] =        0x9c,
0873     [PWRAP_WACS2_CMD] =     0xa0,
0874     [PWRAP_WACS2_RDATA] =       0xa4,
0875     [PWRAP_WACS2_VLDCLR] =      0xa8,
0876     [PWRAP_INT_EN] =        0xac,
0877     [PWRAP_INT_FLG_RAW] =       0xb0,
0878     [PWRAP_INT_FLG] =       0xb4,
0879     [PWRAP_INT_CLR] =       0xb8,
0880     [PWRAP_SIG_ADR] =       0xbc,
0881     [PWRAP_SIG_MODE] =      0xc0,
0882     [PWRAP_SIG_VALUE] =     0xc4,
0883     [PWRAP_SIG_ERRVAL] =        0xc8,
0884     [PWRAP_CRC_EN] =        0xcc,
0885     [PWRAP_TIMER_EN] =      0xd0,
0886     [PWRAP_TIMER_STA] =     0xd4,
0887     [PWRAP_WDT_UNIT] =      0xd8,
0888     [PWRAP_WDT_SRC_EN] =        0xdc,
0889     [PWRAP_WDT_FLG] =       0xe0,
0890     [PWRAP_DEBUG_INT_SEL] =     0xe4,
0891     [PWRAP_DVFS_ADR0] =     0xe8,
0892     [PWRAP_DVFS_WDATA0] =       0xec,
0893     [PWRAP_DVFS_ADR1] =     0xf0,
0894     [PWRAP_DVFS_WDATA1] =       0xf4,
0895     [PWRAP_DVFS_ADR2] =     0xf8,
0896     [PWRAP_DVFS_WDATA2] =       0xfc,
0897     [PWRAP_DVFS_ADR3] =     0x100,
0898     [PWRAP_DVFS_WDATA3] =       0x104,
0899     [PWRAP_DVFS_ADR4] =     0x108,
0900     [PWRAP_DVFS_WDATA4] =       0x10c,
0901     [PWRAP_DVFS_ADR5] =     0x110,
0902     [PWRAP_DVFS_WDATA5] =       0x114,
0903     [PWRAP_DVFS_ADR6] =     0x118,
0904     [PWRAP_DVFS_WDATA6] =       0x11c,
0905     [PWRAP_DVFS_ADR7] =     0x120,
0906     [PWRAP_DVFS_WDATA7] =       0x124,
0907     [PWRAP_SPMINF_STA] =        0x128,
0908     [PWRAP_CIPHER_KEY_SEL] =    0x12c,
0909     [PWRAP_CIPHER_IV_SEL] =     0x130,
0910     [PWRAP_CIPHER_EN] =     0x134,
0911     [PWRAP_CIPHER_RDY] =        0x138,
0912     [PWRAP_CIPHER_MODE] =       0x13c,
0913     [PWRAP_CIPHER_SWRST] =      0x140,
0914     [PWRAP_DCM_EN] =        0x144,
0915     [PWRAP_DCM_DBC_PRD] =       0x148,
0916 };
0917 
0918 static int mt8183_regs[] = {
0919     [PWRAP_MUX_SEL] =           0x0,
0920     [PWRAP_WRAP_EN] =           0x4,
0921     [PWRAP_DIO_EN] =            0x8,
0922     [PWRAP_SI_SAMPLE_CTRL] =        0xC,
0923     [PWRAP_RDDMY] =             0x14,
0924     [PWRAP_CSHEXT_WRITE] =          0x18,
0925     [PWRAP_CSHEXT_READ] =           0x1C,
0926     [PWRAP_CSLEXT_WRITE] =          0x20,
0927     [PWRAP_CSLEXT_READ] =           0x24,
0928     [PWRAP_EXT_CK_WRITE] =          0x28,
0929     [PWRAP_STAUPD_CTRL] =           0x30,
0930     [PWRAP_STAUPD_GRPEN] =          0x34,
0931     [PWRAP_EINT_STA0_ADR] =         0x38,
0932     [PWRAP_HARB_HPRIO] =            0x5C,
0933     [PWRAP_HIPRIO_ARB_EN] =         0x60,
0934     [PWRAP_MAN_EN] =            0x70,
0935     [PWRAP_MAN_CMD] =           0x74,
0936     [PWRAP_WACS0_EN] =          0x80,
0937     [PWRAP_INIT_DONE0] =            0x84,
0938     [PWRAP_WACS1_EN] =          0x88,
0939     [PWRAP_INIT_DONE1] =            0x8C,
0940     [PWRAP_WACS2_EN] =          0x90,
0941     [PWRAP_INIT_DONE2] =            0x94,
0942     [PWRAP_WACS_P2P_EN] =           0xA0,
0943     [PWRAP_INIT_DONE_P2P] =         0xA4,
0944     [PWRAP_WACS_MD32_EN] =          0xA8,
0945     [PWRAP_INIT_DONE_MD32] =        0xAC,
0946     [PWRAP_INT_EN] =            0xB0,
0947     [PWRAP_INT_FLG] =           0xB8,
0948     [PWRAP_INT_CLR] =           0xBC,
0949     [PWRAP_INT1_EN] =           0xC0,
0950     [PWRAP_INT1_FLG] =          0xC8,
0951     [PWRAP_INT1_CLR] =          0xCC,
0952     [PWRAP_SIG_ADR] =           0xD0,
0953     [PWRAP_CRC_EN] =            0xE0,
0954     [PWRAP_TIMER_EN] =          0xE4,
0955     [PWRAP_WDT_UNIT] =          0xEC,
0956     [PWRAP_WDT_SRC_EN] =            0xF0,
0957     [PWRAP_WDT_SRC_EN_1] =          0xF4,
0958     [PWRAP_INT_GPS_AUXADC_CMD_ADDR] =   0x1DC,
0959     [PWRAP_INT_GPS_AUXADC_CMD] =        0x1E0,
0960     [PWRAP_INT_GPS_AUXADC_RDATA_ADDR] = 0x1E4,
0961     [PWRAP_EXT_GPS_AUXADC_RDATA_ADDR] = 0x1E8,
0962     [PWRAP_GPSINF_0_STA] =          0x1EC,
0963     [PWRAP_GPSINF_1_STA] =          0x1F0,
0964     [PWRAP_WACS2_CMD] =         0xC20,
0965     [PWRAP_WACS2_RDATA] =           0xC24,
0966     [PWRAP_WACS2_VLDCLR] =          0xC28,
0967 };
0968 
0969 static int mt8195_regs[] = {
0970     [PWRAP_INIT_DONE2] =        0x0,
0971     [PWRAP_STAUPD_CTRL] =       0x4C,
0972     [PWRAP_TIMER_EN] =      0x3E4,
0973     [PWRAP_INT_EN] =        0x420,
0974     [PWRAP_INT_FLG] =       0x428,
0975     [PWRAP_INT_CLR] =       0x42C,
0976     [PWRAP_INT1_EN] =       0x450,
0977     [PWRAP_INT1_FLG] =      0x458,
0978     [PWRAP_INT1_CLR] =      0x45C,
0979     [PWRAP_WACS2_CMD] =     0x880,
0980     [PWRAP_SWINF_2_WDATA_31_0] =    0x884,
0981     [PWRAP_SWINF_2_RDATA_31_0] =    0x894,
0982     [PWRAP_WACS2_VLDCLR] =      0x8A4,
0983     [PWRAP_WACS2_RDATA] =       0x8A8,
0984 };
0985 
0986 static int mt8516_regs[] = {
0987     [PWRAP_MUX_SEL] =       0x0,
0988     [PWRAP_WRAP_EN] =       0x4,
0989     [PWRAP_DIO_EN] =        0x8,
0990     [PWRAP_SIDLY] =         0xc,
0991     [PWRAP_RDDMY] =         0x10,
0992     [PWRAP_SI_CK_CON] =     0x14,
0993     [PWRAP_CSHEXT_WRITE] =      0x18,
0994     [PWRAP_CSHEXT_READ] =       0x1c,
0995     [PWRAP_CSLEXT_START] =      0x20,
0996     [PWRAP_CSLEXT_END] =        0x24,
0997     [PWRAP_STAUPD_PRD] =        0x28,
0998     [PWRAP_STAUPD_GRPEN] =      0x2c,
0999     [PWRAP_STAUPD_MAN_TRIG] =   0x40,
1000     [PWRAP_STAUPD_STA] =        0x44,
1001     [PWRAP_WRAP_STA] =      0x48,
1002     [PWRAP_HARB_INIT] =     0x4c,
1003     [PWRAP_HARB_HPRIO] =        0x50,
1004     [PWRAP_HIPRIO_ARB_EN] =     0x54,
1005     [PWRAP_HARB_STA0] =     0x58,
1006     [PWRAP_HARB_STA1] =     0x5c,
1007     [PWRAP_MAN_EN] =        0x60,
1008     [PWRAP_MAN_CMD] =       0x64,
1009     [PWRAP_MAN_RDATA] =     0x68,
1010     [PWRAP_MAN_VLDCLR] =        0x6c,
1011     [PWRAP_WACS0_EN] =      0x70,
1012     [PWRAP_INIT_DONE0] =        0x74,
1013     [PWRAP_WACS0_CMD] =     0x78,
1014     [PWRAP_WACS0_RDATA] =       0x7c,
1015     [PWRAP_WACS0_VLDCLR] =      0x80,
1016     [PWRAP_WACS1_EN] =      0x84,
1017     [PWRAP_INIT_DONE1] =        0x88,
1018     [PWRAP_WACS1_CMD] =     0x8c,
1019     [PWRAP_WACS1_RDATA] =       0x90,
1020     [PWRAP_WACS1_VLDCLR] =      0x94,
1021     [PWRAP_WACS2_EN] =      0x98,
1022     [PWRAP_INIT_DONE2] =        0x9c,
1023     [PWRAP_WACS2_CMD] =     0xa0,
1024     [PWRAP_WACS2_RDATA] =       0xa4,
1025     [PWRAP_WACS2_VLDCLR] =      0xa8,
1026     [PWRAP_INT_EN] =        0xac,
1027     [PWRAP_INT_FLG_RAW] =       0xb0,
1028     [PWRAP_INT_FLG] =       0xb4,
1029     [PWRAP_INT_CLR] =       0xb8,
1030     [PWRAP_SIG_ADR] =       0xbc,
1031     [PWRAP_SIG_MODE] =      0xc0,
1032     [PWRAP_SIG_VALUE] =     0xc4,
1033     [PWRAP_SIG_ERRVAL] =        0xc8,
1034     [PWRAP_CRC_EN] =        0xcc,
1035     [PWRAP_TIMER_EN] =      0xd0,
1036     [PWRAP_TIMER_STA] =     0xd4,
1037     [PWRAP_WDT_UNIT] =      0xd8,
1038     [PWRAP_WDT_SRC_EN] =        0xdc,
1039     [PWRAP_WDT_FLG] =       0xe0,
1040     [PWRAP_DEBUG_INT_SEL] =     0xe4,
1041     [PWRAP_DVFS_ADR0] =     0xe8,
1042     [PWRAP_DVFS_WDATA0] =       0xec,
1043     [PWRAP_DVFS_ADR1] =     0xf0,
1044     [PWRAP_DVFS_WDATA1] =       0xf4,
1045     [PWRAP_DVFS_ADR2] =     0xf8,
1046     [PWRAP_DVFS_WDATA2] =       0xfc,
1047     [PWRAP_DVFS_ADR3] =     0x100,
1048     [PWRAP_DVFS_WDATA3] =       0x104,
1049     [PWRAP_DVFS_ADR4] =     0x108,
1050     [PWRAP_DVFS_WDATA4] =       0x10c,
1051     [PWRAP_DVFS_ADR5] =     0x110,
1052     [PWRAP_DVFS_WDATA5] =       0x114,
1053     [PWRAP_DVFS_ADR6] =     0x118,
1054     [PWRAP_DVFS_WDATA6] =       0x11c,
1055     [PWRAP_DVFS_ADR7] =     0x120,
1056     [PWRAP_DVFS_WDATA7] =       0x124,
1057     [PWRAP_SPMINF_STA] =        0x128,
1058     [PWRAP_CIPHER_KEY_SEL] =    0x12c,
1059     [PWRAP_CIPHER_IV_SEL] =     0x130,
1060     [PWRAP_CIPHER_EN] =     0x134,
1061     [PWRAP_CIPHER_RDY] =        0x138,
1062     [PWRAP_CIPHER_MODE] =       0x13c,
1063     [PWRAP_CIPHER_SWRST] =      0x140,
1064     [PWRAP_DCM_EN] =        0x144,
1065     [PWRAP_DCM_DBC_PRD] =       0x148,
1066     [PWRAP_SW_RST] =        0x168,
1067     [PWRAP_OP_TYPE] =       0x16c,
1068     [PWRAP_MSB_FIRST] =     0x170,
1069 };
1070 
1071 static int mt8186_regs[] = {
1072     [PWRAP_MUX_SEL] =       0x0,
1073     [PWRAP_WRAP_EN] =       0x4,
1074     [PWRAP_DIO_EN] =        0x8,
1075     [PWRAP_RDDMY] =         0x20,
1076     [PWRAP_CSHEXT_WRITE] =      0x24,
1077     [PWRAP_CSHEXT_READ] =       0x28,
1078     [PWRAP_CSLEXT_WRITE] =      0x2C,
1079     [PWRAP_CSLEXT_READ] =       0x30,
1080     [PWRAP_EXT_CK_WRITE] =      0x34,
1081     [PWRAP_STAUPD_CTRL] =       0x3C,
1082     [PWRAP_STAUPD_GRPEN] =      0x40,
1083     [PWRAP_EINT_STA0_ADR] =     0x44,
1084     [PWRAP_EINT_STA1_ADR] =     0x48,
1085     [PWRAP_INT_CLR] =       0xC8,
1086     [PWRAP_INT_FLG] =       0xC4,
1087     [PWRAP_MAN_EN] =        0x7C,
1088     [PWRAP_MAN_CMD] =       0x80,
1089     [PWRAP_WACS0_EN] =      0x8C,
1090     [PWRAP_WACS1_EN] =      0x94,
1091     [PWRAP_WACS2_EN] =      0x9C,
1092     [PWRAP_INIT_DONE0] =        0x90,
1093     [PWRAP_INIT_DONE1] =        0x98,
1094     [PWRAP_INIT_DONE2] =        0xA0,
1095     [PWRAP_INT_EN] =        0xBC,
1096     [PWRAP_INT1_EN] =       0xCC,
1097     [PWRAP_INT1_FLG] =      0xD4,
1098     [PWRAP_INT1_CLR] =      0xD8,
1099     [PWRAP_TIMER_EN] =      0xF0,
1100     [PWRAP_WDT_UNIT] =      0xF8,
1101     [PWRAP_WDT_SRC_EN] =        0xFC,
1102     [PWRAP_WDT_SRC_EN_1] =      0x100,
1103     [PWRAP_WDT_FLG] =       0x104,
1104     [PWRAP_SPMINF_STA] =        0x1B4,
1105     [PWRAP_DCM_EN] =        0x1EC,
1106     [PWRAP_DCM_DBC_PRD] =       0x1F0,
1107     [PWRAP_GPSINF_0_STA] =      0x204,
1108     [PWRAP_GPSINF_1_STA] =      0x208,
1109     [PWRAP_WACS0_CMD] =     0xC00,
1110     [PWRAP_WACS0_RDATA] =       0xC04,
1111     [PWRAP_WACS0_VLDCLR] =      0xC08,
1112     [PWRAP_WACS1_CMD] =     0xC10,
1113     [PWRAP_WACS1_RDATA] =       0xC14,
1114     [PWRAP_WACS1_VLDCLR] =      0xC18,
1115     [PWRAP_WACS2_CMD] =     0xC20,
1116     [PWRAP_WACS2_RDATA] =       0xC24,
1117     [PWRAP_WACS2_VLDCLR] =      0xC28,
1118 };
1119 
1120 enum pmic_type {
1121     PMIC_MT6323,
1122     PMIC_MT6351,
1123     PMIC_MT6357,
1124     PMIC_MT6358,
1125     PMIC_MT6359,
1126     PMIC_MT6380,
1127     PMIC_MT6397,
1128 };
1129 
1130 enum pwrap_type {
1131     PWRAP_MT2701,
1132     PWRAP_MT6765,
1133     PWRAP_MT6779,
1134     PWRAP_MT6797,
1135     PWRAP_MT6873,
1136     PWRAP_MT7622,
1137     PWRAP_MT8135,
1138     PWRAP_MT8173,
1139     PWRAP_MT8183,
1140     PWRAP_MT8186,
1141     PWRAP_MT8195,
1142     PWRAP_MT8516,
1143 };
1144 
1145 struct pmic_wrapper;
1146 
1147 struct pwrap_slv_regops {
1148     const struct regmap_config *regmap;
1149     /*
1150      * pwrap operations are highly associated with the PMIC types,
1151      * so the pointers added increases flexibility allowing determination
1152      * which type is used by the detection through device tree.
1153      */
1154     int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1155     int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1156 };
1157 
1158 struct pwrap_slv_type {
1159     const u32 *dew_regs;
1160     enum pmic_type type;
1161     const struct pwrap_slv_regops *regops;
1162     /* Flags indicating the capability for the target slave */
1163     u32 caps;
1164 };
1165 
1166 struct pmic_wrapper {
1167     struct device *dev;
1168     void __iomem *base;
1169     struct regmap *regmap;
1170     const struct pmic_wrapper_type *master;
1171     const struct pwrap_slv_type *slave;
1172     struct clk *clk_spi;
1173     struct clk *clk_wrap;
1174     struct reset_control *rstc;
1175 
1176     struct reset_control *rstc_bridge;
1177     void __iomem *bridge_base;
1178 };
1179 
1180 struct pmic_wrapper_type {
1181     int *regs;
1182     enum pwrap_type type;
1183     u32 arb_en_all;
1184     u32 int_en_all;
1185     u32 int1_en_all;
1186     u32 spi_w;
1187     u32 wdt_src;
1188     /* Flags indicating the capability for the target pwrap */
1189     u32 caps;
1190     int (*init_reg_clock)(struct pmic_wrapper *wrp);
1191     int (*init_soc_specific)(struct pmic_wrapper *wrp);
1192 };
1193 
1194 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1195 {
1196     return readl(wrp->base + wrp->master->regs[reg]);
1197 }
1198 
1199 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1200 {
1201     writel(val, wrp->base + wrp->master->regs[reg]);
1202 }
1203 
1204 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)
1205 {
1206     u32 val;
1207 
1208     val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1209     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1210         return PWRAP_GET_WACS_ARB_FSM(val);
1211     else
1212         return PWRAP_GET_WACS_FSM(val);
1213 }
1214 
1215 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1216 {
1217     return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;
1218 }
1219 
1220 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1221 {
1222     return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;
1223 }
1224 
1225 /*
1226  * Timeout issue sometimes caused by the last read command
1227  * failed because pmic wrap could not got the FSM_VLDCLR
1228  * in time after finishing WACS2_CMD. It made state machine
1229  * still on FSM_VLDCLR and timeout next time.
1230  * Check the status of FSM and clear the vldclr to recovery the
1231  * error.
1232  */
1233 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1234 {
1235     if (pwrap_is_fsm_vldclr(wrp))
1236         pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1237 }
1238 
1239 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1240 {
1241     return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1242 }
1243 
1244 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1245 {
1246     u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1247 
1248     return (PWRAP_GET_WACS_FSM(val) == PWRAP_WACS_FSM_IDLE) &&
1249         (val & PWRAP_STATE_SYNC_IDLE0);
1250 }
1251 
1252 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1253 {
1254     bool tmp;
1255     int ret;
1256     u32 val;
1257 
1258     ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1259                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1260     if (ret) {
1261         pwrap_leave_fsm_vldclr(wrp);
1262         return ret;
1263     }
1264 
1265     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1266         val = adr;
1267     else
1268         val = (adr >> 1) << 16;
1269     pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
1270 
1271     ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp,
1272                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1273     if (ret)
1274         return ret;
1275 
1276     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1277         val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
1278     else
1279         val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1280     *rdata = PWRAP_GET_WACS_RDATA(val);
1281 
1282     pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1283 
1284     return 0;
1285 }
1286 
1287 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1288 {
1289     bool tmp;
1290     int ret, msb;
1291 
1292     *rdata = 0;
1293     for (msb = 0; msb < 2; msb++) {
1294         ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1295                      PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1296 
1297         if (ret) {
1298             pwrap_leave_fsm_vldclr(wrp);
1299             return ret;
1300         }
1301 
1302         pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1303                  PWRAP_WACS2_CMD);
1304 
1305         ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp,
1306                      PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1307         if (ret)
1308             return ret;
1309 
1310         *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1311                PWRAP_WACS2_RDATA)) << (16 * msb));
1312 
1313         pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1314     }
1315 
1316     return 0;
1317 }
1318 
1319 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1320 {
1321     return wrp->slave->regops->pwrap_read(wrp, adr, rdata);
1322 }
1323 
1324 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1325 {
1326     bool tmp;
1327     int ret;
1328 
1329     ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1330                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1331     if (ret) {
1332         pwrap_leave_fsm_vldclr(wrp);
1333         return ret;
1334     }
1335 
1336     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
1337         pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
1338         pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
1339     } else {
1340         pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
1341                  PWRAP_WACS2_CMD);
1342     }
1343 
1344     return 0;
1345 }
1346 
1347 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1348 {
1349     bool tmp;
1350     int ret, msb, rdata;
1351 
1352     for (msb = 0; msb < 2; msb++) {
1353         ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1354                      PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1355         if (ret) {
1356             pwrap_leave_fsm_vldclr(wrp);
1357             return ret;
1358         }
1359 
1360         pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1361                  ((wdata >> (msb * 16)) & 0xffff),
1362                  PWRAP_WACS2_CMD);
1363 
1364         /*
1365          * The pwrap_read operation is the requirement of hardware used
1366          * for the synchronization between two successive 16-bit
1367          * pwrap_writel operations composing one 32-bit bus writing.
1368          * Otherwise, we'll find the result fails on the lower 16-bit
1369          * pwrap writing.
1370          */
1371         if (!msb)
1372             pwrap_read(wrp, adr, &rdata);
1373     }
1374 
1375     return 0;
1376 }
1377 
1378 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1379 {
1380     return wrp->slave->regops->pwrap_write(wrp, adr, wdata);
1381 }
1382 
1383 static int pwrap_regmap_read(void *context, u32 adr, u32 *rdata)
1384 {
1385     return pwrap_read(context, adr, rdata);
1386 }
1387 
1388 static int pwrap_regmap_write(void *context, u32 adr, u32 wdata)
1389 {
1390     return pwrap_write(context, adr, wdata);
1391 }
1392 
1393 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1394 {
1395     bool tmp;
1396     int ret, i;
1397 
1398     pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1399     pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1400     pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1401     pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1402     pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1403 
1404     pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1405             PWRAP_MAN_CMD);
1406     pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1407             PWRAP_MAN_CMD);
1408     pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1409             PWRAP_MAN_CMD);
1410 
1411     for (i = 0; i < 4; i++)
1412         pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1413                 PWRAP_MAN_CMD);
1414 
1415     ret = readx_poll_timeout(pwrap_is_sync_idle, wrp, tmp, tmp,
1416                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1417     if (ret) {
1418         dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1419         return ret;
1420     }
1421 
1422     pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1423     pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1424 
1425     return 0;
1426 }
1427 
1428 /*
1429  * pwrap_init_sidly - configure serial input delay
1430  *
1431  * This configures the serial input delay. We can configure 0, 2, 4 or 6ns
1432  * delay. Do a read test with all possible values and chose the best delay.
1433  */
1434 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1435 {
1436     u32 rdata;
1437     u32 i;
1438     u32 pass = 0;
1439     signed char dly[16] = {
1440         -1, 0, 1, 0, 2, -1, 1, 1, 3, -1, -1, -1, 3, -1, 2, 1
1441     };
1442 
1443     for (i = 0; i < 4; i++) {
1444         pwrap_writel(wrp, i, PWRAP_SIDLY);
1445         pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_READ_TEST],
1446                &rdata);
1447         if (rdata == PWRAP_DEW_READ_TEST_VAL) {
1448             dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1449             pass |= 1 << i;
1450         }
1451     }
1452 
1453     if (dly[pass] < 0) {
1454         dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1455                 pass);
1456         return -EIO;
1457     }
1458 
1459     pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1460 
1461     return 0;
1462 }
1463 
1464 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1465 {
1466     int ret;
1467     bool tmp;
1468     u32 rdata;
1469 
1470     /* Enable dual IO mode */
1471     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1472 
1473     /* Check IDLE & INIT_DONE in advance */
1474     ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,
1475                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1476     if (ret) {
1477         dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1478         return ret;
1479     }
1480 
1481     pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1482 
1483     /* Read Test */
1484     pwrap_read(wrp,
1485            wrp->slave->dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1486     if (rdata != PWRAP_DEW_READ_TEST_VAL) {
1487         dev_err(wrp->dev,
1488             "Read failed on DIO mode: 0x%04x!=0x%04x\n",
1489             PWRAP_DEW_READ_TEST_VAL, rdata);
1490         return -EFAULT;
1491     }
1492 
1493     return 0;
1494 }
1495 
1496 /*
1497  * pwrap_init_chip_select_ext is used to configure CS extension time for each
1498  * phase during data transactions on the pwrap bus.
1499  */
1500 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1501                        u8 hext_read, u8 lext_start,
1502                        u8 lext_end)
1503 {
1504     /*
1505      * After finishing a write and read transaction, extends CS high time
1506      * to be at least xT of BUS CLK as hext_write and hext_read specifies
1507      * respectively.
1508      */
1509     pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1510     pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1511 
1512     /*
1513      * Extends CS low time after CSL and before CSH command to be at
1514      * least xT of BUS CLK as lext_start and lext_end specifies
1515      * respectively.
1516      */
1517     pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1518     pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1519 }
1520 
1521 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1522 {
1523     switch (wrp->master->type) {
1524     case PWRAP_MT8173:
1525         pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1526         break;
1527     case PWRAP_MT8135:
1528         pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1529         pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1530         break;
1531     default:
1532         break;
1533     }
1534 
1535     return 0;
1536 }
1537 
1538 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1539 {
1540     switch (wrp->slave->type) {
1541     case PMIC_MT6397:
1542         pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1543         pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1544         break;
1545 
1546     case PMIC_MT6323:
1547         pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1548         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1549                 0x8);
1550         pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1551         break;
1552     default:
1553         break;
1554     }
1555 
1556     return 0;
1557 }
1558 
1559 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1560 {
1561     return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1562 }
1563 
1564 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1565 {
1566     u32 rdata;
1567     int ret;
1568 
1569     ret = pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_RDY],
1570              &rdata);
1571     if (ret)
1572         return false;
1573 
1574     return rdata == 1;
1575 }
1576 
1577 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1578 {
1579     int ret;
1580     bool tmp;
1581     u32 rdata = 0;
1582 
1583     pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1584     pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1585     pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1586     pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1587 
1588     switch (wrp->master->type) {
1589     case PWRAP_MT8135:
1590         pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1591         pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1592         break;
1593     case PWRAP_MT2701:
1594     case PWRAP_MT6765:
1595     case PWRAP_MT6779:
1596     case PWRAP_MT6797:
1597     case PWRAP_MT8173:
1598     case PWRAP_MT8186:
1599     case PWRAP_MT8516:
1600         pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1601         break;
1602     case PWRAP_MT7622:
1603         pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1604         break;
1605     case PWRAP_MT6873:
1606     case PWRAP_MT8183:
1607     case PWRAP_MT8195:
1608         break;
1609     }
1610 
1611     /* Config cipher mode @PMIC */
1612     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1613     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1614     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1615     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1616 
1617     switch (wrp->slave->type) {
1618     case PMIC_MT6397:
1619         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1620                 0x1);
1621         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1622                 0x1);
1623         break;
1624     case PMIC_MT6323:
1625     case PMIC_MT6351:
1626     case PMIC_MT6357:
1627         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1628                 0x1);
1629         break;
1630     default:
1631         break;
1632     }
1633 
1634     /* wait for cipher data ready@AP */
1635     ret = readx_poll_timeout(pwrap_is_cipher_ready, wrp, tmp, tmp,
1636                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1637     if (ret) {
1638         dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1639         return ret;
1640     }
1641 
1642     /* wait for cipher data ready@PMIC */
1643     ret = readx_poll_timeout(pwrap_is_pmic_cipher_ready, wrp, tmp, tmp,
1644                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1645     if (ret) {
1646         dev_err(wrp->dev,
1647             "timeout waiting for cipher data ready@PMIC\n");
1648         return ret;
1649     }
1650 
1651     /* wait for cipher mode idle */
1652     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1653     ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,
1654                  PWRAP_POLL_DELAY_US, PWRAP_POLL_TIMEOUT_US);
1655     if (ret) {
1656         dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1657         return ret;
1658     }
1659 
1660     pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1661 
1662     /* Write Test */
1663     if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1664             PWRAP_DEW_WRITE_TEST_VAL) ||
1665         pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1666                &rdata) ||
1667         (rdata != PWRAP_DEW_WRITE_TEST_VAL)) {
1668         dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1669         return -EFAULT;
1670     }
1671 
1672     return 0;
1673 }
1674 
1675 static int pwrap_init_security(struct pmic_wrapper *wrp)
1676 {
1677     int ret;
1678 
1679     /* Enable encryption */
1680     ret = pwrap_init_cipher(wrp);
1681     if (ret)
1682         return ret;
1683 
1684     /* Signature checking - using CRC */
1685     if (pwrap_write(wrp,
1686             wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1))
1687         return -EFAULT;
1688 
1689     pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1690     pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1691     pwrap_writel(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL],
1692              PWRAP_SIG_ADR);
1693     pwrap_writel(wrp,
1694              wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1695 
1696     return 0;
1697 }
1698 
1699 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1700 {
1701     /* enable pwrap events and pwrap bridge in AP side */
1702     pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1703     pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1704     writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1705     writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1706     writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1707     writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1708     writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1709     writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1710     writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1711 
1712     /* enable PMIC event out and sources */
1713     if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1714             0x1) ||
1715         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1716             0xffff)) {
1717         dev_err(wrp->dev, "enable dewrap fail\n");
1718         return -EFAULT;
1719     }
1720 
1721     return 0;
1722 }
1723 
1724 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1725 {
1726     /* PMIC_DEWRAP enables */
1727     if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1728             0x1) ||
1729         pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1730             0xffff)) {
1731         dev_err(wrp->dev, "enable dewrap fail\n");
1732         return -EFAULT;
1733     }
1734 
1735     return 0;
1736 }
1737 
1738 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
1739 {
1740     /* GPS_INTF initialization */
1741     switch (wrp->slave->type) {
1742     case PMIC_MT6323:
1743         pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
1744         pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
1745         pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
1746         pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
1747         pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
1748         break;
1749     default:
1750         break;
1751     }
1752 
1753     return 0;
1754 }
1755 
1756 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
1757 {
1758     pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
1759     /* enable 2wire SPI master */
1760     pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
1761 
1762     return 0;
1763 }
1764 
1765 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
1766 {
1767     pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
1768 
1769     pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1770     pwrap_writel(wrp, 1, PWRAP_CRC_EN);
1771     pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
1772     pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
1773 
1774     pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
1775     pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
1776     pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
1777     pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
1778 
1779     return 0;
1780 }
1781 
1782 static int pwrap_init(struct pmic_wrapper *wrp)
1783 {
1784     int ret;
1785 
1786     if (wrp->rstc)
1787         reset_control_reset(wrp->rstc);
1788     if (wrp->rstc_bridge)
1789         reset_control_reset(wrp->rstc_bridge);
1790 
1791     if (wrp->master->type == PWRAP_MT8173) {
1792         /* Enable DCM */
1793         pwrap_writel(wrp, 3, PWRAP_DCM_EN);
1794         pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
1795     }
1796 
1797     if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1798         /* Reset SPI slave */
1799         ret = pwrap_reset_spislave(wrp);
1800         if (ret)
1801             return ret;
1802     }
1803 
1804     pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
1805 
1806     pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1807 
1808     pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
1809 
1810     ret = wrp->master->init_reg_clock(wrp);
1811     if (ret)
1812         return ret;
1813 
1814     if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
1815         /* Setup serial input delay */
1816         ret = pwrap_init_sidly(wrp);
1817         if (ret)
1818             return ret;
1819     }
1820 
1821     if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
1822         /* Enable dual I/O mode */
1823         ret = pwrap_init_dual_io(wrp);
1824         if (ret)
1825             return ret;
1826     }
1827 
1828     if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
1829         /* Enable security on bus */
1830         ret = pwrap_init_security(wrp);
1831         if (ret)
1832             return ret;
1833     }
1834 
1835     if (wrp->master->type == PWRAP_MT8135)
1836         pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
1837 
1838     pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
1839     pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
1840     pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
1841     pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
1842     pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
1843 
1844     if (wrp->master->init_soc_specific) {
1845         ret = wrp->master->init_soc_specific(wrp);
1846         if (ret)
1847             return ret;
1848     }
1849 
1850     /* Setup the init done registers */
1851     pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
1852     pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
1853     pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
1854 
1855     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
1856         writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
1857         writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
1858     }
1859 
1860     return 0;
1861 }
1862 
1863 static irqreturn_t pwrap_interrupt(int irqno, void *dev_id)
1864 {
1865     u32 rdata;
1866     struct pmic_wrapper *wrp = dev_id;
1867 
1868     rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
1869     dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
1870     pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
1871 
1872     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
1873         rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
1874         dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
1875         pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
1876     }
1877 
1878     return IRQ_HANDLED;
1879 }
1880 
1881 static const struct regmap_config pwrap_regmap_config16 = {
1882     .reg_bits = 16,
1883     .val_bits = 16,
1884     .reg_stride = 2,
1885     .reg_read = pwrap_regmap_read,
1886     .reg_write = pwrap_regmap_write,
1887     .max_register = 0xffff,
1888 };
1889 
1890 static const struct regmap_config pwrap_regmap_config32 = {
1891     .reg_bits = 32,
1892     .val_bits = 32,
1893     .reg_stride = 4,
1894     .reg_read = pwrap_regmap_read,
1895     .reg_write = pwrap_regmap_write,
1896     .max_register = 0xffff,
1897 };
1898 
1899 static const struct pwrap_slv_regops pwrap_regops16 = {
1900     .pwrap_read = pwrap_read16,
1901     .pwrap_write = pwrap_write16,
1902     .regmap = &pwrap_regmap_config16,
1903 };
1904 
1905 static const struct pwrap_slv_regops pwrap_regops32 = {
1906     .pwrap_read = pwrap_read32,
1907     .pwrap_write = pwrap_write32,
1908     .regmap = &pwrap_regmap_config32,
1909 };
1910 
1911 static const struct pwrap_slv_type pmic_mt6323 = {
1912     .dew_regs = mt6323_regs,
1913     .type = PMIC_MT6323,
1914     .regops = &pwrap_regops16,
1915     .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1916         PWRAP_SLV_CAP_SECURITY,
1917 };
1918 
1919 static const struct pwrap_slv_type pmic_mt6351 = {
1920     .dew_regs = mt6351_regs,
1921     .type = PMIC_MT6351,
1922     .regops = &pwrap_regops16,
1923     .caps = 0,
1924 };
1925 
1926 static const struct pwrap_slv_type pmic_mt6357 = {
1927     .dew_regs = mt6357_regs,
1928     .type = PMIC_MT6357,
1929     .regops = &pwrap_regops16,
1930     .caps = 0,
1931 };
1932 
1933 static const struct pwrap_slv_type pmic_mt6358 = {
1934     .dew_regs = mt6358_regs,
1935     .type = PMIC_MT6358,
1936     .regops = &pwrap_regops16,
1937     .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO,
1938 };
1939 
1940 static const struct pwrap_slv_type pmic_mt6359 = {
1941     .dew_regs = mt6359_regs,
1942     .type = PMIC_MT6359,
1943     .regops = &pwrap_regops16,
1944     .caps = PWRAP_SLV_CAP_DUALIO,
1945 };
1946 
1947 static const struct pwrap_slv_type pmic_mt6380 = {
1948     .dew_regs = NULL,
1949     .type = PMIC_MT6380,
1950     .regops = &pwrap_regops32,
1951     .caps = 0,
1952 };
1953 
1954 static const struct pwrap_slv_type pmic_mt6397 = {
1955     .dew_regs = mt6397_regs,
1956     .type = PMIC_MT6397,
1957     .regops = &pwrap_regops16,
1958     .caps = PWRAP_SLV_CAP_SPI | PWRAP_SLV_CAP_DUALIO |
1959         PWRAP_SLV_CAP_SECURITY,
1960 };
1961 
1962 static const struct of_device_id of_slave_match_tbl[] = {
1963     { .compatible = "mediatek,mt6323", .data = &pmic_mt6323 },
1964     { .compatible = "mediatek,mt6351", .data = &pmic_mt6351 },
1965     { .compatible = "mediatek,mt6357", .data = &pmic_mt6357 },
1966     { .compatible = "mediatek,mt6358", .data = &pmic_mt6358 },
1967     { .compatible = "mediatek,mt6359", .data = &pmic_mt6359 },
1968 
1969     /* The MT6380 PMIC only implements a regulator, so we bind it
1970      * directly instead of using a MFD.
1971      */
1972     { .compatible = "mediatek,mt6380-regulator", .data = &pmic_mt6380 },
1973     { .compatible = "mediatek,mt6397", .data = &pmic_mt6397 },
1974     { /* sentinel */ }
1975 };
1976 MODULE_DEVICE_TABLE(of, of_slave_match_tbl);
1977 
1978 static const struct pmic_wrapper_type pwrap_mt2701 = {
1979     .regs = mt2701_regs,
1980     .type = PWRAP_MT2701,
1981     .arb_en_all = 0x3f,
1982     .int_en_all = ~(u32)(BIT(31) | BIT(2)),
1983     .int1_en_all = 0,
1984     .spi_w = PWRAP_MAN_CMD_SPI_WRITE_NEW,
1985     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1986     .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1987     .init_reg_clock = pwrap_mt2701_init_reg_clock,
1988     .init_soc_specific = pwrap_mt2701_init_soc_specific,
1989 };
1990 
1991 static const struct pmic_wrapper_type pwrap_mt6765 = {
1992     .regs = mt6765_regs,
1993     .type = PWRAP_MT6765,
1994     .arb_en_all = 0x3fd35,
1995     .int_en_all = 0xffffffff,
1996     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
1997     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
1998     .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
1999     .init_reg_clock = pwrap_common_init_reg_clock,
2000     .init_soc_specific = NULL,
2001 };
2002 
2003 static const struct pmic_wrapper_type pwrap_mt6779 = {
2004     .regs = mt6779_regs,
2005     .type = PWRAP_MT6779,
2006     .arb_en_all = 0xfbb7f,
2007     .int_en_all = 0xfffffffe,
2008     .int1_en_all = 0,
2009     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2010     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2011     .caps = 0,
2012     .init_reg_clock = pwrap_common_init_reg_clock,
2013     .init_soc_specific = NULL,
2014 };
2015 
2016 static const struct pmic_wrapper_type pwrap_mt6797 = {
2017     .regs = mt6797_regs,
2018     .type = PWRAP_MT6797,
2019     .arb_en_all = 0x01fff,
2020     .int_en_all = 0xffffffc6,
2021     .int1_en_all = 0,
2022     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2023     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2024     .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2025     .init_reg_clock = pwrap_common_init_reg_clock,
2026     .init_soc_specific = NULL,
2027 };
2028 
2029 static const struct pmic_wrapper_type pwrap_mt6873 = {
2030     .regs = mt6873_regs,
2031     .type = PWRAP_MT6873,
2032     .arb_en_all = 0x777f,
2033     .int_en_all = BIT(4) | BIT(5),
2034     .int1_en_all = 0,
2035     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2036     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2037     .caps = PWRAP_CAP_ARB,
2038     .init_reg_clock = pwrap_common_init_reg_clock,
2039     .init_soc_specific = NULL,
2040 };
2041 
2042 static const struct pmic_wrapper_type pwrap_mt7622 = {
2043     .regs = mt7622_regs,
2044     .type = PWRAP_MT7622,
2045     .arb_en_all = 0xff,
2046     .int_en_all = ~(u32)BIT(31),
2047     .int1_en_all = 0,
2048     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2049     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2050     .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2051     .init_reg_clock = pwrap_common_init_reg_clock,
2052     .init_soc_specific = pwrap_mt7622_init_soc_specific,
2053 };
2054 
2055 static const struct pmic_wrapper_type pwrap_mt8135 = {
2056     .regs = mt8135_regs,
2057     .type = PWRAP_MT8135,
2058     .arb_en_all = 0x1ff,
2059     .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2060     .int1_en_all = 0,
2061     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2062     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2063     .caps = PWRAP_CAP_BRIDGE | PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2064     .init_reg_clock = pwrap_common_init_reg_clock,
2065     .init_soc_specific = pwrap_mt8135_init_soc_specific,
2066 };
2067 
2068 static const struct pmic_wrapper_type pwrap_mt8173 = {
2069     .regs = mt8173_regs,
2070     .type = PWRAP_MT8173,
2071     .arb_en_all = 0x3f,
2072     .int_en_all = ~(u32)(BIT(31) | BIT(1)),
2073     .int1_en_all = 0,
2074     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2075     .wdt_src = PWRAP_WDT_SRC_MASK_NO_STAUPD,
2076     .caps = PWRAP_CAP_RESET | PWRAP_CAP_DCM,
2077     .init_reg_clock = pwrap_common_init_reg_clock,
2078     .init_soc_specific = pwrap_mt8173_init_soc_specific,
2079 };
2080 
2081 static const struct pmic_wrapper_type pwrap_mt8183 = {
2082     .regs = mt8183_regs,
2083     .type = PWRAP_MT8183,
2084     .arb_en_all = 0x3fa75,
2085     .int_en_all = 0xffffffff,
2086     .int1_en_all = 0xeef7ffff,
2087     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2088     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2089     .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_WDT_SRC1,
2090     .init_reg_clock = pwrap_common_init_reg_clock,
2091     .init_soc_specific = pwrap_mt8183_init_soc_specific,
2092 };
2093 
2094 static struct pmic_wrapper_type pwrap_mt8195 = {
2095     .regs = mt8195_regs,
2096     .type = PWRAP_MT8195,
2097     .arb_en_all = 0x777f, /* NEED CONFIRM */
2098     .int_en_all = 0x180000, /* NEED CONFIRM */
2099     .int1_en_all = 0,
2100     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2101     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2102     .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB,
2103     .init_reg_clock = pwrap_common_init_reg_clock,
2104     .init_soc_specific = NULL,
2105 };
2106 
2107 static struct pmic_wrapper_type pwrap_mt8516 = {
2108     .regs = mt8516_regs,
2109     .type = PWRAP_MT8516,
2110     .arb_en_all = 0xff,
2111     .int_en_all = ~(u32)(BIT(31) | BIT(2)),
2112     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2113     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2114     .caps = PWRAP_CAP_DCM,
2115     .init_reg_clock = pwrap_mt2701_init_reg_clock,
2116     .init_soc_specific = NULL,
2117 };
2118 
2119 static struct pmic_wrapper_type pwrap_mt8186 = {
2120     .regs = mt8186_regs,
2121     .type = PWRAP_MT8186,
2122     .arb_en_all = 0xfb27f,
2123     .int_en_all = 0xfffffffe, /* disable WatchDog Timeout for bit 1 */
2124     .int1_en_all =  0x000017ff, /* disable Matching interrupt for bit 13 */
2125     .spi_w = PWRAP_MAN_CMD_SPI_WRITE,
2126     .wdt_src = PWRAP_WDT_SRC_MASK_ALL,
2127     .caps = PWRAP_CAP_INT1_EN | PWRAP_CAP_ARB_MT8186,
2128     .init_reg_clock = pwrap_common_init_reg_clock,
2129     .init_soc_specific = NULL,
2130 };
2131 
2132 static const struct of_device_id of_pwrap_match_tbl[] = {
2133     { .compatible = "mediatek,mt2701-pwrap", .data = &pwrap_mt2701 },
2134     { .compatible = "mediatek,mt6765-pwrap", .data = &pwrap_mt6765 },
2135     { .compatible = "mediatek,mt6779-pwrap", .data = &pwrap_mt6779 },
2136     { .compatible = "mediatek,mt6797-pwrap", .data = &pwrap_mt6797 },
2137     { .compatible = "mediatek,mt6873-pwrap", .data = &pwrap_mt6873 },
2138     { .compatible = "mediatek,mt7622-pwrap", .data = &pwrap_mt7622 },
2139     { .compatible = "mediatek,mt8135-pwrap", .data = &pwrap_mt8135 },
2140     { .compatible = "mediatek,mt8173-pwrap", .data = &pwrap_mt8173 },
2141     { .compatible = "mediatek,mt8183-pwrap", .data = &pwrap_mt8183 },
2142     { .compatible = "mediatek,mt8186-pwrap", .data = &pwrap_mt8186 },
2143     { .compatible = "mediatek,mt8195-pwrap", .data = &pwrap_mt8195 },
2144     { .compatible = "mediatek,mt8516-pwrap", .data = &pwrap_mt8516 },
2145     { /* sentinel */ }
2146 };
2147 MODULE_DEVICE_TABLE(of, of_pwrap_match_tbl);
2148 
2149 static int pwrap_probe(struct platform_device *pdev)
2150 {
2151     int ret, irq;
2152     u32 mask_done;
2153     struct pmic_wrapper *wrp;
2154     struct device_node *np = pdev->dev.of_node;
2155     const struct of_device_id *of_slave_id = NULL;
2156 
2157     if (np->child)
2158         of_slave_id = of_match_node(of_slave_match_tbl, np->child);
2159 
2160     if (!of_slave_id) {
2161         dev_dbg(&pdev->dev, "slave pmic should be defined in dts\n");
2162         return -EINVAL;
2163     }
2164 
2165     wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2166     if (!wrp)
2167         return -ENOMEM;
2168 
2169     platform_set_drvdata(pdev, wrp);
2170 
2171     wrp->master = of_device_get_match_data(&pdev->dev);
2172     wrp->slave = of_slave_id->data;
2173     wrp->dev = &pdev->dev;
2174 
2175     wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap");
2176     if (IS_ERR(wrp->base))
2177         return PTR_ERR(wrp->base);
2178 
2179     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2180         wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2181         if (IS_ERR(wrp->rstc)) {
2182             ret = PTR_ERR(wrp->rstc);
2183             dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2184             return ret;
2185         }
2186     }
2187 
2188     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2189         wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge");
2190         if (IS_ERR(wrp->bridge_base))
2191             return PTR_ERR(wrp->bridge_base);
2192 
2193         wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2194                               "pwrap-bridge");
2195         if (IS_ERR(wrp->rstc_bridge)) {
2196             ret = PTR_ERR(wrp->rstc_bridge);
2197             dev_dbg(wrp->dev,
2198                 "cannot get pwrap-bridge reset: %d\n", ret);
2199             return ret;
2200         }
2201     }
2202 
2203     wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2204     if (IS_ERR(wrp->clk_spi)) {
2205         dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2206             PTR_ERR(wrp->clk_spi));
2207         return PTR_ERR(wrp->clk_spi);
2208     }
2209 
2210     wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2211     if (IS_ERR(wrp->clk_wrap)) {
2212         dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2213             PTR_ERR(wrp->clk_wrap));
2214         return PTR_ERR(wrp->clk_wrap);
2215     }
2216 
2217     ret = clk_prepare_enable(wrp->clk_spi);
2218     if (ret)
2219         return ret;
2220 
2221     ret = clk_prepare_enable(wrp->clk_wrap);
2222     if (ret)
2223         goto err_out1;
2224 
2225     /* Enable internal dynamic clock */
2226     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2227         pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2228         pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2229     }
2230 
2231     /*
2232      * The PMIC could already be initialized by the bootloader.
2233      * Skip initialization here in this case.
2234      */
2235     if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2236         ret = pwrap_init(wrp);
2237         if (ret) {
2238             dev_dbg(wrp->dev, "init failed with %d\n", ret);
2239             goto err_out2;
2240         }
2241     }
2242 
2243     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2244         mask_done = PWRAP_STATE_INIT_DONE1;
2245     else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))
2246         mask_done = PWRAP_STATE_INIT_DONE0_MT8186;
2247     else
2248         mask_done = PWRAP_STATE_INIT_DONE0;
2249 
2250     if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {
2251         dev_dbg(wrp->dev, "initialization isn't finished\n");
2252         ret = -ENODEV;
2253         goto err_out2;
2254     }
2255 
2256     /* Initialize watchdog, may not be done by the bootloader */
2257     if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2258         pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2259 
2260     /*
2261      * Since STAUPD was not used on mt8173 platform,
2262      * so STAUPD of WDT_SRC which should be turned off
2263      */
2264     pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2265     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2266         pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2267 
2268     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2269         pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
2270     else
2271         pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2272 
2273     pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2274     /*
2275      * We add INT1 interrupt to handle starvation and request exception
2276      * If we support it, we should enable it here.
2277      */
2278     if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2279         pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2280 
2281     irq = platform_get_irq(pdev, 0);
2282     if (irq < 0) {
2283         ret = irq;
2284         goto err_out2;
2285     }
2286 
2287     ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2288                    IRQF_TRIGGER_HIGH,
2289                    "mt-pmic-pwrap", wrp);
2290     if (ret)
2291         goto err_out2;
2292 
2293     wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap);
2294     if (IS_ERR(wrp->regmap)) {
2295         ret = PTR_ERR(wrp->regmap);
2296         goto err_out2;
2297     }
2298 
2299     ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2300     if (ret) {
2301         dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2302                 np);
2303         goto err_out2;
2304     }
2305 
2306     return 0;
2307 
2308 err_out2:
2309     clk_disable_unprepare(wrp->clk_wrap);
2310 err_out1:
2311     clk_disable_unprepare(wrp->clk_spi);
2312 
2313     return ret;
2314 }
2315 
2316 static struct platform_driver pwrap_drv = {
2317     .driver = {
2318         .name = "mt-pmic-pwrap",
2319         .of_match_table = of_match_ptr(of_pwrap_match_tbl),
2320     },
2321     .probe = pwrap_probe,
2322 };
2323 
2324 module_platform_driver(pwrap_drv);
2325 
2326 MODULE_AUTHOR("Flora Fu, MediaTek");
2327 MODULE_DESCRIPTION("MediaTek MT8135 PMIC Wrapper Driver");
2328 MODULE_LICENSE("GPL v2");
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