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0006 #include <linux/clk.h>
0007 #include <linux/iopoll.h>
0008 #include <linux/module.h>
0009 #include <linux/of_device.h>
0010 #include <linux/of_address.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/regmap.h>
0013 #include <linux/soc/mediatek/mtk-mmsys.h>
0014 #include <linux/soc/mediatek/mtk-mutex.h>
0015 #include <linux/soc/mediatek/mtk-cmdq.h>
0016
0017 #define MT2701_MUTEX0_MOD0 0x2c
0018 #define MT2701_MUTEX0_SOF0 0x30
0019 #define MT8183_MUTEX0_MOD0 0x30
0020 #define MT8183_MUTEX0_SOF0 0x2c
0021
0022 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
0023 #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
0024 #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
0025 #define DISP_REG_MUTEX_MOD(mutex_mod_reg, n) (mutex_mod_reg + 0x20 * (n))
0026 #define DISP_REG_MUTEX_SOF(mutex_sof_reg, n) (mutex_sof_reg + 0x20 * (n))
0027 #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
0028
0029 #define INT_MUTEX BIT(1)
0030
0031 #define MT8186_MUTEX_MOD_DISP_OVL0 0
0032 #define MT8186_MUTEX_MOD_DISP_OVL0_2L 1
0033 #define MT8186_MUTEX_MOD_DISP_RDMA0 2
0034 #define MT8186_MUTEX_MOD_DISP_COLOR0 4
0035 #define MT8186_MUTEX_MOD_DISP_CCORR0 5
0036 #define MT8186_MUTEX_MOD_DISP_AAL0 7
0037 #define MT8186_MUTEX_MOD_DISP_GAMMA0 8
0038 #define MT8186_MUTEX_MOD_DISP_POSTMASK0 9
0039 #define MT8186_MUTEX_MOD_DISP_DITHER0 10
0040 #define MT8186_MUTEX_MOD_DISP_RDMA1 17
0041
0042 #define MT8186_MUTEX_SOF_SINGLE_MODE 0
0043 #define MT8186_MUTEX_SOF_DSI0 1
0044 #define MT8186_MUTEX_SOF_DPI0 2
0045 #define MT8186_MUTEX_EOF_DSI0 (MT8186_MUTEX_SOF_DSI0 << 6)
0046 #define MT8186_MUTEX_EOF_DPI0 (MT8186_MUTEX_SOF_DPI0 << 6)
0047
0048 #define MT8167_MUTEX_MOD_DISP_PWM 1
0049 #define MT8167_MUTEX_MOD_DISP_OVL0 6
0050 #define MT8167_MUTEX_MOD_DISP_OVL1 7
0051 #define MT8167_MUTEX_MOD_DISP_RDMA0 8
0052 #define MT8167_MUTEX_MOD_DISP_RDMA1 9
0053 #define MT8167_MUTEX_MOD_DISP_WDMA0 10
0054 #define MT8167_MUTEX_MOD_DISP_CCORR 11
0055 #define MT8167_MUTEX_MOD_DISP_COLOR 12
0056 #define MT8167_MUTEX_MOD_DISP_AAL 13
0057 #define MT8167_MUTEX_MOD_DISP_GAMMA 14
0058 #define MT8167_MUTEX_MOD_DISP_DITHER 15
0059 #define MT8167_MUTEX_MOD_DISP_UFOE 16
0060
0061 #define MT8192_MUTEX_MOD_DISP_OVL0 0
0062 #define MT8192_MUTEX_MOD_DISP_OVL0_2L 1
0063 #define MT8192_MUTEX_MOD_DISP_RDMA0 2
0064 #define MT8192_MUTEX_MOD_DISP_COLOR0 4
0065 #define MT8192_MUTEX_MOD_DISP_CCORR0 5
0066 #define MT8192_MUTEX_MOD_DISP_AAL0 6
0067 #define MT8192_MUTEX_MOD_DISP_GAMMA0 7
0068 #define MT8192_MUTEX_MOD_DISP_POSTMASK0 8
0069 #define MT8192_MUTEX_MOD_DISP_DITHER0 9
0070 #define MT8192_MUTEX_MOD_DISP_OVL2_2L 16
0071 #define MT8192_MUTEX_MOD_DISP_RDMA4 17
0072
0073 #define MT8183_MUTEX_MOD_DISP_RDMA0 0
0074 #define MT8183_MUTEX_MOD_DISP_RDMA1 1
0075 #define MT8183_MUTEX_MOD_DISP_OVL0 9
0076 #define MT8183_MUTEX_MOD_DISP_OVL0_2L 10
0077 #define MT8183_MUTEX_MOD_DISP_OVL1_2L 11
0078 #define MT8183_MUTEX_MOD_DISP_WDMA0 12
0079 #define MT8183_MUTEX_MOD_DISP_COLOR0 13
0080 #define MT8183_MUTEX_MOD_DISP_CCORR0 14
0081 #define MT8183_MUTEX_MOD_DISP_AAL0 15
0082 #define MT8183_MUTEX_MOD_DISP_GAMMA0 16
0083 #define MT8183_MUTEX_MOD_DISP_DITHER0 17
0084
0085 #define MT8183_MUTEX_MOD_MDP_RDMA0 2
0086 #define MT8183_MUTEX_MOD_MDP_RSZ0 4
0087 #define MT8183_MUTEX_MOD_MDP_RSZ1 5
0088 #define MT8183_MUTEX_MOD_MDP_TDSHP0 6
0089 #define MT8183_MUTEX_MOD_MDP_WROT0 7
0090 #define MT8183_MUTEX_MOD_MDP_WDMA 8
0091 #define MT8183_MUTEX_MOD_MDP_AAL0 23
0092 #define MT8183_MUTEX_MOD_MDP_CCORR0 24
0093
0094 #define MT8173_MUTEX_MOD_DISP_OVL0 11
0095 #define MT8173_MUTEX_MOD_DISP_OVL1 12
0096 #define MT8173_MUTEX_MOD_DISP_RDMA0 13
0097 #define MT8173_MUTEX_MOD_DISP_RDMA1 14
0098 #define MT8173_MUTEX_MOD_DISP_RDMA2 15
0099 #define MT8173_MUTEX_MOD_DISP_WDMA0 16
0100 #define MT8173_MUTEX_MOD_DISP_WDMA1 17
0101 #define MT8173_MUTEX_MOD_DISP_COLOR0 18
0102 #define MT8173_MUTEX_MOD_DISP_COLOR1 19
0103 #define MT8173_MUTEX_MOD_DISP_AAL 20
0104 #define MT8173_MUTEX_MOD_DISP_GAMMA 21
0105 #define MT8173_MUTEX_MOD_DISP_UFOE 22
0106 #define MT8173_MUTEX_MOD_DISP_PWM0 23
0107 #define MT8173_MUTEX_MOD_DISP_PWM1 24
0108 #define MT8173_MUTEX_MOD_DISP_OD 25
0109
0110 #define MT8195_MUTEX_MOD_DISP_OVL0 0
0111 #define MT8195_MUTEX_MOD_DISP_WDMA0 1
0112 #define MT8195_MUTEX_MOD_DISP_RDMA0 2
0113 #define MT8195_MUTEX_MOD_DISP_COLOR0 3
0114 #define MT8195_MUTEX_MOD_DISP_CCORR0 4
0115 #define MT8195_MUTEX_MOD_DISP_AAL0 5
0116 #define MT8195_MUTEX_MOD_DISP_GAMMA0 6
0117 #define MT8195_MUTEX_MOD_DISP_DITHER0 7
0118 #define MT8195_MUTEX_MOD_DISP_DSI0 8
0119 #define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
0120 #define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
0121 #define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
0122 #define MT8195_MUTEX_MOD_DISP_PWM0 27
0123
0124 #define MT8365_MUTEX_MOD_DISP_OVL0 7
0125 #define MT8365_MUTEX_MOD_DISP_OVL0_2L 8
0126 #define MT8365_MUTEX_MOD_DISP_RDMA0 9
0127 #define MT8365_MUTEX_MOD_DISP_RDMA1 10
0128 #define MT8365_MUTEX_MOD_DISP_WDMA0 11
0129 #define MT8365_MUTEX_MOD_DISP_COLOR0 12
0130 #define MT8365_MUTEX_MOD_DISP_CCORR 13
0131 #define MT8365_MUTEX_MOD_DISP_AAL 14
0132 #define MT8365_MUTEX_MOD_DISP_GAMMA 15
0133 #define MT8365_MUTEX_MOD_DISP_DITHER 16
0134 #define MT8365_MUTEX_MOD_DISP_DSI0 17
0135 #define MT8365_MUTEX_MOD_DISP_PWM0 20
0136 #define MT8365_MUTEX_MOD_DISP_DPI0 22
0137
0138 #define MT2712_MUTEX_MOD_DISP_PWM2 10
0139 #define MT2712_MUTEX_MOD_DISP_OVL0 11
0140 #define MT2712_MUTEX_MOD_DISP_OVL1 12
0141 #define MT2712_MUTEX_MOD_DISP_RDMA0 13
0142 #define MT2712_MUTEX_MOD_DISP_RDMA1 14
0143 #define MT2712_MUTEX_MOD_DISP_RDMA2 15
0144 #define MT2712_MUTEX_MOD_DISP_WDMA0 16
0145 #define MT2712_MUTEX_MOD_DISP_WDMA1 17
0146 #define MT2712_MUTEX_MOD_DISP_COLOR0 18
0147 #define MT2712_MUTEX_MOD_DISP_COLOR1 19
0148 #define MT2712_MUTEX_MOD_DISP_AAL0 20
0149 #define MT2712_MUTEX_MOD_DISP_UFOE 22
0150 #define MT2712_MUTEX_MOD_DISP_PWM0 23
0151 #define MT2712_MUTEX_MOD_DISP_PWM1 24
0152 #define MT2712_MUTEX_MOD_DISP_OD0 25
0153 #define MT2712_MUTEX_MOD2_DISP_AAL1 33
0154 #define MT2712_MUTEX_MOD2_DISP_OD1 34
0155
0156 #define MT2701_MUTEX_MOD_DISP_OVL 3
0157 #define MT2701_MUTEX_MOD_DISP_WDMA 6
0158 #define MT2701_MUTEX_MOD_DISP_COLOR 7
0159 #define MT2701_MUTEX_MOD_DISP_BLS 9
0160 #define MT2701_MUTEX_MOD_DISP_RDMA0 10
0161 #define MT2701_MUTEX_MOD_DISP_RDMA1 12
0162
0163 #define MT2712_MUTEX_SOF_SINGLE_MODE 0
0164 #define MT2712_MUTEX_SOF_DSI0 1
0165 #define MT2712_MUTEX_SOF_DSI1 2
0166 #define MT2712_MUTEX_SOF_DPI0 3
0167 #define MT2712_MUTEX_SOF_DPI1 4
0168 #define MT2712_MUTEX_SOF_DSI2 5
0169 #define MT2712_MUTEX_SOF_DSI3 6
0170 #define MT8167_MUTEX_SOF_DPI0 2
0171 #define MT8167_MUTEX_SOF_DPI1 3
0172 #define MT8183_MUTEX_SOF_DSI0 1
0173 #define MT8183_MUTEX_SOF_DPI0 2
0174 #define MT8195_MUTEX_SOF_DSI0 1
0175 #define MT8195_MUTEX_SOF_DSI1 2
0176 #define MT8195_MUTEX_SOF_DP_INTF0 3
0177 #define MT8195_MUTEX_SOF_DP_INTF1 4
0178 #define MT8195_MUTEX_SOF_DPI0 6
0179 #define MT8195_MUTEX_SOF_DPI1 5
0180
0181 #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
0182 #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
0183 #define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
0184 #define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
0185 #define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
0186 #define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
0187 #define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
0188 #define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
0189
0190 struct mtk_mutex {
0191 int id;
0192 bool claimed;
0193 };
0194
0195 enum mtk_mutex_sof_id {
0196 MUTEX_SOF_SINGLE_MODE,
0197 MUTEX_SOF_DSI0,
0198 MUTEX_SOF_DSI1,
0199 MUTEX_SOF_DPI0,
0200 MUTEX_SOF_DPI1,
0201 MUTEX_SOF_DSI2,
0202 MUTEX_SOF_DSI3,
0203 MUTEX_SOF_DP_INTF0,
0204 MUTEX_SOF_DP_INTF1,
0205 DDP_MUTEX_SOF_MAX,
0206 };
0207
0208 struct mtk_mutex_data {
0209 const unsigned int *mutex_mod;
0210 const unsigned int *mutex_sof;
0211 const unsigned int mutex_mod_reg;
0212 const unsigned int mutex_sof_reg;
0213 const unsigned int *mutex_table_mod;
0214 const bool no_clk;
0215 };
0216
0217 struct mtk_mutex_ctx {
0218 struct device *dev;
0219 struct clk *clk;
0220 void __iomem *regs;
0221 struct mtk_mutex mutex[10];
0222 const struct mtk_mutex_data *data;
0223 phys_addr_t addr;
0224 struct cmdq_client_reg cmdq_reg;
0225 };
0226
0227 static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0228 [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS,
0229 [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR,
0230 [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL,
0231 [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0,
0232 [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1,
0233 [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
0234 };
0235
0236 static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0237 [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
0238 [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
0239 [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
0240 [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
0241 [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
0242 [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
0243 [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
0244 [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
0245 [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
0246 [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
0247 [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
0248 [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
0249 [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
0250 [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
0251 [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
0252 [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
0253 [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
0254 };
0255
0256 static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0257 [DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
0258 [DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
0259 [DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
0260 [DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
0261 [DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
0262 [DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
0263 [DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
0264 [DDP_COMPONENT_PWM0] = MT8167_MUTEX_MOD_DISP_PWM,
0265 [DDP_COMPONENT_RDMA0] = MT8167_MUTEX_MOD_DISP_RDMA0,
0266 [DDP_COMPONENT_RDMA1] = MT8167_MUTEX_MOD_DISP_RDMA1,
0267 [DDP_COMPONENT_UFOE] = MT8167_MUTEX_MOD_DISP_UFOE,
0268 [DDP_COMPONENT_WDMA0] = MT8167_MUTEX_MOD_DISP_WDMA0,
0269 };
0270
0271 static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0272 [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
0273 [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
0274 [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
0275 [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
0276 [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
0277 [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
0278 [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
0279 [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
0280 [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1,
0281 [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0,
0282 [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1,
0283 [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2,
0284 [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE,
0285 [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0,
0286 [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1,
0287 };
0288
0289 static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0290 [DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
0291 [DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
0292 [DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
0293 [DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
0294 [DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
0295 [DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
0296 [DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
0297 [DDP_COMPONENT_OVL_2L1] = MT8183_MUTEX_MOD_DISP_OVL1_2L,
0298 [DDP_COMPONENT_RDMA0] = MT8183_MUTEX_MOD_DISP_RDMA0,
0299 [DDP_COMPONENT_RDMA1] = MT8183_MUTEX_MOD_DISP_RDMA1,
0300 [DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
0301 };
0302
0303 static const unsigned int mt8183_mutex_table_mod[MUTEX_MOD_IDX_MAX] = {
0304 [MUTEX_MOD_IDX_MDP_RDMA0] = MT8183_MUTEX_MOD_MDP_RDMA0,
0305 [MUTEX_MOD_IDX_MDP_RSZ0] = MT8183_MUTEX_MOD_MDP_RSZ0,
0306 [MUTEX_MOD_IDX_MDP_RSZ1] = MT8183_MUTEX_MOD_MDP_RSZ1,
0307 [MUTEX_MOD_IDX_MDP_TDSHP0] = MT8183_MUTEX_MOD_MDP_TDSHP0,
0308 [MUTEX_MOD_IDX_MDP_WROT0] = MT8183_MUTEX_MOD_MDP_WROT0,
0309 [MUTEX_MOD_IDX_MDP_WDMA] = MT8183_MUTEX_MOD_MDP_WDMA,
0310 [MUTEX_MOD_IDX_MDP_AAL0] = MT8183_MUTEX_MOD_MDP_AAL0,
0311 [MUTEX_MOD_IDX_MDP_CCORR0] = MT8183_MUTEX_MOD_MDP_CCORR0,
0312 };
0313
0314 static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0315 [DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
0316 [DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
0317 [DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
0318 [DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
0319 [DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
0320 [DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
0321 [DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
0322 [DDP_COMPONENT_POSTMASK0] = MT8186_MUTEX_MOD_DISP_POSTMASK0,
0323 [DDP_COMPONENT_RDMA0] = MT8186_MUTEX_MOD_DISP_RDMA0,
0324 [DDP_COMPONENT_RDMA1] = MT8186_MUTEX_MOD_DISP_RDMA1,
0325 };
0326
0327 static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0328 [DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
0329 [DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
0330 [DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
0331 [DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
0332 [DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
0333 [DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
0334 [DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
0335 [DDP_COMPONENT_OVL_2L0] = MT8192_MUTEX_MOD_DISP_OVL0_2L,
0336 [DDP_COMPONENT_OVL_2L2] = MT8192_MUTEX_MOD_DISP_OVL2_2L,
0337 [DDP_COMPONENT_RDMA0] = MT8192_MUTEX_MOD_DISP_RDMA0,
0338 [DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
0339 };
0340
0341 static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0342 [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
0343 [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
0344 [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
0345 [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
0346 [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
0347 [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
0348 [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
0349 [DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
0350 [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
0351 [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
0352 [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
0353 [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
0354 [DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
0355 };
0356
0357 static const unsigned int mt8365_mutex_mod[DDP_COMPONENT_ID_MAX] = {
0358 [DDP_COMPONENT_AAL0] = MT8365_MUTEX_MOD_DISP_AAL,
0359 [DDP_COMPONENT_CCORR] = MT8365_MUTEX_MOD_DISP_CCORR,
0360 [DDP_COMPONENT_COLOR0] = MT8365_MUTEX_MOD_DISP_COLOR0,
0361 [DDP_COMPONENT_DITHER0] = MT8365_MUTEX_MOD_DISP_DITHER,
0362 [DDP_COMPONENT_DPI0] = MT8365_MUTEX_MOD_DISP_DPI0,
0363 [DDP_COMPONENT_DSI0] = MT8365_MUTEX_MOD_DISP_DSI0,
0364 [DDP_COMPONENT_GAMMA] = MT8365_MUTEX_MOD_DISP_GAMMA,
0365 [DDP_COMPONENT_OVL0] = MT8365_MUTEX_MOD_DISP_OVL0,
0366 [DDP_COMPONENT_OVL_2L0] = MT8365_MUTEX_MOD_DISP_OVL0_2L,
0367 [DDP_COMPONENT_PWM0] = MT8365_MUTEX_MOD_DISP_PWM0,
0368 [DDP_COMPONENT_RDMA0] = MT8365_MUTEX_MOD_DISP_RDMA0,
0369 [DDP_COMPONENT_RDMA1] = MT8365_MUTEX_MOD_DISP_RDMA1,
0370 [DDP_COMPONENT_WDMA0] = MT8365_MUTEX_MOD_DISP_WDMA0,
0371 };
0372
0373 static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
0374 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
0375 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
0376 [MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
0377 [MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0,
0378 [MUTEX_SOF_DPI1] = MUTEX_SOF_DPI1,
0379 [MUTEX_SOF_DSI2] = MUTEX_SOF_DSI2,
0380 [MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
0381 };
0382
0383 static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
0384 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
0385 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
0386 [MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
0387 [MUTEX_SOF_DPI1] = MT8167_MUTEX_SOF_DPI1,
0388 };
0389
0390
0391 static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
0392 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
0393 [MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
0394 [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
0395 };
0396
0397 static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
0398 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
0399 [MUTEX_SOF_DSI0] = MT8186_MUTEX_SOF_DSI0 | MT8186_MUTEX_EOF_DSI0,
0400 [MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
0401 };
0402
0403
0404
0405
0406
0407
0408
0409
0410
0411 static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
0412 [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
0413 [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
0414 [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
0415 [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
0416 [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
0417 [MUTEX_SOF_DP_INTF0] =
0418 MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
0419 [MUTEX_SOF_DP_INTF1] =
0420 MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
0421 };
0422
0423 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
0424 .mutex_mod = mt2701_mutex_mod,
0425 .mutex_sof = mt2712_mutex_sof,
0426 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
0427 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
0428 };
0429
0430 static const struct mtk_mutex_data mt2712_mutex_driver_data = {
0431 .mutex_mod = mt2712_mutex_mod,
0432 .mutex_sof = mt2712_mutex_sof,
0433 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
0434 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
0435 };
0436
0437 static const struct mtk_mutex_data mt8167_mutex_driver_data = {
0438 .mutex_mod = mt8167_mutex_mod,
0439 .mutex_sof = mt8167_mutex_sof,
0440 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
0441 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
0442 .no_clk = true,
0443 };
0444
0445 static const struct mtk_mutex_data mt8173_mutex_driver_data = {
0446 .mutex_mod = mt8173_mutex_mod,
0447 .mutex_sof = mt2712_mutex_sof,
0448 .mutex_mod_reg = MT2701_MUTEX0_MOD0,
0449 .mutex_sof_reg = MT2701_MUTEX0_SOF0,
0450 };
0451
0452 static const struct mtk_mutex_data mt8183_mutex_driver_data = {
0453 .mutex_mod = mt8183_mutex_mod,
0454 .mutex_sof = mt8183_mutex_sof,
0455 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
0456 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
0457 .mutex_table_mod = mt8183_mutex_table_mod,
0458 .no_clk = true,
0459 };
0460
0461 static const struct mtk_mutex_data mt8186_mutex_driver_data = {
0462 .mutex_mod = mt8186_mutex_mod,
0463 .mutex_sof = mt8186_mutex_sof,
0464 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
0465 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
0466 };
0467
0468 static const struct mtk_mutex_data mt8192_mutex_driver_data = {
0469 .mutex_mod = mt8192_mutex_mod,
0470 .mutex_sof = mt8183_mutex_sof,
0471 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
0472 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
0473 };
0474
0475 static const struct mtk_mutex_data mt8195_mutex_driver_data = {
0476 .mutex_mod = mt8195_mutex_mod,
0477 .mutex_sof = mt8195_mutex_sof,
0478 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
0479 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
0480 };
0481
0482 static const struct mtk_mutex_data mt8365_mutex_driver_data = {
0483 .mutex_mod = mt8365_mutex_mod,
0484 .mutex_sof = mt8183_mutex_sof,
0485 .mutex_mod_reg = MT8183_MUTEX0_MOD0,
0486 .mutex_sof_reg = MT8183_MUTEX0_SOF0,
0487 .no_clk = true,
0488 };
0489
0490 struct mtk_mutex *mtk_mutex_get(struct device *dev)
0491 {
0492 struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
0493 int i;
0494
0495 for (i = 0; i < 10; i++)
0496 if (!mtx->mutex[i].claimed) {
0497 mtx->mutex[i].claimed = true;
0498 return &mtx->mutex[i];
0499 }
0500
0501 return ERR_PTR(-EBUSY);
0502 }
0503 EXPORT_SYMBOL_GPL(mtk_mutex_get);
0504
0505 void mtk_mutex_put(struct mtk_mutex *mutex)
0506 {
0507 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0508 mutex[mutex->id]);
0509
0510 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0511
0512 mutex->claimed = false;
0513 }
0514 EXPORT_SYMBOL_GPL(mtk_mutex_put);
0515
0516 int mtk_mutex_prepare(struct mtk_mutex *mutex)
0517 {
0518 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0519 mutex[mutex->id]);
0520 return clk_prepare_enable(mtx->clk);
0521 }
0522 EXPORT_SYMBOL_GPL(mtk_mutex_prepare);
0523
0524 void mtk_mutex_unprepare(struct mtk_mutex *mutex)
0525 {
0526 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0527 mutex[mutex->id]);
0528 clk_disable_unprepare(mtx->clk);
0529 }
0530 EXPORT_SYMBOL_GPL(mtk_mutex_unprepare);
0531
0532 void mtk_mutex_add_comp(struct mtk_mutex *mutex,
0533 enum mtk_ddp_comp_id id)
0534 {
0535 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0536 mutex[mutex->id]);
0537 unsigned int reg;
0538 unsigned int sof_id;
0539 unsigned int offset;
0540
0541 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0542
0543 switch (id) {
0544 case DDP_COMPONENT_DSI0:
0545 sof_id = MUTEX_SOF_DSI0;
0546 break;
0547 case DDP_COMPONENT_DSI1:
0548 sof_id = MUTEX_SOF_DSI0;
0549 break;
0550 case DDP_COMPONENT_DSI2:
0551 sof_id = MUTEX_SOF_DSI2;
0552 break;
0553 case DDP_COMPONENT_DSI3:
0554 sof_id = MUTEX_SOF_DSI3;
0555 break;
0556 case DDP_COMPONENT_DPI0:
0557 sof_id = MUTEX_SOF_DPI0;
0558 break;
0559 case DDP_COMPONENT_DPI1:
0560 sof_id = MUTEX_SOF_DPI1;
0561 break;
0562 case DDP_COMPONENT_DP_INTF0:
0563 sof_id = MUTEX_SOF_DP_INTF0;
0564 break;
0565 default:
0566 if (mtx->data->mutex_mod[id] < 32) {
0567 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
0568 mutex->id);
0569 reg = readl_relaxed(mtx->regs + offset);
0570 reg |= 1 << mtx->data->mutex_mod[id];
0571 writel_relaxed(reg, mtx->regs + offset);
0572 } else {
0573 offset = DISP_REG_MUTEX_MOD2(mutex->id);
0574 reg = readl_relaxed(mtx->regs + offset);
0575 reg |= 1 << (mtx->data->mutex_mod[id] - 32);
0576 writel_relaxed(reg, mtx->regs + offset);
0577 }
0578 return;
0579 }
0580
0581 writel_relaxed(mtx->data->mutex_sof[sof_id],
0582 mtx->regs +
0583 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
0584 }
0585 EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
0586
0587 void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
0588 enum mtk_ddp_comp_id id)
0589 {
0590 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0591 mutex[mutex->id]);
0592 unsigned int reg;
0593 unsigned int offset;
0594
0595 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0596
0597 switch (id) {
0598 case DDP_COMPONENT_DSI0:
0599 case DDP_COMPONENT_DSI1:
0600 case DDP_COMPONENT_DSI2:
0601 case DDP_COMPONENT_DSI3:
0602 case DDP_COMPONENT_DPI0:
0603 case DDP_COMPONENT_DPI1:
0604 case DDP_COMPONENT_DP_INTF0:
0605 writel_relaxed(MUTEX_SOF_SINGLE_MODE,
0606 mtx->regs +
0607 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
0608 mutex->id));
0609 break;
0610 default:
0611 if (mtx->data->mutex_mod[id] < 32) {
0612 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
0613 mutex->id);
0614 reg = readl_relaxed(mtx->regs + offset);
0615 reg &= ~(1 << mtx->data->mutex_mod[id]);
0616 writel_relaxed(reg, mtx->regs + offset);
0617 } else {
0618 offset = DISP_REG_MUTEX_MOD2(mutex->id);
0619 reg = readl_relaxed(mtx->regs + offset);
0620 reg &= ~(1 << (mtx->data->mutex_mod[id] - 32));
0621 writel_relaxed(reg, mtx->regs + offset);
0622 }
0623 break;
0624 }
0625 }
0626 EXPORT_SYMBOL_GPL(mtk_mutex_remove_comp);
0627
0628 void mtk_mutex_enable(struct mtk_mutex *mutex)
0629 {
0630 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0631 mutex[mutex->id]);
0632
0633 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0634
0635 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
0636 }
0637 EXPORT_SYMBOL_GPL(mtk_mutex_enable);
0638
0639 int mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex, void *pkt)
0640 {
0641 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0642 mutex[mutex->id]);
0643 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0644 struct cmdq_pkt *cmdq_pkt = (struct cmdq_pkt *)pkt;
0645
0646 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0647
0648 if (!mtx->cmdq_reg.size) {
0649 dev_err(mtx->dev, "mediatek,gce-client-reg hasn't been set");
0650 return -EINVAL;
0651 }
0652
0653 cmdq_pkt_write(cmdq_pkt, mtx->cmdq_reg.subsys,
0654 mtx->addr + DISP_REG_MUTEX_EN(mutex->id), 1);
0655 return 0;
0656 #else
0657 dev_err(mtx->dev, "Not support for enable MUTEX by CMDQ");
0658 return -ENODEV;
0659 #endif
0660 }
0661 EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
0662
0663 void mtk_mutex_disable(struct mtk_mutex *mutex)
0664 {
0665 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0666 mutex[mutex->id]);
0667
0668 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0669
0670 writel(0, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
0671 }
0672 EXPORT_SYMBOL_GPL(mtk_mutex_disable);
0673
0674 void mtk_mutex_acquire(struct mtk_mutex *mutex)
0675 {
0676 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0677 mutex[mutex->id]);
0678 u32 tmp;
0679
0680 writel(1, mtx->regs + DISP_REG_MUTEX_EN(mutex->id));
0681 writel(1, mtx->regs + DISP_REG_MUTEX(mutex->id));
0682 if (readl_poll_timeout_atomic(mtx->regs + DISP_REG_MUTEX(mutex->id),
0683 tmp, tmp & INT_MUTEX, 1, 10000))
0684 pr_err("could not acquire mutex %d\n", mutex->id);
0685 }
0686 EXPORT_SYMBOL_GPL(mtk_mutex_acquire);
0687
0688 void mtk_mutex_release(struct mtk_mutex *mutex)
0689 {
0690 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0691 mutex[mutex->id]);
0692
0693 writel(0, mtx->regs + DISP_REG_MUTEX(mutex->id));
0694 }
0695 EXPORT_SYMBOL_GPL(mtk_mutex_release);
0696
0697 int mtk_mutex_write_mod(struct mtk_mutex *mutex,
0698 enum mtk_mutex_mod_index idx, bool clear)
0699 {
0700 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0701 mutex[mutex->id]);
0702 unsigned int reg;
0703 unsigned int offset;
0704
0705 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0706
0707 if (idx < MUTEX_MOD_IDX_MDP_RDMA0 ||
0708 idx >= MUTEX_MOD_IDX_MAX) {
0709 dev_err(mtx->dev, "Not supported MOD table index : %d", idx);
0710 return -EINVAL;
0711 }
0712
0713 offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
0714 mutex->id);
0715 reg = readl_relaxed(mtx->regs + offset);
0716
0717 if (clear)
0718 reg &= ~BIT(mtx->data->mutex_table_mod[idx]);
0719 else
0720 reg |= BIT(mtx->data->mutex_table_mod[idx]);
0721
0722 writel_relaxed(reg, mtx->regs + offset);
0723
0724 return 0;
0725 }
0726 EXPORT_SYMBOL_GPL(mtk_mutex_write_mod);
0727
0728 int mtk_mutex_write_sof(struct mtk_mutex *mutex,
0729 enum mtk_mutex_sof_index idx)
0730 {
0731 struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
0732 mutex[mutex->id]);
0733
0734 WARN_ON(&mtx->mutex[mutex->id] != mutex);
0735
0736 if (idx < MUTEX_SOF_IDX_SINGLE_MODE ||
0737 idx >= MUTEX_SOF_IDX_MAX) {
0738 dev_err(mtx->dev, "Not supported SOF index : %d", idx);
0739 return -EINVAL;
0740 }
0741
0742 writel_relaxed(idx, mtx->regs +
0743 DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id));
0744
0745 return 0;
0746 }
0747 EXPORT_SYMBOL_GPL(mtk_mutex_write_sof);
0748
0749 static int mtk_mutex_probe(struct platform_device *pdev)
0750 {
0751 struct device *dev = &pdev->dev;
0752 struct mtk_mutex_ctx *mtx;
0753 struct resource *regs;
0754 int i;
0755 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0756 int ret;
0757 #endif
0758
0759 mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
0760 if (!mtx)
0761 return -ENOMEM;
0762
0763 for (i = 0; i < 10; i++)
0764 mtx->mutex[i].id = i;
0765
0766 mtx->data = of_device_get_match_data(dev);
0767
0768 if (!mtx->data->no_clk) {
0769 mtx->clk = devm_clk_get(dev, NULL);
0770 if (IS_ERR(mtx->clk)) {
0771 if (PTR_ERR(mtx->clk) != -EPROBE_DEFER)
0772 dev_err(dev, "Failed to get clock\n");
0773 return PTR_ERR(mtx->clk);
0774 }
0775 }
0776
0777 mtx->regs = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
0778 if (IS_ERR(mtx->regs)) {
0779 dev_err(dev, "Failed to map mutex registers\n");
0780 return PTR_ERR(mtx->regs);
0781 }
0782 mtx->addr = regs->start;
0783
0784 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
0785 ret = cmdq_dev_get_client_reg(dev, &mtx->cmdq_reg, 0);
0786 if (ret)
0787 dev_dbg(dev, "No mediatek,gce-client-reg!\n");
0788 #endif
0789
0790 platform_set_drvdata(pdev, mtx);
0791
0792 return 0;
0793 }
0794
0795 static int mtk_mutex_remove(struct platform_device *pdev)
0796 {
0797 return 0;
0798 }
0799
0800 static const struct of_device_id mutex_driver_dt_match[] = {
0801 { .compatible = "mediatek,mt2701-disp-mutex",
0802 .data = &mt2701_mutex_driver_data},
0803 { .compatible = "mediatek,mt2712-disp-mutex",
0804 .data = &mt2712_mutex_driver_data},
0805 { .compatible = "mediatek,mt8167-disp-mutex",
0806 .data = &mt8167_mutex_driver_data},
0807 { .compatible = "mediatek,mt8173-disp-mutex",
0808 .data = &mt8173_mutex_driver_data},
0809 { .compatible = "mediatek,mt8183-disp-mutex",
0810 .data = &mt8183_mutex_driver_data},
0811 { .compatible = "mediatek,mt8186-disp-mutex",
0812 .data = &mt8186_mutex_driver_data},
0813 { .compatible = "mediatek,mt8192-disp-mutex",
0814 .data = &mt8192_mutex_driver_data},
0815 { .compatible = "mediatek,mt8195-disp-mutex",
0816 .data = &mt8195_mutex_driver_data},
0817 { .compatible = "mediatek,mt8365-disp-mutex",
0818 .data = &mt8365_mutex_driver_data},
0819 {},
0820 };
0821 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
0822
0823 static struct platform_driver mtk_mutex_driver = {
0824 .probe = mtk_mutex_probe,
0825 .remove = mtk_mutex_remove,
0826 .driver = {
0827 .name = "mediatek-mutex",
0828 .owner = THIS_MODULE,
0829 .of_match_table = mutex_driver_dt_match,
0830 },
0831 };
0832
0833 builtin_platform_driver(mtk_mutex_driver);
