soc/mediatek/mtk-mmsys.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002
0003 #ifndef __SOC_MEDIATEK_MTK_MMSYS_H
0004 #define __SOC_MEDIATEK_MTK_MMSYS_H
0005
0006 #define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN   0x040
0007 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN   0x044
0008 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN     0x048
0009 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN  0x04c
0010 #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN   0x050
0011 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN  0x084
0012 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN  0x088
0013 #define DISP_REG_CONFIG_DSIE_SEL_IN     0x0a4
0014 #define DISP_REG_CONFIG_DSIO_SEL_IN     0x0a8
0015 #define DISP_REG_CONFIG_DPI_SEL_IN      0x0ac
0016 #define DISP_REG_CONFIG_DISP_RDMA2_SOUT     0x0b8
0017 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN  0x0c4
0018 #define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN  0x0c8
0019 #define DISP_REG_CONFIG_MMSYS_CG_CON0       0x100
0020
0021 #define DISP_REG_CONFIG_DISP_OVL_MOUT_EN    0x030
0022 #define DISP_REG_CONFIG_OUT_SEL         0x04c
0023 #define DISP_REG_CONFIG_DSI_SEL         0x050
0024 #define DISP_REG_CONFIG_DPI_SEL         0x064
0025
0026 #define OVL0_MOUT_EN_COLOR0         0x1
0027 #define OD_MOUT_EN_RDMA0            0x1
0028 #define OD1_MOUT_EN_RDMA1           BIT(16)
0029 #define UFOE_MOUT_EN_DSI0           0x1
0030 #define COLOR0_SEL_IN_OVL0          0x1
0031 #define OVL1_MOUT_EN_COLOR1         0x1
0032 #define GAMMA_MOUT_EN_RDMA1         0x1
0033 #define RDMA0_SOUT_DPI0             0x2
0034 #define RDMA0_SOUT_DPI1             0x3
0035 #define RDMA0_SOUT_DSI1             0x1
0036 #define RDMA0_SOUT_DSI2             0x4
0037 #define RDMA0_SOUT_DSI3             0x5
0038 #define RDMA0_SOUT_MASK             0x7
0039 #define RDMA1_SOUT_DPI0             0x2
0040 #define RDMA1_SOUT_DPI1             0x3
0041 #define RDMA1_SOUT_DSI1             0x1
0042 #define RDMA1_SOUT_DSI2             0x4
0043 #define RDMA1_SOUT_DSI3             0x5
0044 #define RDMA1_SOUT_MASK             0x7
0045 #define RDMA2_SOUT_DPI0             0x2
0046 #define RDMA2_SOUT_DPI1             0x3
0047 #define RDMA2_SOUT_DSI1             0x1
0048 #define RDMA2_SOUT_DSI2             0x4
0049 #define RDMA2_SOUT_DSI3             0x5
0050 #define RDMA2_SOUT_MASK             0x7
0051 #define DPI0_SEL_IN_RDMA1           0x1
0052 #define DPI0_SEL_IN_RDMA2           0x3
0053 #define DPI0_SEL_IN_MASK            0x3
0054 #define DPI1_SEL_IN_RDMA1           (0x1 << 8)
0055 #define DPI1_SEL_IN_RDMA2           (0x3 << 8)
0056 #define DPI1_SEL_IN_MASK            (0x3 << 8)
0057 #define DSI0_SEL_IN_RDMA1           0x1
0058 #define DSI0_SEL_IN_RDMA2           0x4
0059 #define DSI0_SEL_IN_MASK            0x7
0060 #define DSI1_SEL_IN_RDMA1           0x1
0061 #define DSI1_SEL_IN_RDMA2           0x4
0062 #define DSI1_SEL_IN_MASK            0x7
0063 #define DSI2_SEL_IN_RDMA1           (0x1 << 16)
0064 #define DSI2_SEL_IN_RDMA2           (0x4 << 16)
0065 #define DSI2_SEL_IN_MASK            (0x7 << 16)
0066 #define DSI3_SEL_IN_RDMA1           (0x1 << 16)
0067 #define DSI3_SEL_IN_RDMA2           (0x4 << 16)
0068 #define DSI3_SEL_IN_MASK            (0x7 << 16)
0069 #define COLOR1_SEL_IN_OVL1          0x1
0070
0071 #define OVL_MOUT_EN_RDMA            0x1
0072 #define BLS_TO_DSI_RDMA1_TO_DPI1        0x8
0073 #define BLS_TO_DPI_RDMA1_TO_DSI         0x2
0074 #define BLS_RDMA1_DSI_DPI_MASK          0xf
0075 #define DSI_SEL_IN_BLS              0x0
0076 #define DPI_SEL_IN_BLS              0x0
0077 #define DPI_SEL_IN_MASK             0x1
0078 #define DSI_SEL_IN_RDMA             0x1
0079 #define DSI_SEL_IN_MASK             0x1
0080
0081 struct mtk_mmsys_routes {
0082     u32 from_comp;
0083     u32 to_comp;
0084     u32 addr;
0085     u32 mask;
0086     u32 val;
0087 };
0088
0089 struct mtk_mmsys_driver_data {
0090     const resource_size_t io_start;
0091     const char *clk_driver;
0092     const struct mtk_mmsys_routes *routes;
0093     const unsigned int num_routes;
0094     const u16 sw0_rst_offset;
0095 };
0096
0097 struct mtk_mmsys_match_data {
0098     unsigned short num_drv_data;
0099     const struct mtk_mmsys_driver_data *drv_data[];
0100 };
0101
0102 /*
0103  * Routes in mt8173, mt2701, mt2712 are different. That means
0104  * in the same register address, it controls different input/output
0105  * selection for each SoC. But, right now, they use the same table as
0106  * default routes meet their requirements. But we don't have the complete
0107  * route information for these three SoC, so just keep them in the same
0108  * table. After we've more information, we could separate mt2701, mt2712
0109  * to an independent table.
0110  */
0111 static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
0112     {
0113         DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
0114         DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
0115         BLS_TO_DSI_RDMA1_TO_DPI1
0116     }, {
0117         DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
0118         DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
0119         DSI_SEL_IN_BLS
0120     }, {
0121         DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
0122         DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
0123         BLS_TO_DPI_RDMA1_TO_DSI
0124     }, {
0125         DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
0126         DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
0127         DSI_SEL_IN_RDMA
0128     }, {
0129         DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
0130         DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
0131         DPI_SEL_IN_BLS
0132     }, {
0133         DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
0134         DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
0135         GAMMA_MOUT_EN_RDMA1
0136     }, {
0137         DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
0138         DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
0139         OD_MOUT_EN_RDMA0
0140     }, {
0141         DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
0142         DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
0143         OD1_MOUT_EN_RDMA1
0144     }, {
0145         DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
0146         DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
0147         OVL0_MOUT_EN_COLOR0
0148     }, {
0149         DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
0150         DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
0151         COLOR0_SEL_IN_OVL0
0152     }, {
0153         DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0154         DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
0155         OVL_MOUT_EN_RDMA
0156     }, {
0157         DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
0158         DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
0159         OVL1_MOUT_EN_COLOR1
0160     }, {
0161         DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
0162         DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
0163         COLOR1_SEL_IN_OVL1
0164     }, {
0165         DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
0166         DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
0167         RDMA0_SOUT_DPI0
0168     }, {
0169         DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
0170         DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
0171         RDMA0_SOUT_DPI1
0172     }, {
0173         DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
0174         DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
0175         RDMA0_SOUT_DSI1
0176     }, {
0177         DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
0178         DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
0179         RDMA0_SOUT_DSI2
0180     }, {
0181         DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
0182         DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
0183         RDMA0_SOUT_DSI3
0184     }, {
0185         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0186         DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
0187         RDMA1_SOUT_DPI0
0188     }, {
0189         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0190         DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
0191         DPI0_SEL_IN_RDMA1
0192     }, {
0193         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
0194         DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
0195         RDMA1_SOUT_DPI1
0196     }, {
0197         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
0198         DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
0199         DPI1_SEL_IN_RDMA1
0200     }, {
0201         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
0202         DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
0203         DSI0_SEL_IN_RDMA1
0204     }, {
0205         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
0206         DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
0207         RDMA1_SOUT_DSI1
0208     }, {
0209         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
0210         DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
0211         DSI1_SEL_IN_RDMA1
0212     }, {
0213         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
0214         DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
0215         RDMA1_SOUT_DSI2
0216     }, {
0217         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
0218         DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
0219         DSI2_SEL_IN_RDMA1
0220     }, {
0221         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
0222         DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
0223         RDMA1_SOUT_DSI3
0224     }, {
0225         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
0226         DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
0227         DSI3_SEL_IN_RDMA1
0228     }, {
0229         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
0230         DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
0231         RDMA2_SOUT_DPI0
0232     }, {
0233         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
0234         DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
0235         DPI0_SEL_IN_RDMA2
0236     }, {
0237         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
0238         DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
0239         RDMA2_SOUT_DPI1
0240     }, {
0241         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
0242         DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
0243         DPI1_SEL_IN_RDMA2
0244     }, {
0245         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
0246         DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
0247         DSI0_SEL_IN_RDMA2
0248     }, {
0249         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
0250         DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
0251         RDMA2_SOUT_DSI1
0252     }, {
0253         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
0254         DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
0255         DSI1_SEL_IN_RDMA2
0256     }, {
0257         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
0258         DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
0259         RDMA2_SOUT_DSI2
0260     }, {
0261         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
0262         DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
0263         DSI2_SEL_IN_RDMA2
0264     }, {
0265         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
0266         DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
0267         RDMA2_SOUT_DSI3
0268     }, {
0269         DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
0270         DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
0271         DSI3_SEL_IN_RDMA2
0272     }, {
0273         DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
0274         DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
0275         UFOE_MOUT_EN_DSI0
0276     }
0277 };
0278
0279 #endif /* __SOC_MEDIATEK_MTK_MMSYS_H */