soc/mediatek/mtk-infracfg.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015 Pengutronix, Sascha Hauer <kernel@pengutronix.de>
0004  */
0005
0006 #include <linux/export.h>
0007 #include <linux/jiffies.h>
0008 #include <linux/regmap.h>
0009 #include <linux/mfd/syscon.h>
0010 #include <linux/soc/mediatek/infracfg.h>
0011 #include <asm/processor.h>
0012
0013 #define MTK_POLL_DELAY_US   10
0014 #define MTK_POLL_TIMEOUT    (jiffies_to_usecs(HZ))
0015
0016 /**
0017  * mtk_infracfg_set_bus_protection - enable bus protection
0018  * @infracfg: The infracfg regmap
0019  * @mask: The mask containing the protection bits to be enabled.
0020  * @reg_update: The boolean flag determines to set the protection bits
0021  *              by regmap_update_bits with enable register(PROTECTEN) or
0022  *              by regmap_write with set register(PROTECTEN_SET).
0023  *
0024  * This function enables the bus protection bits for disabled power
0025  * domains so that the system does not hang when some unit accesses the
0026  * bus while in power down.
0027  */
0028 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask,
0029         bool reg_update)
0030 {
0031     u32 val;
0032     int ret;
0033
0034     if (reg_update)
0035         regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask,
0036                 mask);
0037     else
0038         regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask);
0039
0040     ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
0041                        val, (val & mask) == mask,
0042                        MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
0043
0044     return ret;
0045 }
0046
0047 /**
0048  * mtk_infracfg_clear_bus_protection - disable bus protection
0049  * @infracfg: The infracfg regmap
0050  * @mask: The mask containing the protection bits to be disabled.
0051  * @reg_update: The boolean flag determines to clear the protection bits
0052  *              by regmap_update_bits with enable register(PROTECTEN) or
0053  *              by regmap_write with clear register(PROTECTEN_CLR).
0054  *
0055  * This function disables the bus protection bits previously enabled with
0056  * mtk_infracfg_set_bus_protection.
0057  */
0058
0059 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask,
0060         bool reg_update)
0061 {
0062     int ret;
0063     u32 val;
0064
0065     if (reg_update)
0066         regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0);
0067     else
0068         regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask);
0069
0070     ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1,
0071                        val, !(val & mask),
0072                        MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT);
0073
0074     return ret;
0075 }
0076
0077 static int __init mtk_infracfg_init(void)
0078 {
0079     struct regmap *infracfg;
0080
0081     /*
0082      * MT8192 has an experimental path to route GPU traffic to the DSU's
0083      * Accelerator Coherency Port, which is inadvertently enabled by
0084      * default. It turns out not to work, so disable it to prevent spurious
0085      * GPU faults.
0086      */
0087     infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg");
0088     if (!IS_ERR(infracfg))
0089         regmap_set_bits(infracfg, MT8192_INFRA_CTRL,
0090                 MT8192_INFRA_CTRL_DISABLE_MFG2ACP);
0091     return 0;
0092 }
0093 postcore_initcall(mtk_infracfg_init);