soc/mediatek/mt8365-mmsys.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002
0003 #ifndef __SOC_MEDIATEK_MT8365_MMSYS_H
0004 #define __SOC_MEDIATEK_MT8365_MMSYS_H
0005
0006 #define MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN    0xf3c
0007 #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL  0xf4c
0008 #define MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf50
0009 #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN    0xf54
0010 #define MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN   0xf60
0011 #define MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN   0xf64
0012 #define MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN     0xf68
0013 #define MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL  0xfd0
0014 #define MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN     0xfd8
0015 #define MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00 0xfdc
0016
0017 #define MT8365_RDMA0_SOUT_COLOR0            0x1
0018 #define MT8365_DITHER_MOUT_EN_DSI0          0x1
0019 #define MT8365_DSI0_SEL_IN_DITHER           0x1
0020 #define MT8365_RDMA0_SEL_IN_OVL0            0x0
0021 #define MT8365_RDMA0_RSZ0_SEL_IN_RDMA0          0x0
0022 #define MT8365_DISP_COLOR_SEL_IN_COLOR0         0x0
0023 #define MT8365_OVL0_MOUT_PATH0_SEL          BIT(0)
0024 #define MT8365_RDMA1_SOUT_DPI0              0x1
0025 #define MT8365_DPI0_SEL_IN_RDMA1            0x0
0026 #define MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK     0x1
0027 #define MT8365_DPI0_SEL_IN_RDMA1            0x0
0028
0029 static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
0030     {
0031         DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0032         MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
0033         MT8365_OVL0_MOUT_PATH0_SEL, MT8365_OVL0_MOUT_PATH0_SEL
0034     },
0035     {
0036         DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0037         MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
0038         MT8365_RDMA0_SEL_IN_OVL0, MT8365_RDMA0_SEL_IN_OVL0
0039     },
0040     {
0041         DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
0042         MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
0043         MT8365_RDMA0_SOUT_COLOR0, MT8365_RDMA0_SOUT_COLOR0
0044     },
0045     {
0046         DDP_COMPONENT_COLOR0, DDP_COMPONENT_CCORR,
0047         MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
0048         MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
0049     },
0050     {
0051         DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0052         MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
0053         MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
0054     },
0055     {
0056         DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0057         MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
0058         MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
0059     },
0060     {
0061         DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
0062         MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
0063         MT8365_RDMA0_RSZ0_SEL_IN_RDMA0, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0
0064     },
0065     {
0066         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0067         MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
0068         MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK, MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK
0069     },
0070     {
0071         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0072         MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
0073         MT8365_DPI0_SEL_IN_RDMA1, MT8365_DPI0_SEL_IN_RDMA1
0074     },
0075     {
0076         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0077         MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
0078         MT8365_RDMA1_SOUT_DPI0, MT8365_RDMA1_SOUT_DPI0
0079     },
0080 };
0081
0082 #endif /* __SOC_MEDIATEK_MT8365_MMSYS_H */