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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2021 MediaTek Inc.
0004  * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
0005  */
0006 
0007 #ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
0008 #define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H
0009 
0010 #include "mtk-pm-domains.h"
0011 #include <dt-bindings/power/mt8195-power.h>
0012 
0013 /*
0014  * MT8195 power domain support
0015  */
0016 
0017 static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = {
0018     [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = {
0019         .name = "pcie_mac_p0",
0020         .sta_mask = BIT(11),
0021         .ctl_offs = 0x328,
0022         .pwr_sta_offs = 0x174,
0023         .pwr_sta2nd_offs = 0x178,
0024         .sram_pdn_bits = GENMASK(8, 8),
0025         .sram_pdn_ack_bits = GENMASK(12, 12),
0026         .bp_infracfg = {
0027             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0,
0028                     MT8195_TOP_AXI_PROT_EN_VDNR_SET,
0029                     MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
0030                     MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
0031             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0,
0032                     MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
0033                     MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
0034                     MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
0035         },
0036     },
0037     [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = {
0038         .name = "pcie_mac_p1",
0039         .sta_mask = BIT(12),
0040         .ctl_offs = 0x32C,
0041         .pwr_sta_offs = 0x174,
0042         .pwr_sta2nd_offs = 0x178,
0043         .sram_pdn_bits = GENMASK(8, 8),
0044         .sram_pdn_ack_bits = GENMASK(12, 12),
0045         .bp_infracfg = {
0046             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1,
0047                     MT8195_TOP_AXI_PROT_EN_VDNR_SET,
0048                     MT8195_TOP_AXI_PROT_EN_VDNR_CLR,
0049                     MT8195_TOP_AXI_PROT_EN_VDNR_STA1),
0050             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1,
0051                     MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
0052                     MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
0053                     MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
0054         },
0055     },
0056     [MT8195_POWER_DOMAIN_PCIE_PHY] = {
0057         .name = "pcie_phy",
0058         .sta_mask = BIT(13),
0059         .ctl_offs = 0x330,
0060         .pwr_sta_offs = 0x174,
0061         .pwr_sta2nd_offs = 0x178,
0062         .caps = MTK_SCPD_ACTIVE_WAKEUP,
0063     },
0064     [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = {
0065         .name = "ssusb_pcie_phy",
0066         .sta_mask = BIT(14),
0067         .ctl_offs = 0x334,
0068         .pwr_sta_offs = 0x174,
0069         .pwr_sta2nd_offs = 0x178,
0070         .caps = MTK_SCPD_ACTIVE_WAKEUP | MTK_SCPD_ALWAYS_ON,
0071     },
0072     [MT8195_POWER_DOMAIN_CSI_RX_TOP] = {
0073         .name = "csi_rx_top",
0074         .sta_mask = BIT(18),
0075         .ctl_offs = 0x3C4,
0076         .pwr_sta_offs = 0x174,
0077         .pwr_sta2nd_offs = 0x178,
0078         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0079     },
0080     [MT8195_POWER_DOMAIN_ETHER] = {
0081         .name = "ether",
0082         .sta_mask = BIT(3),
0083         .ctl_offs = 0x344,
0084         .pwr_sta_offs = 0x16c,
0085         .pwr_sta2nd_offs = 0x170,
0086         .sram_pdn_bits = GENMASK(8, 8),
0087         .sram_pdn_ack_bits = GENMASK(12, 12),
0088         .caps = MTK_SCPD_ACTIVE_WAKEUP,
0089     },
0090     [MT8195_POWER_DOMAIN_ADSP] = {
0091         .name = "adsp",
0092         .sta_mask = BIT(10),
0093         .ctl_offs = 0x360,
0094         .pwr_sta_offs = 0x16c,
0095         .pwr_sta2nd_offs = 0x170,
0096         .sram_pdn_bits = GENMASK(8, 8),
0097         .sram_pdn_ack_bits = GENMASK(12, 12),
0098         .bp_infracfg = {
0099             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP,
0100                     MT8195_TOP_AXI_PROT_EN_2_SET,
0101                     MT8195_TOP_AXI_PROT_EN_2_CLR,
0102                     MT8195_TOP_AXI_PROT_EN_2_STA1),
0103         },
0104         .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
0105     },
0106     [MT8195_POWER_DOMAIN_AUDIO] = {
0107         .name = "audio",
0108         .sta_mask = BIT(8),
0109         .ctl_offs = 0x358,
0110         .pwr_sta_offs = 0x16c,
0111         .pwr_sta2nd_offs = 0x170,
0112         .sram_pdn_bits = GENMASK(8, 8),
0113         .sram_pdn_ack_bits = GENMASK(12, 12),
0114         .bp_infracfg = {
0115             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO,
0116                     MT8195_TOP_AXI_PROT_EN_2_SET,
0117                     MT8195_TOP_AXI_PROT_EN_2_CLR,
0118                     MT8195_TOP_AXI_PROT_EN_2_STA1),
0119         },
0120     },
0121     [MT8195_POWER_DOMAIN_MFG0] = {
0122         .name = "mfg0",
0123         .sta_mask = BIT(1),
0124         .ctl_offs = 0x300,
0125         .pwr_sta_offs = 0x174,
0126         .pwr_sta2nd_offs = 0x178,
0127         .sram_pdn_bits = GENMASK(8, 8),
0128         .sram_pdn_ack_bits = GENMASK(12, 12),
0129         .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
0130     },
0131     [MT8195_POWER_DOMAIN_MFG1] = {
0132         .name = "mfg1",
0133         .sta_mask = BIT(2),
0134         .ctl_offs = 0x304,
0135         .pwr_sta_offs = 0x174,
0136         .pwr_sta2nd_offs = 0x178,
0137         .sram_pdn_bits = GENMASK(8, 8),
0138         .sram_pdn_ack_bits = GENMASK(12, 12),
0139         .bp_infracfg = {
0140             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1,
0141                     MT8195_TOP_AXI_PROT_EN_SET,
0142                     MT8195_TOP_AXI_PROT_EN_CLR,
0143                     MT8195_TOP_AXI_PROT_EN_STA1),
0144             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1,
0145                     MT8195_TOP_AXI_PROT_EN_2_SET,
0146                     MT8195_TOP_AXI_PROT_EN_2_CLR,
0147                     MT8195_TOP_AXI_PROT_EN_2_STA1),
0148             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1,
0149                     MT8195_TOP_AXI_PROT_EN_1_SET,
0150                     MT8195_TOP_AXI_PROT_EN_1_CLR,
0151                     MT8195_TOP_AXI_PROT_EN_1_STA1),
0152             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND,
0153                     MT8195_TOP_AXI_PROT_EN_2_SET,
0154                     MT8195_TOP_AXI_PROT_EN_2_CLR,
0155                     MT8195_TOP_AXI_PROT_EN_2_STA1),
0156             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND,
0157                     MT8195_TOP_AXI_PROT_EN_SET,
0158                     MT8195_TOP_AXI_PROT_EN_CLR,
0159                     MT8195_TOP_AXI_PROT_EN_STA1),
0160             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1,
0161                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
0162                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
0163                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
0164         },
0165         .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
0166     },
0167     [MT8195_POWER_DOMAIN_MFG2] = {
0168         .name = "mfg2",
0169         .sta_mask = BIT(3),
0170         .ctl_offs = 0x308,
0171         .pwr_sta_offs = 0x174,
0172         .pwr_sta2nd_offs = 0x178,
0173         .sram_pdn_bits = GENMASK(8, 8),
0174         .sram_pdn_ack_bits = GENMASK(12, 12),
0175         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0176     },
0177     [MT8195_POWER_DOMAIN_MFG3] = {
0178         .name = "mfg3",
0179         .sta_mask = BIT(4),
0180         .ctl_offs = 0x30C,
0181         .pwr_sta_offs = 0x174,
0182         .pwr_sta2nd_offs = 0x178,
0183         .sram_pdn_bits = GENMASK(8, 8),
0184         .sram_pdn_ack_bits = GENMASK(12, 12),
0185         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0186     },
0187     [MT8195_POWER_DOMAIN_MFG4] = {
0188         .name = "mfg4",
0189         .sta_mask = BIT(5),
0190         .ctl_offs = 0x310,
0191         .pwr_sta_offs = 0x174,
0192         .pwr_sta2nd_offs = 0x178,
0193         .sram_pdn_bits = GENMASK(8, 8),
0194         .sram_pdn_ack_bits = GENMASK(12, 12),
0195         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0196     },
0197     [MT8195_POWER_DOMAIN_MFG5] = {
0198         .name = "mfg5",
0199         .sta_mask = BIT(6),
0200         .ctl_offs = 0x314,
0201         .pwr_sta_offs = 0x174,
0202         .pwr_sta2nd_offs = 0x178,
0203         .sram_pdn_bits = GENMASK(8, 8),
0204         .sram_pdn_ack_bits = GENMASK(12, 12),
0205         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0206     },
0207     [MT8195_POWER_DOMAIN_MFG6] = {
0208         .name = "mfg6",
0209         .sta_mask = BIT(7),
0210         .ctl_offs = 0x318,
0211         .pwr_sta_offs = 0x174,
0212         .pwr_sta2nd_offs = 0x178,
0213         .sram_pdn_bits = GENMASK(8, 8),
0214         .sram_pdn_ack_bits = GENMASK(12, 12),
0215         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0216     },
0217     [MT8195_POWER_DOMAIN_VPPSYS0] = {
0218         .name = "vppsys0",
0219         .sta_mask = BIT(11),
0220         .ctl_offs = 0x364,
0221         .pwr_sta_offs = 0x16c,
0222         .pwr_sta2nd_offs = 0x170,
0223         .sram_pdn_bits = GENMASK(8, 8),
0224         .sram_pdn_ack_bits = GENMASK(12, 12),
0225         .bp_infracfg = {
0226             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0,
0227                     MT8195_TOP_AXI_PROT_EN_SET,
0228                     MT8195_TOP_AXI_PROT_EN_CLR,
0229                     MT8195_TOP_AXI_PROT_EN_STA1),
0230             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0,
0231                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0232                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0233                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0234             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND,
0235                     MT8195_TOP_AXI_PROT_EN_SET,
0236                     MT8195_TOP_AXI_PROT_EN_CLR,
0237                     MT8195_TOP_AXI_PROT_EN_STA1),
0238             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND,
0239                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0240                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0241                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0242             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0,
0243                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
0244                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
0245                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
0246         },
0247     },
0248     [MT8195_POWER_DOMAIN_VDOSYS0] = {
0249         .name = "vdosys0",
0250         .sta_mask = BIT(13),
0251         .ctl_offs = 0x36C,
0252         .pwr_sta_offs = 0x16c,
0253         .pwr_sta2nd_offs = 0x170,
0254         .sram_pdn_bits = GENMASK(8, 8),
0255         .sram_pdn_ack_bits = GENMASK(12, 12),
0256         .bp_infracfg = {
0257             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0,
0258                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0259                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0260                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0261             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0,
0262                     MT8195_TOP_AXI_PROT_EN_SET,
0263                     MT8195_TOP_AXI_PROT_EN_CLR,
0264                     MT8195_TOP_AXI_PROT_EN_STA1),
0265             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0,
0266                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
0267                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
0268                     MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1),
0269         },
0270     },
0271     [MT8195_POWER_DOMAIN_VPPSYS1] = {
0272         .name = "vppsys1",
0273         .sta_mask = BIT(12),
0274         .ctl_offs = 0x368,
0275         .pwr_sta_offs = 0x16c,
0276         .pwr_sta2nd_offs = 0x170,
0277         .sram_pdn_bits = GENMASK(8, 8),
0278         .sram_pdn_ack_bits = GENMASK(12, 12),
0279         .bp_infracfg = {
0280             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1,
0281                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0282                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0283                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0284             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND,
0285                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0286                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0287                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0288             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1,
0289                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0290                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0291                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0292         },
0293     },
0294     [MT8195_POWER_DOMAIN_VDOSYS1] = {
0295         .name = "vdosys1",
0296         .sta_mask = BIT(14),
0297         .ctl_offs = 0x370,
0298         .pwr_sta_offs = 0x16c,
0299         .pwr_sta2nd_offs = 0x170,
0300         .sram_pdn_bits = GENMASK(8, 8),
0301         .sram_pdn_ack_bits = GENMASK(12, 12),
0302         .bp_infracfg = {
0303             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1,
0304                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0305                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0306                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0307             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND,
0308                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0309                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0310                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0311             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1,
0312                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0313                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0314                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0315         },
0316     },
0317     [MT8195_POWER_DOMAIN_DP_TX] = {
0318         .name = "dp_tx",
0319         .sta_mask = BIT(16),
0320         .ctl_offs = 0x378,
0321         .pwr_sta_offs = 0x16c,
0322         .pwr_sta2nd_offs = 0x170,
0323         .sram_pdn_bits = GENMASK(8, 8),
0324         .sram_pdn_ack_bits = GENMASK(12, 12),
0325         .bp_infracfg = {
0326             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX,
0327                     MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
0328                     MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
0329                     MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
0330         },
0331         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0332     },
0333     [MT8195_POWER_DOMAIN_EPD_TX] = {
0334         .name = "epd_tx",
0335         .sta_mask = BIT(17),
0336         .ctl_offs = 0x37C,
0337         .pwr_sta_offs = 0x16c,
0338         .pwr_sta2nd_offs = 0x170,
0339         .sram_pdn_bits = GENMASK(8, 8),
0340         .sram_pdn_ack_bits = GENMASK(12, 12),
0341         .bp_infracfg = {
0342             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX,
0343                     MT8195_TOP_AXI_PROT_EN_VDNR_1_SET,
0344                     MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR,
0345                     MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1),
0346         },
0347         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0348     },
0349     [MT8195_POWER_DOMAIN_HDMI_TX] = {
0350         .name = "hdmi_tx",
0351         .sta_mask = BIT(18),
0352         .ctl_offs = 0x380,
0353         .pwr_sta_offs = 0x16c,
0354         .pwr_sta2nd_offs = 0x170,
0355         .sram_pdn_bits = GENMASK(8, 8),
0356         .sram_pdn_ack_bits = GENMASK(12, 12),
0357         .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
0358     },
0359     [MT8195_POWER_DOMAIN_WPESYS] = {
0360         .name = "wpesys",
0361         .sta_mask = BIT(15),
0362         .ctl_offs = 0x374,
0363         .pwr_sta_offs = 0x16c,
0364         .pwr_sta2nd_offs = 0x170,
0365         .sram_pdn_bits = GENMASK(8, 8),
0366         .sram_pdn_ack_bits = GENMASK(12, 12),
0367         .bp_infracfg = {
0368             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS,
0369                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0370                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0371                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0372             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS,
0373                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0374                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0375                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0376             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND,
0377                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0378                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0379                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0380         },
0381     },
0382     [MT8195_POWER_DOMAIN_VDEC0] = {
0383         .name = "vdec0",
0384         .sta_mask = BIT(20),
0385         .ctl_offs = 0x388,
0386         .pwr_sta_offs = 0x16c,
0387         .pwr_sta2nd_offs = 0x170,
0388         .sram_pdn_bits = GENMASK(8, 8),
0389         .sram_pdn_ack_bits = GENMASK(12, 12),
0390         .bp_infracfg = {
0391             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0,
0392                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0393                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0394                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0395             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0,
0396                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0397                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0398                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0399             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND,
0400                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0401                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0402                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0403             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND,
0404                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0405                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0406                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0407         },
0408         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0409     },
0410     [MT8195_POWER_DOMAIN_VDEC1] = {
0411         .name = "vdec1",
0412         .sta_mask = BIT(21),
0413         .ctl_offs = 0x38C,
0414         .pwr_sta_offs = 0x16c,
0415         .pwr_sta2nd_offs = 0x170,
0416         .sram_pdn_bits = GENMASK(8, 8),
0417         .sram_pdn_ack_bits = GENMASK(12, 12),
0418         .bp_infracfg = {
0419             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1,
0420                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0421                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0422                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0423             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND,
0424                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0425                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0426                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0427         },
0428         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0429     },
0430     [MT8195_POWER_DOMAIN_VDEC2] = {
0431         .name = "vdec2",
0432         .sta_mask = BIT(22),
0433         .ctl_offs = 0x390,
0434         .pwr_sta_offs = 0x16c,
0435         .pwr_sta2nd_offs = 0x170,
0436         .sram_pdn_bits = GENMASK(8, 8),
0437         .sram_pdn_ack_bits = GENMASK(12, 12),
0438         .bp_infracfg = {
0439             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2,
0440                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0441                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0442                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0443             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND,
0444                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0445                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0446                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0447         },
0448         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0449     },
0450     [MT8195_POWER_DOMAIN_VENC] = {
0451         .name = "venc",
0452         .sta_mask = BIT(23),
0453         .ctl_offs = 0x394,
0454         .pwr_sta_offs = 0x16c,
0455         .pwr_sta2nd_offs = 0x170,
0456         .sram_pdn_bits = GENMASK(8, 8),
0457         .sram_pdn_ack_bits = GENMASK(12, 12),
0458         .bp_infracfg = {
0459             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC,
0460                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0461                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0462                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0463             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND,
0464                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0465                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0466                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0467             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC,
0468                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0469                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0470                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0471         },
0472         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0473     },
0474     [MT8195_POWER_DOMAIN_VENC_CORE1] = {
0475         .name = "venc_core1",
0476         .sta_mask = BIT(24),
0477         .ctl_offs = 0x398,
0478         .pwr_sta_offs = 0x16c,
0479         .pwr_sta2nd_offs = 0x170,
0480         .sram_pdn_bits = GENMASK(8, 8),
0481         .sram_pdn_ack_bits = GENMASK(12, 12),
0482         .bp_infracfg = {
0483             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1,
0484                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0485                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0486                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0487             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1,
0488                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0489                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0490                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0491         },
0492         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0493     },
0494     [MT8195_POWER_DOMAIN_IMG] = {
0495         .name = "img",
0496         .sta_mask = BIT(29),
0497         .ctl_offs = 0x3AC,
0498         .pwr_sta_offs = 0x16c,
0499         .pwr_sta2nd_offs = 0x170,
0500         .sram_pdn_bits = GENMASK(8, 8),
0501         .sram_pdn_ack_bits = GENMASK(12, 12),
0502         .bp_infracfg = {
0503             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG,
0504                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0505                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0506                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0507             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND,
0508                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0509                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0510                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0511         },
0512         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0513     },
0514     [MT8195_POWER_DOMAIN_DIP] = {
0515         .name = "dip",
0516         .sta_mask = BIT(30),
0517         .ctl_offs = 0x3B0,
0518         .pwr_sta_offs = 0x16c,
0519         .pwr_sta2nd_offs = 0x170,
0520         .sram_pdn_bits = GENMASK(8, 8),
0521         .sram_pdn_ack_bits = GENMASK(12, 12),
0522         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0523     },
0524     [MT8195_POWER_DOMAIN_IPE] = {
0525         .name = "ipe",
0526         .sta_mask = BIT(31),
0527         .ctl_offs = 0x3B4,
0528         .pwr_sta_offs = 0x16c,
0529         .pwr_sta2nd_offs = 0x170,
0530         .sram_pdn_bits = GENMASK(8, 8),
0531         .sram_pdn_ack_bits = GENMASK(12, 12),
0532         .bp_infracfg = {
0533             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE,
0534                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0535                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0536                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0537             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE,
0538                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0539                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0540                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0541         },
0542         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0543     },
0544     [MT8195_POWER_DOMAIN_CAM] = {
0545         .name = "cam",
0546         .sta_mask = BIT(25),
0547         .ctl_offs = 0x39C,
0548         .pwr_sta_offs = 0x16c,
0549         .pwr_sta2nd_offs = 0x170,
0550         .sram_pdn_bits = GENMASK(8, 8),
0551         .sram_pdn_ack_bits = GENMASK(12, 12),
0552         .bp_infracfg = {
0553             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM,
0554                     MT8195_TOP_AXI_PROT_EN_2_SET,
0555                     MT8195_TOP_AXI_PROT_EN_2_CLR,
0556                     MT8195_TOP_AXI_PROT_EN_2_STA1),
0557             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM,
0558                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0559                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0560                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0561             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM,
0562                     MT8195_TOP_AXI_PROT_EN_1_SET,
0563                     MT8195_TOP_AXI_PROT_EN_1_CLR,
0564                     MT8195_TOP_AXI_PROT_EN_1_STA1),
0565             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND,
0566                     MT8195_TOP_AXI_PROT_EN_MM_SET,
0567                     MT8195_TOP_AXI_PROT_EN_MM_CLR,
0568                     MT8195_TOP_AXI_PROT_EN_MM_STA1),
0569             BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM,
0570                     MT8195_TOP_AXI_PROT_EN_MM_2_SET,
0571                     MT8195_TOP_AXI_PROT_EN_MM_2_CLR,
0572                     MT8195_TOP_AXI_PROT_EN_MM_2_STA1),
0573         },
0574         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0575     },
0576     [MT8195_POWER_DOMAIN_CAM_RAWA] = {
0577         .name = "cam_rawa",
0578         .sta_mask = BIT(26),
0579         .ctl_offs = 0x3A0,
0580         .pwr_sta_offs = 0x16c,
0581         .pwr_sta2nd_offs = 0x170,
0582         .sram_pdn_bits = GENMASK(8, 8),
0583         .sram_pdn_ack_bits = GENMASK(12, 12),
0584         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0585     },
0586     [MT8195_POWER_DOMAIN_CAM_RAWB] = {
0587         .name = "cam_rawb",
0588         .sta_mask = BIT(27),
0589         .ctl_offs = 0x3A4,
0590         .pwr_sta_offs = 0x16c,
0591         .pwr_sta2nd_offs = 0x170,
0592         .sram_pdn_bits = GENMASK(8, 8),
0593         .sram_pdn_ack_bits = GENMASK(12, 12),
0594         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0595     },
0596     [MT8195_POWER_DOMAIN_CAM_MRAW] = {
0597         .name = "cam_mraw",
0598         .sta_mask = BIT(28),
0599         .ctl_offs = 0x3A8,
0600         .pwr_sta_offs = 0x16c,
0601         .pwr_sta2nd_offs = 0x170,
0602         .sram_pdn_bits = GENMASK(8, 8),
0603         .sram_pdn_ack_bits = GENMASK(12, 12),
0604         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0605     },
0606 };
0607 
0608 static const struct scpsys_soc_data mt8195_scpsys_data = {
0609     .domains_data = scpsys_domain_data_mt8195,
0610     .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195),
0611 };
0612 
0613 #endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */
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