0001
0002
0003 #ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
0004 #define __SOC_MEDIATEK_MT8195_MMSYS_H
0005
0006 #define MT8195_VDO0_OVL_MOUT_EN 0xf14
0007 #define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
0008 #define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
0009 #define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
0010 #define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
0011 #define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
0012 #define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
0013
0014 #define MT8195_VDO0_SEL_IN 0xf34
0015 #define MT8195_SEL_IN_VPP_MERGE_FROM_MASK GENMASK(1, 0)
0016 #define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
0017 #define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
0018 #define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
0019 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK GENMASK(4, 4)
0020 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
0021 #define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
0022 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK GENMASK(5, 5)
0023 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
0024 #define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
0025 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK GENMASK(8, 8)
0026 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
0027 #define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
0028 #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK GENMASK(9, 9)
0029 #define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
0030 #define MT8195_SEL_IN_DP_INTF0_FROM_MASK GENMASK(13, 12)
0031 #define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 0)
0032 #define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
0033 #define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
0034 #define MT8195_SEL_IN_DSI0_FROM_MASK GENMASK(16, 16)
0035 #define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
0036 #define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
0037 #define MT8195_SEL_IN_DSI1_FROM_MASK GENMASK(17, 17)
0038 #define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
0039 #define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
0040 #define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK GENMASK(20, 20)
0041 #define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
0042 #define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
0043 #define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK GENMASK(21, 21)
0044 #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
0045 #define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
0046 #define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK GENMASK(22, 22)
0047 #define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
0048
0049 #define MT8195_VDO0_SEL_OUT 0xf38
0050 #define MT8195_SOUT_DISP_DITHER0_TO_MASK BIT(0)
0051 #define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
0052 #define MT8195_SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
0053 #define MT8195_SOUT_DISP_DITHER1_TO_MASK GENMASK(2, 1)
0054 #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
0055 #define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
0056 #define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
0057 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK GENMASK(4, 4)
0058 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
0059 #define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
0060 #define MT8195_SOUT_VPP_MERGE_TO_MASK GENMASK(10, 8)
0061 #define MT8195_SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
0062 #define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
0063 #define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
0064 #define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
0065 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
0066 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK GENMASK(11, 11)
0067 #define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
0068 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK GENMASK(13, 12)
0069 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
0070 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
0071 #define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
0072 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK GENMASK(17, 16)
0073 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
0074 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
0075 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
0076 #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
0077
0078 static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
0079 {
0080 DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0081 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
0082 MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
0083 }, {
0084 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
0085 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
0086 MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
0087 }, {
0088 DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
0089 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
0090 MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
0091 }, {
0092 DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
0093 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
0094 MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
0095 }, {
0096 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
0097 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
0098 MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
0099 }, {
0100 DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
0101 MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
0102 MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
0103 }, {
0104 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
0105 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
0106 MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
0107 }, {
0108 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
0109 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
0110 MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
0111 }, {
0112 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
0113 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
0114 MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
0115 }, {
0116 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
0117 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
0118 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
0119 }, {
0120 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
0121 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
0122 MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
0123 }, {
0124 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
0125 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
0126 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
0127 }, {
0128 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
0129 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
0130 MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
0131 }, {
0132 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
0133 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
0134 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
0135 }, {
0136 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
0137 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
0138 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
0139 }, {
0140 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
0141 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
0142 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
0143 }, {
0144 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
0145 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
0146 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
0147 }, {
0148 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
0149 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
0150 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
0151 }, {
0152 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
0153 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
0154 MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
0155 }, {
0156 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
0157 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
0158 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
0159 }, {
0160 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
0161 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
0162 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
0163 }, {
0164 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
0165 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
0166 MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
0167 }, {
0168 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
0169 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
0170 MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
0171 }, {
0172 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
0173 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
0174 MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
0175 }, {
0176 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
0177 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
0178 MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
0179 }, {
0180 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
0181 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
0182 MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
0183 }, {
0184 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0185 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
0186 MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
0187 }, {
0188 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
0189 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
0190 MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
0191 }, {
0192 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
0193 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
0194 MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
0195 }, {
0196 DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
0197 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
0198 MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
0199 }, {
0200 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
0201 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
0202 MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
0203 }, {
0204 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
0205 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0206 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
0207 }, {
0208 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
0209 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0210 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
0211 }, {
0212 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
0213 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0214 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
0215 }, {
0216 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
0217 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0218 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
0219 }, {
0220 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
0221 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0222 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
0223 }, {
0224 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
0225 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0226 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
0227 }, {
0228 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
0229 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0230 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
0231 }, {
0232 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
0233 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0234 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
0235 }, {
0236 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
0237 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0238 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
0239 }, {
0240 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
0241 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
0242 MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
0243 }, {
0244 DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
0245 MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
0246 MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
0247 }, {
0248 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
0249 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
0250 MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
0251 }, {
0252 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0253 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
0254 MT8195_SOUT_DISP_DITHER0_TO_DSI0
0255 }, {
0256 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
0257 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0258 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
0259 }, {
0260 DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
0261 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0262 MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
0263 }, {
0264 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
0265 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0266 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
0267 }, {
0268 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
0269 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0270 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
0271 }, {
0272 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
0273 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0274 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
0275 }, {
0276 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
0277 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0278 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
0279 }, {
0280 DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
0281 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
0282 MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
0283 }, {
0284 DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
0285 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
0286 MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
0287 }, {
0288 DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
0289 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
0290 MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
0291 }, {
0292 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
0293 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0294 MT8195_SOUT_VPP_MERGE_TO_DSI1
0295 }, {
0296 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
0297 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0298 MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
0299 }, {
0300 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
0301 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0302 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
0303 }, {
0304 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
0305 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0306 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
0307 }, {
0308 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
0309 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0310 MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
0311 }, {
0312 DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
0313 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0314 MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
0315 }, {
0316 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
0317 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
0318 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
0319 }, {
0320 DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
0321 MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
0322 MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
0323 }, {
0324 DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
0325 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
0326 MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
0327 }, {
0328 DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
0329 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
0330 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
0331 }, {
0332 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
0333 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
0334 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
0335 }, {
0336 DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
0337 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
0338 MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
0339 }, {
0340 DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
0341 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
0342 MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
0343 }, {
0344 DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
0345 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
0346 MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
0347 }, {
0348 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
0349 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
0350 MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
0351 }, {
0352 DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
0353 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
0354 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
0355 }, {
0356 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
0357 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
0358 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
0359 }, {
0360 DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
0361 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
0362 MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
0363 }, {
0364 DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
0365 MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
0366 MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
0367 }
0368 };
0369
0370 #endif
