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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 
0003 #ifndef __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
0004 #define __SOC_MEDIATEK_MT8192_PM_DOMAINS_H
0005 
0006 #include "mtk-pm-domains.h"
0007 #include <dt-bindings/power/mt8192-power.h>
0008 
0009 /*
0010  * MT8192 power domain support
0011  */
0012 
0013 static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
0014     [MT8192_POWER_DOMAIN_AUDIO] = {
0015         .name = "audio",
0016         .sta_mask = BIT(21),
0017         .ctl_offs = 0x0354,
0018         .pwr_sta_offs = 0x016c,
0019         .pwr_sta2nd_offs = 0x0170,
0020         .sram_pdn_bits = GENMASK(8, 8),
0021         .sram_pdn_ack_bits = GENMASK(12, 12),
0022         .bp_infracfg = {
0023             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_AUDIO,
0024                     MT8192_TOP_AXI_PROT_EN_2_SET,
0025                     MT8192_TOP_AXI_PROT_EN_2_CLR,
0026                     MT8192_TOP_AXI_PROT_EN_2_STA1),
0027         },
0028     },
0029     [MT8192_POWER_DOMAIN_CONN] = {
0030         .name = "conn",
0031         .sta_mask = PWR_STATUS_CONN,
0032         .ctl_offs = 0x0304,
0033         .pwr_sta_offs = 0x016c,
0034         .pwr_sta2nd_offs = 0x0170,
0035         .sram_pdn_bits = 0,
0036         .sram_pdn_ack_bits = 0,
0037         .bp_infracfg = {
0038             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN,
0039                     MT8192_TOP_AXI_PROT_EN_SET,
0040                     MT8192_TOP_AXI_PROT_EN_CLR,
0041                     MT8192_TOP_AXI_PROT_EN_STA1),
0042             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_CONN_2ND,
0043                     MT8192_TOP_AXI_PROT_EN_SET,
0044                     MT8192_TOP_AXI_PROT_EN_CLR,
0045                     MT8192_TOP_AXI_PROT_EN_STA1),
0046             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CONN,
0047                     MT8192_TOP_AXI_PROT_EN_1_SET,
0048                     MT8192_TOP_AXI_PROT_EN_1_CLR,
0049                     MT8192_TOP_AXI_PROT_EN_1_STA1),
0050         },
0051         .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
0052     },
0053     [MT8192_POWER_DOMAIN_MFG0] = {
0054         .name = "mfg0",
0055         .sta_mask = BIT(2),
0056         .ctl_offs = 0x0308,
0057         .pwr_sta_offs = 0x016c,
0058         .pwr_sta2nd_offs = 0x0170,
0059         .sram_pdn_bits = GENMASK(8, 8),
0060         .sram_pdn_ack_bits = GENMASK(12, 12),
0061         .caps = MTK_SCPD_DOMAIN_SUPPLY,
0062     },
0063     [MT8192_POWER_DOMAIN_MFG1] = {
0064         .name = "mfg1",
0065         .sta_mask = BIT(3),
0066         .ctl_offs = 0x030c,
0067         .pwr_sta_offs = 0x016c,
0068         .pwr_sta2nd_offs = 0x0170,
0069         .sram_pdn_bits = GENMASK(8, 8),
0070         .sram_pdn_ack_bits = GENMASK(12, 12),
0071         .bp_infracfg = {
0072             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_MFG1,
0073                     MT8192_TOP_AXI_PROT_EN_1_SET,
0074                     MT8192_TOP_AXI_PROT_EN_1_CLR,
0075                     MT8192_TOP_AXI_PROT_EN_1_STA1),
0076             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1,
0077                     MT8192_TOP_AXI_PROT_EN_2_SET,
0078                     MT8192_TOP_AXI_PROT_EN_2_CLR,
0079                     MT8192_TOP_AXI_PROT_EN_2_STA1),
0080             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MFG1,
0081                     MT8192_TOP_AXI_PROT_EN_SET,
0082                     MT8192_TOP_AXI_PROT_EN_CLR,
0083                     MT8192_TOP_AXI_PROT_EN_STA1),
0084             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_MFG1_2ND,
0085                     MT8192_TOP_AXI_PROT_EN_2_SET,
0086                     MT8192_TOP_AXI_PROT_EN_2_CLR,
0087                     MT8192_TOP_AXI_PROT_EN_2_STA1),
0088         },
0089         .caps = MTK_SCPD_DOMAIN_SUPPLY,
0090     },
0091     [MT8192_POWER_DOMAIN_MFG2] = {
0092         .name = "mfg2",
0093         .sta_mask = BIT(4),
0094         .ctl_offs = 0x0310,
0095         .pwr_sta_offs = 0x016c,
0096         .pwr_sta2nd_offs = 0x0170,
0097         .sram_pdn_bits = GENMASK(8, 8),
0098         .sram_pdn_ack_bits = GENMASK(12, 12),
0099     },
0100     [MT8192_POWER_DOMAIN_MFG3] = {
0101         .name = "mfg3",
0102         .sta_mask = BIT(5),
0103         .ctl_offs = 0x0314,
0104         .pwr_sta_offs = 0x016c,
0105         .pwr_sta2nd_offs = 0x0170,
0106         .sram_pdn_bits = GENMASK(8, 8),
0107         .sram_pdn_ack_bits = GENMASK(12, 12),
0108     },
0109     [MT8192_POWER_DOMAIN_MFG4] = {
0110         .name = "mfg4",
0111         .sta_mask = BIT(6),
0112         .ctl_offs = 0x0318,
0113         .pwr_sta_offs = 0x016c,
0114         .pwr_sta2nd_offs = 0x0170,
0115         .sram_pdn_bits = GENMASK(8, 8),
0116         .sram_pdn_ack_bits = GENMASK(12, 12),
0117     },
0118     [MT8192_POWER_DOMAIN_MFG5] = {
0119         .name = "mfg5",
0120         .sta_mask = BIT(7),
0121         .ctl_offs = 0x031c,
0122         .pwr_sta_offs = 0x016c,
0123         .pwr_sta2nd_offs = 0x0170,
0124         .sram_pdn_bits = GENMASK(8, 8),
0125         .sram_pdn_ack_bits = GENMASK(12, 12),
0126     },
0127     [MT8192_POWER_DOMAIN_MFG6] = {
0128         .name = "mfg6",
0129         .sta_mask = BIT(8),
0130         .ctl_offs = 0x0320,
0131         .pwr_sta_offs = 0x016c,
0132         .pwr_sta2nd_offs = 0x0170,
0133         .sram_pdn_bits = GENMASK(8, 8),
0134         .sram_pdn_ack_bits = GENMASK(12, 12),
0135     },
0136     [MT8192_POWER_DOMAIN_DISP] = {
0137         .name = "disp",
0138         .sta_mask = BIT(20),
0139         .ctl_offs = 0x0350,
0140         .pwr_sta_offs = 0x016c,
0141         .pwr_sta2nd_offs = 0x0170,
0142         .sram_pdn_bits = GENMASK(8, 8),
0143         .sram_pdn_ack_bits = GENMASK(12, 12),
0144         .bp_infracfg = {
0145             BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_DISP,
0146                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0147                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0148                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0149             BUS_PROT_WR_IGN(MT8192_TOP_AXI_PROT_EN_MM_2_DISP,
0150                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
0151                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
0152                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
0153             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_DISP,
0154                     MT8192_TOP_AXI_PROT_EN_SET,
0155                     MT8192_TOP_AXI_PROT_EN_CLR,
0156                     MT8192_TOP_AXI_PROT_EN_STA1),
0157             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_DISP_2ND,
0158                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0159                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0160                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0161             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_DISP_2ND,
0162                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
0163                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
0164                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
0165         },
0166     },
0167     [MT8192_POWER_DOMAIN_IPE] = {
0168         .name = "ipe",
0169         .sta_mask = BIT(14),
0170         .ctl_offs = 0x0338,
0171         .pwr_sta_offs = 0x016c,
0172         .pwr_sta2nd_offs = 0x0170,
0173         .sram_pdn_bits = GENMASK(8, 8),
0174         .sram_pdn_ack_bits = GENMASK(12, 12),
0175         .bp_infracfg = {
0176             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE,
0177                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0178                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0179                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0180             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_IPE_2ND,
0181                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0182                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0183                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0184         },
0185     },
0186     [MT8192_POWER_DOMAIN_ISP] = {
0187         .name = "isp",
0188         .sta_mask = BIT(12),
0189         .ctl_offs = 0x0330,
0190         .pwr_sta_offs = 0x016c,
0191         .pwr_sta2nd_offs = 0x0170,
0192         .sram_pdn_bits = GENMASK(8, 8),
0193         .sram_pdn_ack_bits = GENMASK(12, 12),
0194         .bp_infracfg = {
0195             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP,
0196                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
0197                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
0198                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
0199             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_ISP_2ND,
0200                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
0201                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
0202                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
0203         },
0204     },
0205     [MT8192_POWER_DOMAIN_ISP2] = {
0206         .name = "isp2",
0207         .sta_mask = BIT(13),
0208         .ctl_offs = 0x0334,
0209         .pwr_sta_offs = 0x016c,
0210         .pwr_sta2nd_offs = 0x0170,
0211         .sram_pdn_bits = GENMASK(8, 8),
0212         .sram_pdn_ack_bits = GENMASK(12, 12),
0213         .bp_infracfg = {
0214             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2,
0215                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0216                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0217                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0218             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_ISP2_2ND,
0219                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0220                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0221                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0222         },
0223     },
0224     [MT8192_POWER_DOMAIN_MDP] = {
0225         .name = "mdp",
0226         .sta_mask = BIT(19),
0227         .ctl_offs = 0x034c,
0228         .pwr_sta_offs = 0x016c,
0229         .pwr_sta2nd_offs = 0x0170,
0230         .sram_pdn_bits = GENMASK(8, 8),
0231         .sram_pdn_ack_bits = GENMASK(12, 12),
0232         .bp_infracfg = {
0233             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP,
0234                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
0235                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
0236                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
0237             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND,
0238                     MT8192_TOP_AXI_PROT_EN_MM_2_SET,
0239                     MT8192_TOP_AXI_PROT_EN_MM_2_CLR,
0240                     MT8192_TOP_AXI_PROT_EN_MM_2_STA1),
0241         },
0242     },
0243     [MT8192_POWER_DOMAIN_VENC] = {
0244         .name = "venc",
0245         .sta_mask = BIT(17),
0246         .ctl_offs = 0x0344,
0247         .pwr_sta_offs = 0x016c,
0248         .pwr_sta2nd_offs = 0x0170,
0249         .sram_pdn_bits = GENMASK(8, 8),
0250         .sram_pdn_ack_bits = GENMASK(12, 12),
0251         .bp_infracfg = {
0252             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC,
0253                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0254                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0255                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0256             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VENC_2ND,
0257                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0258                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0259                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0260         },
0261     },
0262     [MT8192_POWER_DOMAIN_VDEC] = {
0263         .name = "vdec",
0264         .sta_mask = BIT(15),
0265         .ctl_offs = 0x033c,
0266         .pwr_sta_offs = 0x016c,
0267         .pwr_sta2nd_offs = 0x0170,
0268         .sram_pdn_bits = GENMASK(8, 8),
0269         .sram_pdn_ack_bits = GENMASK(12, 12),
0270         .bp_infracfg = {
0271             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC,
0272                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0273                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0274                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0275             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_VDEC_2ND,
0276                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0277                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0278                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0279         },
0280     },
0281     [MT8192_POWER_DOMAIN_VDEC2] = {
0282         .name = "vdec2",
0283         .sta_mask = BIT(16),
0284         .ctl_offs = 0x0340,
0285         .pwr_sta_offs = 0x016c,
0286         .pwr_sta2nd_offs = 0x0170,
0287         .sram_pdn_bits = GENMASK(8, 8),
0288         .sram_pdn_ack_bits = GENMASK(12, 12),
0289     },
0290     [MT8192_POWER_DOMAIN_CAM] = {
0291         .name = "cam",
0292         .sta_mask = BIT(23),
0293         .ctl_offs = 0x035c,
0294         .pwr_sta_offs = 0x016c,
0295         .pwr_sta2nd_offs = 0x0170,
0296         .sram_pdn_bits = GENMASK(8, 8),
0297         .sram_pdn_ack_bits = GENMASK(12, 12),
0298         .bp_infracfg = {
0299             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_2_CAM,
0300                     MT8192_TOP_AXI_PROT_EN_2_SET,
0301                     MT8192_TOP_AXI_PROT_EN_2_CLR,
0302                     MT8192_TOP_AXI_PROT_EN_2_STA1),
0303             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM,
0304                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0305                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0306                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0307             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_1_CAM,
0308                     MT8192_TOP_AXI_PROT_EN_1_SET,
0309                     MT8192_TOP_AXI_PROT_EN_1_CLR,
0310                     MT8192_TOP_AXI_PROT_EN_1_STA1),
0311             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_MM_CAM_2ND,
0312                     MT8192_TOP_AXI_PROT_EN_MM_SET,
0313                     MT8192_TOP_AXI_PROT_EN_MM_CLR,
0314                     MT8192_TOP_AXI_PROT_EN_MM_STA1),
0315             BUS_PROT_WR(MT8192_TOP_AXI_PROT_EN_VDNR_CAM,
0316                     MT8192_TOP_AXI_PROT_EN_VDNR_SET,
0317                     MT8192_TOP_AXI_PROT_EN_VDNR_CLR,
0318                     MT8192_TOP_AXI_PROT_EN_VDNR_STA1),
0319         },
0320     },
0321     [MT8192_POWER_DOMAIN_CAM_RAWA] = {
0322         .name = "cam_rawa",
0323         .sta_mask = BIT(24),
0324         .ctl_offs = 0x0360,
0325         .pwr_sta_offs = 0x016c,
0326         .pwr_sta2nd_offs = 0x0170,
0327         .sram_pdn_bits = GENMASK(8, 8),
0328         .sram_pdn_ack_bits = GENMASK(12, 12),
0329     },
0330     [MT8192_POWER_DOMAIN_CAM_RAWB] = {
0331         .name = "cam_rawb",
0332         .sta_mask = BIT(25),
0333         .ctl_offs = 0x0364,
0334         .pwr_sta_offs = 0x016c,
0335         .pwr_sta2nd_offs = 0x0170,
0336         .sram_pdn_bits = GENMASK(8, 8),
0337         .sram_pdn_ack_bits = GENMASK(12, 12),
0338     },
0339     [MT8192_POWER_DOMAIN_CAM_RAWC] = {
0340         .name = "cam_rawc",
0341         .sta_mask = BIT(26),
0342         .ctl_offs = 0x0368,
0343         .pwr_sta_offs = 0x016c,
0344         .pwr_sta2nd_offs = 0x0170,
0345         .sram_pdn_bits = GENMASK(8, 8),
0346         .sram_pdn_ack_bits = GENMASK(12, 12),
0347     },
0348 };
0349 
0350 static const struct scpsys_soc_data mt8192_scpsys_data = {
0351     .domains_data = scpsys_domain_data_mt8192,
0352     .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192),
0353 };
0354 
0355 #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */
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