soc/mediatek/mt8192-mmsys.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002
0003 #ifndef __SOC_MEDIATEK_MT8192_MMSYS_H
0004 #define __SOC_MEDIATEK_MT8192_MMSYS_H
0005
0006 #define MT8192_MMSYS_OVL_MOUT_EN        0xf04
0007 #define MT8192_DISP_OVL1_2L_MOUT_EN     0xf08
0008 #define MT8192_DISP_OVL0_2L_MOUT_EN     0xf18
0009 #define MT8192_DISP_OVL0_MOUT_EN        0xf1c
0010 #define MT8192_DISP_RDMA0_SEL_IN        0xf2c
0011 #define MT8192_DISP_RDMA0_SOUT_SEL      0xf30
0012 #define MT8192_DISP_CCORR0_SOUT_SEL     0xf34
0013 #define MT8192_DISP_AAL0_SEL_IN         0xf38
0014 #define MT8192_DISP_DITHER0_MOUT_EN     0xf3c
0015 #define MT8192_DISP_DSI0_SEL_IN         0xf40
0016 #define MT8192_DISP_OVL2_2L_MOUT_EN     0xf4c
0017
0018 #define MT8192_DISP_OVL0_GO_BLEND           BIT(0)
0019 #define MT8192_DITHER0_MOUT_IN_DSI0         BIT(0)
0020 #define MT8192_OVL0_MOUT_EN_DISP_RDMA0          BIT(0)
0021 #define MT8192_OVL2_2L_MOUT_EN_RDMA4            BIT(0)
0022 #define MT8192_DISP_OVL0_GO_BG              BIT(1)
0023 #define MT8192_DISP_OVL0_2L_GO_BLEND            BIT(2)
0024 #define MT8192_DISP_OVL0_2L_GO_BG           BIT(3)
0025 #define MT8192_OVL1_2L_MOUT_EN_RDMA1            BIT(4)
0026 #define MT8192_OVL0_MOUT_EN_OVL0_2L         BIT(4)
0027 #define MT8192_RDMA0_SEL_IN_OVL0_2L         0x3
0028 #define MT8192_RDMA0_SOUT_COLOR0            0x1
0029 #define MT8192_CCORR0_SOUT_AAL0             0x1
0030 #define MT8192_AAL0_SEL_IN_CCORR0           0x1
0031 #define MT8192_DSI0_SEL_IN_DITHER0          0x1
0032
0033 static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
0034     {
0035         DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
0036         MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
0037         MT8192_OVL0_MOUT_EN_DISP_RDMA0
0038     }, {
0039         DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4,
0040         MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
0041         MT8192_OVL2_2L_MOUT_EN_RDMA4
0042     }, {
0043         DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0044         MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
0045         MT8192_DITHER0_MOUT_IN_DSI0
0046     }, {
0047         DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
0048         MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
0049         MT8192_RDMA0_SEL_IN_OVL0_2L
0050     }, {
0051         DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
0052         MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
0053         MT8192_AAL0_SEL_IN_CCORR0
0054     }, {
0055         DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0056         MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
0057         MT8192_DSI0_SEL_IN_DITHER0
0058     }, {
0059         DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
0060         MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
0061         MT8192_RDMA0_SOUT_COLOR0
0062     }, {
0063         DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0,
0064         MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
0065         MT8192_CCORR0_SOUT_AAL0
0066     }, {
0067         DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
0068         MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
0069         MT8192_DISP_OVL0_GO_BG
0070     }, {
0071         DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
0072         MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
0073         MT8192_DISP_OVL0_2L_GO_BLEND
0074     }
0075 };
0076
0077 #endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */