soc/mediatek/mt8186-mmsys.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002
0003 #ifndef __SOC_MEDIATEK_MT8186_MMSYS_H
0004 #define __SOC_MEDIATEK_MT8186_MMSYS_H
0005
0006 #define MT8186_MMSYS_OVL_CON            0xF04
0007 #define MT8186_MMSYS_OVL0_CON_MASK          0x3
0008 #define MT8186_MMSYS_OVL0_2L_CON_MASK           0xC
0009 #define MT8186_OVL0_GO_BLEND                BIT(0)
0010 #define MT8186_OVL0_GO_BG               BIT(1)
0011 #define MT8186_OVL0_2L_GO_BLEND             BIT(2)
0012 #define MT8186_OVL0_2L_GO_BG                BIT(3)
0013 #define MT8186_DISP_RDMA0_SOUT_SEL      0xF0C
0014 #define MT8186_RDMA0_SOUT_SEL_MASK          0xF
0015 #define MT8186_RDMA0_SOUT_TO_DSI0           (0)
0016 #define MT8186_RDMA0_SOUT_TO_COLOR0         (1)
0017 #define MT8186_RDMA0_SOUT_TO_DPI0           (2)
0018 #define MT8186_DISP_OVL0_2L_MOUT_EN     0xF14
0019 #define MT8186_OVL0_2L_MOUT_EN_MASK         0xF
0020 #define MT8186_OVL0_2L_MOUT_TO_RDMA0            BIT(0)
0021 #define MT8186_OVL0_2L_MOUT_TO_RDMA1            BIT(3)
0022 #define MT8186_DISP_OVL0_MOUT_EN        0xF18
0023 #define MT8186_OVL0_MOUT_EN_MASK            0xF
0024 #define MT8186_OVL0_MOUT_TO_RDMA0           BIT(0)
0025 #define MT8186_OVL0_MOUT_TO_RDMA1           BIT(3)
0026 #define MT8186_DISP_DITHER0_MOUT_EN     0xF20
0027 #define MT8186_DITHER0_MOUT_EN_MASK         0xF
0028 #define MT8186_DITHER0_MOUT_TO_DSI0         BIT(0)
0029 #define MT8186_DITHER0_MOUT_TO_RDMA1            BIT(2)
0030 #define MT8186_DITHER0_MOUT_TO_DPI0         BIT(3)
0031 #define MT8186_DISP_RDMA0_SEL_IN        0xF28
0032 #define MT8186_RDMA0_SEL_IN_MASK            0xF
0033 #define MT8186_RDMA0_FROM_OVL0              0
0034 #define MT8186_RDMA0_FROM_OVL0_2L           2
0035 #define MT8186_DISP_DSI0_SEL_IN         0xF30
0036 #define MT8186_DSI0_SEL_IN_MASK             0xF
0037 #define MT8186_DSI0_FROM_RDMA0              0
0038 #define MT8186_DSI0_FROM_DITHER0            1
0039 #define MT8186_DSI0_FROM_RDMA1              2
0040 #define MT8186_DISP_RDMA1_MOUT_EN       0xF3C
0041 #define MT8186_RDMA1_MOUT_EN_MASK           0xF
0042 #define MT8186_RDMA1_MOUT_TO_DPI0_SEL           BIT(0)
0043 #define MT8186_RDMA1_MOUT_TO_DSI0_SEL           BIT(2)
0044 #define MT8186_DISP_RDMA1_SEL_IN        0xF40
0045 #define MT8186_RDMA1_SEL_IN_MASK            0xF
0046 #define MT8186_RDMA1_FROM_OVL0              0
0047 #define MT8186_RDMA1_FROM_OVL0_2L           2
0048 #define MT8186_RDMA1_FROM_DITHER0           3
0049 #define MT8186_DISP_DPI0_SEL_IN         0xF44
0050 #define MT8186_DPI0_SEL_IN_MASK             0xF
0051 #define MT8186_DPI0_FROM_RDMA1              0
0052 #define MT8186_DPI0_FROM_DITHER0            1
0053 #define MT8186_DPI0_FROM_RDMA0              2
0054
0055 #define MT8186_MMSYS_SW0_RST_B              0x160
0056
0057 static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
0058     {
0059         DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0060         MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
0061         MT8186_OVL0_MOUT_TO_RDMA0
0062     },
0063     {
0064         DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0065         MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
0066         MT8186_RDMA0_FROM_OVL0
0067     },
0068     {
0069         DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
0070         MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
0071         MT8186_OVL0_GO_BLEND
0072     },
0073     {
0074         DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
0075         MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
0076         MT8186_RDMA0_SOUT_TO_COLOR0
0077     },
0078     {
0079         DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0080         MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
0081         MT8186_DITHER0_MOUT_TO_DSI0,
0082     },
0083     {
0084         DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0085         MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
0086         MT8186_DSI0_FROM_DITHER0
0087     },
0088     {
0089         DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
0090         MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
0091         MT8186_OVL0_2L_MOUT_TO_RDMA1
0092     },
0093     {
0094         DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
0095         MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
0096         MT8186_RDMA1_FROM_OVL0_2L
0097     },
0098     {
0099         DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA1,
0100         MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
0101         MT8186_OVL0_2L_GO_BLEND
0102     },
0103     {
0104         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0105         MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
0106         MT8186_RDMA1_MOUT_TO_DPI0_SEL
0107     },
0108     {
0109         DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0110         MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
0111         MT8186_DPI0_FROM_RDMA1
0112     },
0113 };
0114
0115 #endif /* __SOC_MEDIATEK_MT8186_MMSYS_H */