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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 
0003 #ifndef __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
0004 #define __SOC_MEDIATEK_MT8183_PM_DOMAINS_H
0005 
0006 #include "mtk-pm-domains.h"
0007 #include <dt-bindings/power/mt8183-power.h>
0008 
0009 /*
0010  * MT8183 power domain support
0011  */
0012 
0013 static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = {
0014     [MT8183_POWER_DOMAIN_AUDIO] = {
0015         .name = "audio",
0016         .sta_mask = PWR_STATUS_AUDIO,
0017         .ctl_offs = 0x0314,
0018         .pwr_sta_offs = 0x0180,
0019         .pwr_sta2nd_offs = 0x0184,
0020         .sram_pdn_bits = GENMASK(11, 8),
0021         .sram_pdn_ack_bits = GENMASK(15, 12),
0022     },
0023     [MT8183_POWER_DOMAIN_CONN] = {
0024         .name = "conn",
0025         .sta_mask = PWR_STATUS_CONN,
0026         .ctl_offs = 0x032c,
0027         .pwr_sta_offs = 0x0180,
0028         .pwr_sta2nd_offs = 0x0184,
0029         .sram_pdn_bits = 0,
0030         .sram_pdn_ack_bits = 0,
0031         .bp_infracfg = {
0032             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CONN, MT8183_TOP_AXI_PROT_EN_SET,
0033                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
0034         },
0035     },
0036     [MT8183_POWER_DOMAIN_MFG_ASYNC] = {
0037         .name = "mfg_async",
0038         .sta_mask = PWR_STATUS_MFG_ASYNC,
0039         .ctl_offs = 0x0334,
0040         .pwr_sta_offs = 0x0180,
0041         .pwr_sta2nd_offs = 0x0184,
0042         .sram_pdn_bits = 0,
0043         .sram_pdn_ack_bits = 0,
0044         .caps = MTK_SCPD_DOMAIN_SUPPLY,
0045     },
0046     [MT8183_POWER_DOMAIN_MFG] = {
0047         .name = "mfg",
0048         .sta_mask = PWR_STATUS_MFG,
0049         .ctl_offs = 0x0338,
0050         .pwr_sta_offs = 0x0180,
0051         .pwr_sta2nd_offs = 0x0184,
0052         .sram_pdn_bits = GENMASK(8, 8),
0053         .sram_pdn_ack_bits = GENMASK(12, 12),
0054         .caps = MTK_SCPD_DOMAIN_SUPPLY,
0055     },
0056     [MT8183_POWER_DOMAIN_MFG_CORE0] = {
0057         .name = "mfg_core0",
0058         .sta_mask = BIT(7),
0059         .ctl_offs = 0x034c,
0060         .pwr_sta_offs = 0x0180,
0061         .pwr_sta2nd_offs = 0x0184,
0062         .sram_pdn_bits = GENMASK(8, 8),
0063         .sram_pdn_ack_bits = GENMASK(12, 12),
0064     },
0065     [MT8183_POWER_DOMAIN_MFG_CORE1] = {
0066         .name = "mfg_core1",
0067         .sta_mask = BIT(20),
0068         .ctl_offs = 0x0310,
0069         .pwr_sta_offs = 0x0180,
0070         .pwr_sta2nd_offs = 0x0184,
0071         .sram_pdn_bits = GENMASK(8, 8),
0072         .sram_pdn_ack_bits = GENMASK(12, 12),
0073     },
0074     [MT8183_POWER_DOMAIN_MFG_2D] = {
0075         .name = "mfg_2d",
0076         .sta_mask = PWR_STATUS_MFG_2D,
0077         .ctl_offs = 0x0348,
0078         .pwr_sta_offs = 0x0180,
0079         .pwr_sta2nd_offs = 0x0184,
0080         .sram_pdn_bits = GENMASK(8, 8),
0081         .sram_pdn_ack_bits = GENMASK(12, 12),
0082         .bp_infracfg = {
0083             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_MFG, MT8183_TOP_AXI_PROT_EN_1_SET,
0084                     MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
0085             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MFG, MT8183_TOP_AXI_PROT_EN_SET,
0086                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
0087         },
0088     },
0089     [MT8183_POWER_DOMAIN_DISP] = {
0090         .name = "disp",
0091         .sta_mask = PWR_STATUS_DISP,
0092         .ctl_offs = 0x030c,
0093         .pwr_sta_offs = 0x0180,
0094         .pwr_sta2nd_offs = 0x0184,
0095         .sram_pdn_bits = GENMASK(8, 8),
0096         .sram_pdn_ack_bits = GENMASK(12, 12),
0097         .bp_infracfg = {
0098             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_1_DISP, MT8183_TOP_AXI_PROT_EN_1_SET,
0099                     MT8183_TOP_AXI_PROT_EN_1_CLR, MT8183_TOP_AXI_PROT_EN_STA1_1),
0100             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_DISP, MT8183_TOP_AXI_PROT_EN_SET,
0101                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
0102         },
0103         .bp_smi = {
0104             BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_DISP,
0105                     MT8183_SMI_COMMON_CLAMP_EN_SET,
0106                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
0107                     MT8183_SMI_COMMON_CLAMP_EN),
0108         },
0109     },
0110     [MT8183_POWER_DOMAIN_CAM] = {
0111         .name = "cam",
0112         .sta_mask = BIT(25),
0113         .ctl_offs = 0x0344,
0114         .pwr_sta_offs = 0x0180,
0115         .pwr_sta2nd_offs = 0x0184,
0116         .sram_pdn_bits = GENMASK(9, 8),
0117         .sram_pdn_ack_bits = GENMASK(13, 12),
0118         .bp_infracfg = {
0119             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_CAM, MT8183_TOP_AXI_PROT_EN_MM_SET,
0120                     MT8183_TOP_AXI_PROT_EN_MM_CLR, MT8183_TOP_AXI_PROT_EN_MM_STA1),
0121             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_CAM, MT8183_TOP_AXI_PROT_EN_SET,
0122                     MT8183_TOP_AXI_PROT_EN_CLR, MT8183_TOP_AXI_PROT_EN_STA1),
0123             BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_CAM_2ND,
0124                     MT8183_TOP_AXI_PROT_EN_MM_SET,
0125                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
0126                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
0127         },
0128         .bp_smi = {
0129             BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_CAM,
0130                     MT8183_SMI_COMMON_CLAMP_EN_SET,
0131                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
0132                     MT8183_SMI_COMMON_CLAMP_EN),
0133         },
0134     },
0135     [MT8183_POWER_DOMAIN_ISP] = {
0136         .name = "isp",
0137         .sta_mask = PWR_STATUS_ISP,
0138         .ctl_offs = 0x0308,
0139         .pwr_sta_offs = 0x0180,
0140         .pwr_sta2nd_offs = 0x0184,
0141         .sram_pdn_bits = GENMASK(9, 8),
0142         .sram_pdn_ack_bits = GENMASK(13, 12),
0143         .bp_infracfg = {
0144             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_ISP,
0145                     MT8183_TOP_AXI_PROT_EN_MM_SET,
0146                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
0147                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
0148             BUS_PROT_WR_IGN(MT8183_TOP_AXI_PROT_EN_MM_ISP_2ND,
0149                     MT8183_TOP_AXI_PROT_EN_MM_SET,
0150                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
0151                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
0152         },
0153         .bp_smi = {
0154             BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_ISP,
0155                     MT8183_SMI_COMMON_CLAMP_EN_SET,
0156                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
0157                     MT8183_SMI_COMMON_CLAMP_EN),
0158         },
0159     },
0160     [MT8183_POWER_DOMAIN_VDEC] = {
0161         .name = "vdec",
0162         .sta_mask = BIT(31),
0163         .ctl_offs = 0x0300,
0164         .pwr_sta_offs = 0x0180,
0165         .pwr_sta2nd_offs = 0x0184,
0166         .sram_pdn_bits = GENMASK(8, 8),
0167         .sram_pdn_ack_bits = GENMASK(12, 12),
0168         .bp_smi = {
0169             BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VDEC,
0170                     MT8183_SMI_COMMON_CLAMP_EN_SET,
0171                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
0172                     MT8183_SMI_COMMON_CLAMP_EN),
0173         },
0174     },
0175     [MT8183_POWER_DOMAIN_VENC] = {
0176         .name = "venc",
0177         .sta_mask = PWR_STATUS_VENC,
0178         .ctl_offs = 0x0304,
0179         .pwr_sta_offs = 0x0180,
0180         .pwr_sta2nd_offs = 0x0184,
0181         .sram_pdn_bits = GENMASK(11, 8),
0182         .sram_pdn_ack_bits = GENMASK(15, 12),
0183         .bp_smi = {
0184             BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VENC,
0185                     MT8183_SMI_COMMON_CLAMP_EN_SET,
0186                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
0187                     MT8183_SMI_COMMON_CLAMP_EN),
0188         },
0189     },
0190     [MT8183_POWER_DOMAIN_VPU_TOP] = {
0191         .name = "vpu_top",
0192         .sta_mask = BIT(26),
0193         .ctl_offs = 0x0324,
0194         .pwr_sta_offs = 0x0180,
0195         .pwr_sta2nd_offs = 0x0184,
0196         .sram_pdn_bits = GENMASK(8, 8),
0197         .sram_pdn_ack_bits = GENMASK(12, 12),
0198         .bp_infracfg = {
0199             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP,
0200                     MT8183_TOP_AXI_PROT_EN_MM_SET,
0201                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
0202                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
0203             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_VPU_TOP,
0204                     MT8183_TOP_AXI_PROT_EN_SET,
0205                     MT8183_TOP_AXI_PROT_EN_CLR,
0206                     MT8183_TOP_AXI_PROT_EN_STA1),
0207             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MM_VPU_TOP_2ND,
0208                     MT8183_TOP_AXI_PROT_EN_MM_SET,
0209                     MT8183_TOP_AXI_PROT_EN_MM_CLR,
0210                     MT8183_TOP_AXI_PROT_EN_MM_STA1),
0211         },
0212         .bp_smi = {
0213             BUS_PROT_WR(MT8183_SMI_COMMON_SMI_CLAMP_VPU_TOP,
0214                     MT8183_SMI_COMMON_CLAMP_EN_SET,
0215                     MT8183_SMI_COMMON_CLAMP_EN_CLR,
0216                     MT8183_SMI_COMMON_CLAMP_EN),
0217         },
0218     },
0219     [MT8183_POWER_DOMAIN_VPU_CORE0] = {
0220         .name = "vpu_core0",
0221         .sta_mask = BIT(27),
0222         .ctl_offs = 0x33c,
0223         .pwr_sta_offs = 0x0180,
0224         .pwr_sta2nd_offs = 0x0184,
0225         .sram_pdn_bits = GENMASK(11, 8),
0226         .sram_pdn_ack_bits = GENMASK(13, 12),
0227         .bp_infracfg = {
0228             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0,
0229                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
0230                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
0231                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
0232             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND,
0233                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
0234                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
0235                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
0236         },
0237         .caps = MTK_SCPD_SRAM_ISO,
0238     },
0239     [MT8183_POWER_DOMAIN_VPU_CORE1] = {
0240         .name = "vpu_core1",
0241         .sta_mask = BIT(28),
0242         .ctl_offs = 0x0340,
0243         .pwr_sta_offs = 0x0180,
0244         .pwr_sta2nd_offs = 0x0184,
0245         .sram_pdn_bits = GENMASK(11, 8),
0246         .sram_pdn_ack_bits = GENMASK(13, 12),
0247         .bp_infracfg = {
0248             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1,
0249                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
0250                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
0251                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
0252             BUS_PROT_WR(MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE1_2ND,
0253                     MT8183_TOP_AXI_PROT_EN_MCU_SET,
0254                     MT8183_TOP_AXI_PROT_EN_MCU_CLR,
0255                     MT8183_TOP_AXI_PROT_EN_MCU_STA1),
0256         },
0257         .caps = MTK_SCPD_SRAM_ISO,
0258     },
0259 };
0260 
0261 static const struct scpsys_soc_data mt8183_scpsys_data = {
0262     .domains_data = scpsys_domain_data_mt8183,
0263     .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183),
0264 };
0265 
0266 #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */
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