0001
0002
0003 #ifndef __SOC_MEDIATEK_MT8183_MMSYS_H
0004 #define __SOC_MEDIATEK_MT8183_MMSYS_H
0005
0006 #define MT8183_DISP_OVL0_MOUT_EN 0xf00
0007 #define MT8183_DISP_OVL0_2L_MOUT_EN 0xf04
0008 #define MT8183_DISP_OVL1_2L_MOUT_EN 0xf08
0009 #define MT8183_DISP_DITHER0_MOUT_EN 0xf0c
0010 #define MT8183_DISP_PATH0_SEL_IN 0xf24
0011 #define MT8183_DISP_DSI0_SEL_IN 0xf2c
0012 #define MT8183_DISP_DPI0_SEL_IN 0xf30
0013 #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
0014 #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
0015
0016 #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
0017 #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
0018 #define MT8183_OVL1_2L_MOUT_EN_RDMA1 BIT(4)
0019 #define MT8183_DITHER0_MOUT_IN_DSI0 BIT(0)
0020 #define MT8183_DISP_PATH0_SEL_IN_OVL0_2L 0x1
0021 #define MT8183_DSI0_SEL_IN_RDMA0 0x1
0022 #define MT8183_DSI0_SEL_IN_RDMA1 0x3
0023 #define MT8183_DPI0_SEL_IN_RDMA0 0x1
0024 #define MT8183_DPI0_SEL_IN_RDMA1 0x2
0025 #define MT8183_RDMA0_SOUT_COLOR0 0x1
0026 #define MT8183_RDMA1_SOUT_DSI0 0x1
0027
0028 #define MT8183_MMSYS_SW0_RST_B 0x140
0029
0030 static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
0031 {
0032 DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0,
0033 MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
0034 MT8183_OVL0_MOUT_EN_OVL0_2L
0035 }, {
0036 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
0037 MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
0038 MT8183_OVL0_2L_MOUT_EN_DISP_PATH0
0039 }, {
0040 DDP_COMPONENT_OVL_2L1, DDP_COMPONENT_RDMA1,
0041 MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
0042 MT8183_OVL1_2L_MOUT_EN_RDMA1
0043 }, {
0044 DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
0045 MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
0046 MT8183_DITHER0_MOUT_IN_DSI0
0047 }, {
0048 DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0,
0049 MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
0050 MT8183_DISP_PATH0_SEL_IN_OVL0_2L
0051 }, {
0052 DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
0053 MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
0054 MT8183_DPI0_SEL_IN_RDMA1
0055 }, {
0056 DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0,
0057 MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
0058 MT8183_RDMA0_SOUT_COLOR0
0059 }
0060 };
0061
0062 #endif
0063