soc/mediatek/mt8167-pm-domains.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002
0003 #ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
0004 #define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
0005
0006 #include "mtk-pm-domains.h"
0007 #include <dt-bindings/power/mt8167-power.h>
0008
0009 #define MT8167_PWR_STATUS_MFG_2D    BIT(24)
0010 #define MT8167_PWR_STATUS_MFG_ASYNC BIT(25)
0011
0012 /*
0013  * MT8167 power domain support
0014  */
0015
0016 static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
0017     [MT8167_POWER_DOMAIN_MM] = {
0018         .name = "mm",
0019         .sta_mask = PWR_STATUS_DISP,
0020         .ctl_offs = SPM_DIS_PWR_CON,
0021         .pwr_sta_offs = SPM_PWR_STATUS,
0022         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0023         .sram_pdn_bits = GENMASK(11, 8),
0024         .sram_pdn_ack_bits = GENMASK(12, 12),
0025         .bp_infracfg = {
0026             BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
0027                            MT8167_TOP_AXI_PROT_EN_MCU_MM),
0028         },
0029         .caps = MTK_SCPD_ACTIVE_WAKEUP,
0030     },
0031     [MT8167_POWER_DOMAIN_VDEC] = {
0032         .name = "vdec",
0033         .sta_mask = PWR_STATUS_VDEC,
0034         .ctl_offs = SPM_VDE_PWR_CON,
0035         .pwr_sta_offs = SPM_PWR_STATUS,
0036         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0037         .sram_pdn_bits = GENMASK(8, 8),
0038         .sram_pdn_ack_bits = GENMASK(12, 12),
0039         .caps = MTK_SCPD_ACTIVE_WAKEUP,
0040     },
0041     [MT8167_POWER_DOMAIN_ISP] = {
0042         .name = "isp",
0043         .sta_mask = PWR_STATUS_ISP,
0044         .ctl_offs = SPM_ISP_PWR_CON,
0045         .pwr_sta_offs = SPM_PWR_STATUS,
0046         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0047         .sram_pdn_bits = GENMASK(11, 8),
0048         .sram_pdn_ack_bits = GENMASK(13, 12),
0049         .caps = MTK_SCPD_ACTIVE_WAKEUP,
0050     },
0051     [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
0052         .name = "mfg_async",
0053         .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
0054         .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
0055         .pwr_sta_offs = SPM_PWR_STATUS,
0056         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0057         .sram_pdn_bits = 0,
0058         .sram_pdn_ack_bits = 0,
0059         .bp_infracfg = {
0060             BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
0061                            MT8167_TOP_AXI_PROT_EN_MFG_EMI),
0062         },
0063     },
0064     [MT8167_POWER_DOMAIN_MFG_2D] = {
0065         .name = "mfg_2d",
0066         .sta_mask = MT8167_PWR_STATUS_MFG_2D,
0067         .ctl_offs = SPM_MFG_2D_PWR_CON,
0068         .pwr_sta_offs = SPM_PWR_STATUS,
0069         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0070         .sram_pdn_bits = GENMASK(11, 8),
0071         .sram_pdn_ack_bits = GENMASK(15, 12),
0072     },
0073     [MT8167_POWER_DOMAIN_MFG] = {
0074         .name = "mfg",
0075         .sta_mask = PWR_STATUS_MFG,
0076         .ctl_offs = SPM_MFG_PWR_CON,
0077         .pwr_sta_offs = SPM_PWR_STATUS,
0078         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0079         .sram_pdn_bits = GENMASK(11, 8),
0080         .sram_pdn_ack_bits = GENMASK(15, 12),
0081     },
0082     [MT8167_POWER_DOMAIN_CONN] = {
0083         .name = "conn",
0084         .sta_mask = PWR_STATUS_CONN,
0085         .ctl_offs = SPM_CONN_PWR_CON,
0086         .pwr_sta_offs = SPM_PWR_STATUS,
0087         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0088         .sram_pdn_bits = GENMASK(8, 8),
0089         .sram_pdn_ack_bits = 0,
0090         .caps = MTK_SCPD_ACTIVE_WAKEUP,
0091         .bp_infracfg = {
0092             BUS_PROT_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
0093                            MT8167_TOP_AXI_PROT_EN_CONN_MCU |
0094                            MT8167_TOP_AXI_PROT_EN_MCU_CONN),
0095         },
0096     },
0097 };
0098
0099 static const struct scpsys_soc_data mt8167_scpsys_data = {
0100     .domains_data = scpsys_domain_data_mt8167,
0101     .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
0102 };
0103
0104 #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
0105