soc/mediatek/mt6795-pm-domains.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002
0003 #ifndef __SOC_MEDIATEK_MT6795_PM_DOMAINS_H
0004 #define __SOC_MEDIATEK_MT6795_PM_DOMAINS_H
0005
0006 #include "mtk-pm-domains.h"
0007 #include <dt-bindings/power/mt6795-power.h>
0008
0009 /*
0010  * MT6795 power domain support
0011  */
0012
0013 static const struct scpsys_domain_data scpsys_domain_data_mt6795[] = {
0014     [MT6795_POWER_DOMAIN_VDEC] = {
0015         .name = "vdec",
0016         .sta_mask = PWR_STATUS_VDEC,
0017         .ctl_offs = SPM_VDE_PWR_CON,
0018         .pwr_sta_offs = SPM_PWR_STATUS,
0019         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0020         .sram_pdn_bits = GENMASK(11, 8),
0021         .sram_pdn_ack_bits = GENMASK(12, 12),
0022     },
0023     [MT6795_POWER_DOMAIN_VENC] = {
0024         .name = "venc",
0025         .sta_mask = PWR_STATUS_VENC,
0026         .ctl_offs = SPM_VEN_PWR_CON,
0027         .pwr_sta_offs = SPM_PWR_STATUS,
0028         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0029         .sram_pdn_bits = GENMASK(11, 8),
0030         .sram_pdn_ack_bits = GENMASK(15, 12),
0031     },
0032     [MT6795_POWER_DOMAIN_ISP] = {
0033         .name = "isp",
0034         .sta_mask = PWR_STATUS_ISP,
0035         .ctl_offs = SPM_ISP_PWR_CON,
0036         .pwr_sta_offs = SPM_PWR_STATUS,
0037         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0038         .sram_pdn_bits = GENMASK(11, 8),
0039         .sram_pdn_ack_bits = GENMASK(13, 12),
0040     },
0041     [MT6795_POWER_DOMAIN_MM] = {
0042         .name = "mm",
0043         .sta_mask = PWR_STATUS_DISP,
0044         .ctl_offs = SPM_DIS_PWR_CON,
0045         .pwr_sta_offs = SPM_PWR_STATUS,
0046         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0047         .sram_pdn_bits = GENMASK(11, 8),
0048         .sram_pdn_ack_bits = GENMASK(12, 12),
0049         .bp_infracfg = {
0050             BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
0051                            MT8173_TOP_AXI_PROT_EN_MM_M1),
0052         },
0053     },
0054     [MT6795_POWER_DOMAIN_MJC] = {
0055         .name = "mjc",
0056         .sta_mask = BIT(20),
0057         .ctl_offs = 0x298,
0058         .pwr_sta_offs = SPM_PWR_STATUS,
0059         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0060         .sram_pdn_bits = GENMASK(11, 8),
0061         .sram_pdn_ack_bits = GENMASK(15, 12),
0062     },
0063     [MT6795_POWER_DOMAIN_AUDIO] = {
0064         .name = "audio",
0065         .sta_mask = PWR_STATUS_AUDIO,
0066         .ctl_offs = SPM_AUDIO_PWR_CON,
0067         .pwr_sta_offs = SPM_PWR_STATUS,
0068         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0069         .sram_pdn_bits = GENMASK(11, 8),
0070         .sram_pdn_ack_bits = GENMASK(15, 12),
0071     },
0072     [MT6795_POWER_DOMAIN_MFG_ASYNC] = {
0073         .name = "mfg_async",
0074         .sta_mask = PWR_STATUS_MFG_ASYNC,
0075         .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
0076         .pwr_sta_offs = SPM_PWR_STATUS,
0077         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0078         .sram_pdn_bits = GENMASK(11, 8),
0079         .sram_pdn_ack_bits = 0,
0080     },
0081     [MT6795_POWER_DOMAIN_MFG_2D] = {
0082         .name = "mfg_2d",
0083         .sta_mask = PWR_STATUS_MFG_2D,
0084         .ctl_offs = SPM_MFG_2D_PWR_CON,
0085         .pwr_sta_offs = SPM_PWR_STATUS,
0086         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0087         .sram_pdn_bits = GENMASK(11, 8),
0088         .sram_pdn_ack_bits = GENMASK(13, 12),
0089     },
0090     [MT6795_POWER_DOMAIN_MFG] = {
0091         .name = "mfg",
0092         .sta_mask = PWR_STATUS_MFG,
0093         .ctl_offs = SPM_MFG_PWR_CON,
0094         .pwr_sta_offs = SPM_PWR_STATUS,
0095         .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
0096         .sram_pdn_bits = GENMASK(13, 8),
0097         .sram_pdn_ack_bits = GENMASK(21, 16),
0098         .bp_infracfg = {
0099             BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
0100                            MT8173_TOP_AXI_PROT_EN_MFG_M0 |
0101                            MT8173_TOP_AXI_PROT_EN_MFG_M1 |
0102                            MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
0103         },
0104     },
0105 };
0106
0107 static const struct scpsys_soc_data mt6795_scpsys_data = {
0108     .domains_data = scpsys_domain_data_mt6795,
0109     .num_domains = ARRAY_SIZE(scpsys_domain_data_mt6795),
0110 };
0111
0112 #endif /* __SOC_MEDIATEK_MT6795_PM_DOMAINS_H */