soc/imx/soc-imx8m.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2019 NXP.
0004  */
0005
0006 #include <linux/init.h>
0007 #include <linux/io.h>
0008 #include <linux/of_address.h>
0009 #include <linux/slab.h>
0010 #include <linux/sys_soc.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/arm-smccc.h>
0013 #include <linux/of.h>
0014
0015 #define REV_B1              0x21
0016
0017 #define IMX8MQ_SW_INFO_B1       0x40
0018 #define IMX8MQ_SW_MAGIC_B1      0xff0055aa
0019
0020 #define IMX_SIP_GET_SOC_INFO        0xc2000006
0021
0022 #define OCOTP_UID_LOW           0x410
0023 #define OCOTP_UID_HIGH          0x420
0024
0025 #define IMX8MP_OCOTP_UID_OFFSET     0x10
0026
0027 /* Same as ANADIG_DIGPROG_IMX7D */
0028 #define ANADIG_DIGPROG_IMX8MM   0x800
0029
0030 struct imx8_soc_data {
0031     char *name;
0032     u32 (*soc_revision)(void);
0033 };
0034
0035 static u64 soc_uid;
0036
0037 #ifdef CONFIG_HAVE_ARM_SMCCC
0038 static u32 imx8mq_soc_revision_from_atf(void)
0039 {
0040     struct arm_smccc_res res;
0041
0042     arm_smccc_smc(IMX_SIP_GET_SOC_INFO, 0, 0, 0, 0, 0, 0, 0, &res);
0043
0044     if (res.a0 == SMCCC_RET_NOT_SUPPORTED)
0045         return 0;
0046     else
0047         return res.a0 & 0xff;
0048 }
0049 #else
0050 static inline u32 imx8mq_soc_revision_from_atf(void) { return 0; };
0051 #endif
0052
0053 static u32 __init imx8mq_soc_revision(void)
0054 {
0055     struct device_node *np;
0056     void __iomem *ocotp_base;
0057     u32 magic;
0058     u32 rev;
0059
0060     np = of_find_compatible_node(NULL, NULL, "fsl,imx8mq-ocotp");
0061     if (!np)
0062         return 0;
0063
0064     ocotp_base = of_iomap(np, 0);
0065     WARN_ON(!ocotp_base);
0066
0067     /*
0068      * SOC revision on older imx8mq is not available in fuses so query
0069      * the value from ATF instead.
0070      */
0071     rev = imx8mq_soc_revision_from_atf();
0072     if (!rev) {
0073         magic = readl_relaxed(ocotp_base + IMX8MQ_SW_INFO_B1);
0074         if (magic == IMX8MQ_SW_MAGIC_B1)
0075             rev = REV_B1;
0076     }
0077
0078     soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH);
0079     soc_uid <<= 32;
0080     soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW);
0081
0082     iounmap(ocotp_base);
0083     of_node_put(np);
0084
0085     return rev;
0086 }
0087
0088 static void __init imx8mm_soc_uid(void)
0089 {
0090     void __iomem *ocotp_base;
0091     struct device_node *np;
0092     u32 offset = of_machine_is_compatible("fsl,imx8mp") ?
0093              IMX8MP_OCOTP_UID_OFFSET : 0;
0094
0095     np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-ocotp");
0096     if (!np)
0097         return;
0098
0099     ocotp_base = of_iomap(np, 0);
0100     WARN_ON(!ocotp_base);
0101
0102     soc_uid = readl_relaxed(ocotp_base + OCOTP_UID_HIGH + offset);
0103     soc_uid <<= 32;
0104     soc_uid |= readl_relaxed(ocotp_base + OCOTP_UID_LOW + offset);
0105
0106     iounmap(ocotp_base);
0107     of_node_put(np);
0108 }
0109
0110 static u32 __init imx8mm_soc_revision(void)
0111 {
0112     struct device_node *np;
0113     void __iomem *anatop_base;
0114     u32 rev;
0115
0116     np = of_find_compatible_node(NULL, NULL, "fsl,imx8mm-anatop");
0117     if (!np)
0118         return 0;
0119
0120     anatop_base = of_iomap(np, 0);
0121     WARN_ON(!anatop_base);
0122
0123     rev = readl_relaxed(anatop_base + ANADIG_DIGPROG_IMX8MM);
0124
0125     iounmap(anatop_base);
0126     of_node_put(np);
0127
0128     imx8mm_soc_uid();
0129
0130     return rev;
0131 }
0132
0133 static const struct imx8_soc_data imx8mq_soc_data = {
0134     .name = "i.MX8MQ",
0135     .soc_revision = imx8mq_soc_revision,
0136 };
0137
0138 static const struct imx8_soc_data imx8mm_soc_data = {
0139     .name = "i.MX8MM",
0140     .soc_revision = imx8mm_soc_revision,
0141 };
0142
0143 static const struct imx8_soc_data imx8mn_soc_data = {
0144     .name = "i.MX8MN",
0145     .soc_revision = imx8mm_soc_revision,
0146 };
0147
0148 static const struct imx8_soc_data imx8mp_soc_data = {
0149     .name = "i.MX8MP",
0150     .soc_revision = imx8mm_soc_revision,
0151 };
0152
0153 static __maybe_unused const struct of_device_id imx8_soc_match[] = {
0154     { .compatible = "fsl,imx8mq", .data = &imx8mq_soc_data, },
0155     { .compatible = "fsl,imx8mm", .data = &imx8mm_soc_data, },
0156     { .compatible = "fsl,imx8mn", .data = &imx8mn_soc_data, },
0157     { .compatible = "fsl,imx8mp", .data = &imx8mp_soc_data, },
0158     { }
0159 };
0160
0161 #define imx8_revision(soc_rev) \
0162     soc_rev ? \
0163     kasprintf(GFP_KERNEL, "%d.%d", (soc_rev >> 4) & 0xf,  soc_rev & 0xf) : \
0164     "unknown"
0165
0166 static int __init imx8_soc_init(void)
0167 {
0168     struct soc_device_attribute *soc_dev_attr;
0169     struct soc_device *soc_dev;
0170     const struct of_device_id *id;
0171     u32 soc_rev = 0;
0172     const struct imx8_soc_data *data;
0173     int ret;
0174
0175     soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
0176     if (!soc_dev_attr)
0177         return -ENOMEM;
0178
0179     soc_dev_attr->family = "Freescale i.MX";
0180
0181     ret = of_property_read_string(of_root, "model", &soc_dev_attr->machine);
0182     if (ret)
0183         goto free_soc;
0184
0185     id = of_match_node(imx8_soc_match, of_root);
0186     if (!id) {
0187         ret = -ENODEV;
0188         goto free_soc;
0189     }
0190
0191     data = id->data;
0192     if (data) {
0193         soc_dev_attr->soc_id = data->name;
0194         if (data->soc_revision)
0195             soc_rev = data->soc_revision();
0196     }
0197
0198     soc_dev_attr->revision = imx8_revision(soc_rev);
0199     if (!soc_dev_attr->revision) {
0200         ret = -ENOMEM;
0201         goto free_soc;
0202     }
0203
0204     soc_dev_attr->serial_number = kasprintf(GFP_KERNEL, "%016llX", soc_uid);
0205     if (!soc_dev_attr->serial_number) {
0206         ret = -ENOMEM;
0207         goto free_rev;
0208     }
0209
0210     soc_dev = soc_device_register(soc_dev_attr);
0211     if (IS_ERR(soc_dev)) {
0212         ret = PTR_ERR(soc_dev);
0213         goto free_serial_number;
0214     }
0215
0216     pr_info("SoC: %s revision %s\n", soc_dev_attr->soc_id,
0217         soc_dev_attr->revision);
0218
0219     if (IS_ENABLED(CONFIG_ARM_IMX_CPUFREQ_DT))
0220         platform_device_register_simple("imx-cpufreq-dt", -1, NULL, 0);
0221
0222     return 0;
0223
0224 free_serial_number:
0225     kfree(soc_dev_attr->serial_number);
0226 free_rev:
0227     if (strcmp(soc_dev_attr->revision, "unknown"))
0228         kfree(soc_dev_attr->revision);
0229 free_soc:
0230     kfree(soc_dev_attr);
0231     return ret;
0232 }
0233 device_initcall(imx8_soc_init);