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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
0004  *
0005  * Authors:     Shlomi Gridish <gridish@freescale.com>
0006  *      Li Yang <leoli@freescale.com>
0007  *
0008  * Description:
0009  * QE UCC Slow API Set - UCC Slow specific routines implementations.
0010  */
0011 #include <linux/kernel.h>
0012 #include <linux/errno.h>
0013 #include <linux/slab.h>
0014 #include <linux/stddef.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/err.h>
0017 #include <linux/export.h>
0018 
0019 #include <asm/io.h>
0020 #include <soc/fsl/qe/immap_qe.h>
0021 #include <soc/fsl/qe/qe.h>
0022 
0023 #include <soc/fsl/qe/ucc.h>
0024 #include <soc/fsl/qe/ucc_slow.h>
0025 
0026 u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
0027 {
0028     switch (uccs_num) {
0029     case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
0030     case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
0031     case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
0032     case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
0033     case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
0034     case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
0035     case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
0036     case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
0037     default: return QE_CR_SUBBLOCK_INVALID;
0038     }
0039 }
0040 EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
0041 
0042 void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
0043 {
0044     struct ucc_slow_info *us_info = uccs->us_info;
0045     u32 id;
0046 
0047     id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
0048     qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
0049              QE_CR_PROTOCOL_UNSPECIFIED, 0);
0050 }
0051 EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
0052 
0053 void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
0054 {
0055     struct ucc_slow_info *us_info = uccs->us_info;
0056     u32 id;
0057 
0058     id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
0059     qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
0060 }
0061 EXPORT_SYMBOL(ucc_slow_stop_tx);
0062 
0063 void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
0064 {
0065     struct ucc_slow_info *us_info = uccs->us_info;
0066     u32 id;
0067 
0068     id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
0069     qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
0070 }
0071 EXPORT_SYMBOL(ucc_slow_restart_tx);
0072 
0073 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
0074 {
0075     struct ucc_slow __iomem *us_regs;
0076     u32 gumr_l;
0077 
0078     us_regs = uccs->us_regs;
0079 
0080     /* Enable reception and/or transmission on this UCC. */
0081     gumr_l = ioread32be(&us_regs->gumr_l);
0082     if (mode & COMM_DIR_TX) {
0083         gumr_l |= UCC_SLOW_GUMR_L_ENT;
0084         uccs->enabled_tx = 1;
0085     }
0086     if (mode & COMM_DIR_RX) {
0087         gumr_l |= UCC_SLOW_GUMR_L_ENR;
0088         uccs->enabled_rx = 1;
0089     }
0090     iowrite32be(gumr_l, &us_regs->gumr_l);
0091 }
0092 EXPORT_SYMBOL(ucc_slow_enable);
0093 
0094 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
0095 {
0096     struct ucc_slow __iomem *us_regs;
0097     u32 gumr_l;
0098 
0099     us_regs = uccs->us_regs;
0100 
0101     /* Disable reception and/or transmission on this UCC. */
0102     gumr_l = ioread32be(&us_regs->gumr_l);
0103     if (mode & COMM_DIR_TX) {
0104         gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
0105         uccs->enabled_tx = 0;
0106     }
0107     if (mode & COMM_DIR_RX) {
0108         gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
0109         uccs->enabled_rx = 0;
0110     }
0111     iowrite32be(gumr_l, &us_regs->gumr_l);
0112 }
0113 EXPORT_SYMBOL(ucc_slow_disable);
0114 
0115 /* Initialize the UCC for Slow operations
0116  *
0117  * The caller should initialize the following us_info
0118  */
0119 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
0120 {
0121     struct ucc_slow_private *uccs;
0122     u32 i;
0123     struct ucc_slow __iomem *us_regs;
0124     u32 gumr;
0125     struct qe_bd __iomem *bd;
0126     u32 id;
0127     u32 command;
0128     int ret = 0;
0129 
0130     if (!us_info)
0131         return -EINVAL;
0132 
0133     /* check if the UCC port number is in range. */
0134     if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
0135         printk(KERN_ERR "%s: illegal UCC number\n", __func__);
0136         return -EINVAL;
0137     }
0138 
0139     /*
0140      * Set mrblr
0141      * Check that 'max_rx_buf_length' is properly aligned (4), unless
0142      * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
0143      * case when QE accepts 32 bits at a time.
0144      */
0145     if ((!us_info->rfw) &&
0146         (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
0147         printk(KERN_ERR "max_rx_buf_length not aligned.\n");
0148         return -EINVAL;
0149     }
0150 
0151     uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
0152     if (!uccs) {
0153         printk(KERN_ERR "%s: Cannot allocate private data\n",
0154             __func__);
0155         return -ENOMEM;
0156     }
0157     uccs->rx_base_offset = -1;
0158     uccs->tx_base_offset = -1;
0159     uccs->us_pram_offset = -1;
0160 
0161     /* Fill slow UCC structure */
0162     uccs->us_info = us_info;
0163     /* Set the PHY base address */
0164     uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
0165     if (uccs->us_regs == NULL) {
0166         printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
0167         kfree(uccs);
0168         return -ENOMEM;
0169     }
0170 
0171     us_regs = uccs->us_regs;
0172     uccs->p_ucce = &us_regs->ucce;
0173     uccs->p_uccm = &us_regs->uccm;
0174 
0175     /* Get PRAM base */
0176     uccs->us_pram_offset =
0177         qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
0178     if (uccs->us_pram_offset < 0) {
0179         printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
0180         ucc_slow_free(uccs);
0181         return -ENOMEM;
0182     }
0183     id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
0184     qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
0185              uccs->us_pram_offset);
0186 
0187     uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
0188 
0189     /* Set UCC to slow type */
0190     ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
0191     if (ret) {
0192         printk(KERN_ERR "%s: cannot set UCC type", __func__);
0193         ucc_slow_free(uccs);
0194         return ret;
0195     }
0196 
0197     iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
0198 
0199     INIT_LIST_HEAD(&uccs->confQ);
0200 
0201     /* Allocate BDs. */
0202     uccs->rx_base_offset =
0203         qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
0204                 QE_ALIGNMENT_OF_BD);
0205     if (uccs->rx_base_offset < 0) {
0206         printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
0207             us_info->rx_bd_ring_len);
0208         ucc_slow_free(uccs);
0209         return -ENOMEM;
0210     }
0211 
0212     uccs->tx_base_offset =
0213         qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
0214             QE_ALIGNMENT_OF_BD);
0215     if (uccs->tx_base_offset < 0) {
0216         printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
0217         ucc_slow_free(uccs);
0218         return -ENOMEM;
0219     }
0220 
0221     /* Init Tx bds */
0222     bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
0223     for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
0224         /* clear bd buffer */
0225         iowrite32be(0, &bd->buf);
0226         /* set bd status and length */
0227         iowrite32be(0, (u32 __iomem *)bd);
0228         bd++;
0229     }
0230     /* for last BD set Wrap bit */
0231     iowrite32be(0, &bd->buf);
0232     iowrite32be(T_W, (u32 __iomem *)bd);
0233 
0234     /* Init Rx bds */
0235     bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
0236     for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
0237         /* set bd status and length */
0238         iowrite32be(0, (u32 __iomem *)bd);
0239         /* clear bd buffer */
0240         iowrite32be(0, &bd->buf);
0241         bd++;
0242     }
0243     /* for last BD set Wrap bit */
0244     iowrite32be(R_W, (u32 __iomem *)bd);
0245     iowrite32be(0, &bd->buf);
0246 
0247     /* Set GUMR (For more details see the hardware spec.). */
0248     /* gumr_h */
0249     gumr = us_info->tcrc;
0250     if (us_info->cdp)
0251         gumr |= UCC_SLOW_GUMR_H_CDP;
0252     if (us_info->ctsp)
0253         gumr |= UCC_SLOW_GUMR_H_CTSP;
0254     if (us_info->cds)
0255         gumr |= UCC_SLOW_GUMR_H_CDS;
0256     if (us_info->ctss)
0257         gumr |= UCC_SLOW_GUMR_H_CTSS;
0258     if (us_info->tfl)
0259         gumr |= UCC_SLOW_GUMR_H_TFL;
0260     if (us_info->rfw)
0261         gumr |= UCC_SLOW_GUMR_H_RFW;
0262     if (us_info->txsy)
0263         gumr |= UCC_SLOW_GUMR_H_TXSY;
0264     if (us_info->rtsm)
0265         gumr |= UCC_SLOW_GUMR_H_RTSM;
0266     iowrite32be(gumr, &us_regs->gumr_h);
0267 
0268     /* gumr_l */
0269     gumr = (u32)us_info->tdcr | (u32)us_info->rdcr | (u32)us_info->tenc |
0270            (u32)us_info->renc | (u32)us_info->diag | (u32)us_info->mode;
0271     if (us_info->tci)
0272         gumr |= UCC_SLOW_GUMR_L_TCI;
0273     if (us_info->rinv)
0274         gumr |= UCC_SLOW_GUMR_L_RINV;
0275     if (us_info->tinv)
0276         gumr |= UCC_SLOW_GUMR_L_TINV;
0277     if (us_info->tend)
0278         gumr |= UCC_SLOW_GUMR_L_TEND;
0279     iowrite32be(gumr, &us_regs->gumr_l);
0280 
0281     /* Function code registers */
0282 
0283     /* if the data is in cachable memory, the 'global' */
0284     /* in the function code should be set. */
0285     iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->tbmr);
0286     iowrite8(UCC_BMR_BO_BE, &uccs->us_pram->rbmr);
0287 
0288     /* rbase, tbase are offsets from MURAM base */
0289     iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
0290     iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
0291 
0292     /* Mux clocking */
0293     /* Grant Support */
0294     ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
0295     /* Breakpoint Support */
0296     ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
0297     /* Set Tsa or NMSI mode. */
0298     ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
0299     /* If NMSI (not Tsa), set Tx and Rx clock. */
0300     if (!us_info->tsa) {
0301         /* Rx clock routing */
0302         if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
0303                     COMM_DIR_RX)) {
0304             printk(KERN_ERR "%s: illegal value for RX clock\n",
0305                    __func__);
0306             ucc_slow_free(uccs);
0307             return -EINVAL;
0308         }
0309         /* Tx clock routing */
0310         if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
0311                     COMM_DIR_TX)) {
0312             printk(KERN_ERR "%s: illegal value for TX clock\n",
0313                    __func__);
0314             ucc_slow_free(uccs);
0315             return -EINVAL;
0316         }
0317     }
0318 
0319     /* Set interrupt mask register at UCC level. */
0320     iowrite16be(us_info->uccm_mask, &us_regs->uccm);
0321 
0322     /* First, clear anything pending at UCC level,
0323      * otherwise, old garbage may come through
0324      * as soon as the dam is opened. */
0325 
0326     /* Writing '1' clears */
0327     iowrite16be(0xffff, &us_regs->ucce);
0328 
0329     /* Issue QE Init command */
0330     if (us_info->init_tx && us_info->init_rx)
0331         command = QE_INIT_TX_RX;
0332     else if (us_info->init_tx)
0333         command = QE_INIT_TX;
0334     else
0335         command = QE_INIT_RX;   /* We know at least one is TRUE */
0336 
0337     qe_issue_cmd(command, id, us_info->protocol, 0);
0338 
0339     *uccs_ret = uccs;
0340     return 0;
0341 }
0342 EXPORT_SYMBOL(ucc_slow_init);
0343 
0344 void ucc_slow_free(struct ucc_slow_private * uccs)
0345 {
0346     if (!uccs)
0347         return;
0348 
0349     qe_muram_free(uccs->rx_base_offset);
0350     qe_muram_free(uccs->tx_base_offset);
0351     qe_muram_free(uccs->us_pram_offset);
0352 
0353     if (uccs->us_regs)
0354         iounmap(uccs->us_regs);
0355 
0356     kfree(uccs);
0357 }
0358 EXPORT_SYMBOL(ucc_slow_free);
0359
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