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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
0004  *
0005  * Authors:     Shlomi Gridish <gridish@freescale.com>
0006  *      Li Yang <leoli@freescale.com>
0007  *
0008  * Description:
0009  * QE UCC Fast API Set - UCC Fast specific routines implementations.
0010  */
0011 #include <linux/kernel.h>
0012 #include <linux/errno.h>
0013 #include <linux/slab.h>
0014 #include <linux/stddef.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/err.h>
0017 #include <linux/export.h>
0018 
0019 #include <asm/io.h>
0020 #include <soc/fsl/qe/immap_qe.h>
0021 #include <soc/fsl/qe/qe.h>
0022 
0023 #include <soc/fsl/qe/ucc.h>
0024 #include <soc/fsl/qe/ucc_fast.h>
0025 
0026 void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
0027 {
0028     printk(KERN_INFO "UCC%u Fast registers:\n", uccf->uf_info->ucc_num);
0029     printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
0030 
0031     printk(KERN_INFO "gumr  : addr=0x%p, val=0x%08x\n",
0032           &uccf->uf_regs->gumr, ioread32be(&uccf->uf_regs->gumr));
0033     printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
0034           &uccf->uf_regs->upsmr, ioread32be(&uccf->uf_regs->upsmr));
0035     printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
0036           &uccf->uf_regs->utodr, ioread16be(&uccf->uf_regs->utodr));
0037     printk(KERN_INFO "udsr  : addr=0x%p, val=0x%04x\n",
0038           &uccf->uf_regs->udsr, ioread16be(&uccf->uf_regs->udsr));
0039     printk(KERN_INFO "ucce  : addr=0x%p, val=0x%08x\n",
0040           &uccf->uf_regs->ucce, ioread32be(&uccf->uf_regs->ucce));
0041     printk(KERN_INFO "uccm  : addr=0x%p, val=0x%08x\n",
0042           &uccf->uf_regs->uccm, ioread32be(&uccf->uf_regs->uccm));
0043     printk(KERN_INFO "uccs  : addr=0x%p, val=0x%02x\n",
0044           &uccf->uf_regs->uccs, ioread8(&uccf->uf_regs->uccs));
0045     printk(KERN_INFO "urfb  : addr=0x%p, val=0x%08x\n",
0046           &uccf->uf_regs->urfb, ioread32be(&uccf->uf_regs->urfb));
0047     printk(KERN_INFO "urfs  : addr=0x%p, val=0x%04x\n",
0048           &uccf->uf_regs->urfs, ioread16be(&uccf->uf_regs->urfs));
0049     printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
0050           &uccf->uf_regs->urfet, ioread16be(&uccf->uf_regs->urfet));
0051     printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
0052           &uccf->uf_regs->urfset,
0053           ioread16be(&uccf->uf_regs->urfset));
0054     printk(KERN_INFO "utfb  : addr=0x%p, val=0x%08x\n",
0055           &uccf->uf_regs->utfb, ioread32be(&uccf->uf_regs->utfb));
0056     printk(KERN_INFO "utfs  : addr=0x%p, val=0x%04x\n",
0057           &uccf->uf_regs->utfs, ioread16be(&uccf->uf_regs->utfs));
0058     printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
0059           &uccf->uf_regs->utfet, ioread16be(&uccf->uf_regs->utfet));
0060     printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
0061           &uccf->uf_regs->utftt, ioread16be(&uccf->uf_regs->utftt));
0062     printk(KERN_INFO "utpt  : addr=0x%p, val=0x%04x\n",
0063           &uccf->uf_regs->utpt, ioread16be(&uccf->uf_regs->utpt));
0064     printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
0065           &uccf->uf_regs->urtry, ioread32be(&uccf->uf_regs->urtry));
0066     printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
0067           &uccf->uf_regs->guemr, ioread8(&uccf->uf_regs->guemr));
0068 }
0069 EXPORT_SYMBOL(ucc_fast_dump_regs);
0070 
0071 u32 ucc_fast_get_qe_cr_subblock(int uccf_num)
0072 {
0073     switch (uccf_num) {
0074     case 0: return QE_CR_SUBBLOCK_UCCFAST1;
0075     case 1: return QE_CR_SUBBLOCK_UCCFAST2;
0076     case 2: return QE_CR_SUBBLOCK_UCCFAST3;
0077     case 3: return QE_CR_SUBBLOCK_UCCFAST4;
0078     case 4: return QE_CR_SUBBLOCK_UCCFAST5;
0079     case 5: return QE_CR_SUBBLOCK_UCCFAST6;
0080     case 6: return QE_CR_SUBBLOCK_UCCFAST7;
0081     case 7: return QE_CR_SUBBLOCK_UCCFAST8;
0082     default: return QE_CR_SUBBLOCK_INVALID;
0083     }
0084 }
0085 EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
0086 
0087 void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
0088 {
0089     iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
0090 }
0091 EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
0092 
0093 void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
0094 {
0095     struct ucc_fast __iomem *uf_regs;
0096     u32 gumr;
0097 
0098     uf_regs = uccf->uf_regs;
0099 
0100     /* Enable reception and/or transmission on this UCC. */
0101     gumr = ioread32be(&uf_regs->gumr);
0102     if (mode & COMM_DIR_TX) {
0103         gumr |= UCC_FAST_GUMR_ENT;
0104         uccf->enabled_tx = 1;
0105     }
0106     if (mode & COMM_DIR_RX) {
0107         gumr |= UCC_FAST_GUMR_ENR;
0108         uccf->enabled_rx = 1;
0109     }
0110     iowrite32be(gumr, &uf_regs->gumr);
0111 }
0112 EXPORT_SYMBOL(ucc_fast_enable);
0113 
0114 void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
0115 {
0116     struct ucc_fast __iomem *uf_regs;
0117     u32 gumr;
0118 
0119     uf_regs = uccf->uf_regs;
0120 
0121     /* Disable reception and/or transmission on this UCC. */
0122     gumr = ioread32be(&uf_regs->gumr);
0123     if (mode & COMM_DIR_TX) {
0124         gumr &= ~UCC_FAST_GUMR_ENT;
0125         uccf->enabled_tx = 0;
0126     }
0127     if (mode & COMM_DIR_RX) {
0128         gumr &= ~UCC_FAST_GUMR_ENR;
0129         uccf->enabled_rx = 0;
0130     }
0131     iowrite32be(gumr, &uf_regs->gumr);
0132 }
0133 EXPORT_SYMBOL(ucc_fast_disable);
0134 
0135 int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** uccf_ret)
0136 {
0137     struct ucc_fast_private *uccf;
0138     struct ucc_fast __iomem *uf_regs;
0139     u32 gumr;
0140     int ret;
0141 
0142     if (!uf_info)
0143         return -EINVAL;
0144 
0145     /* check if the UCC port number is in range. */
0146     if ((uf_info->ucc_num < 0) || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
0147         printk(KERN_ERR "%s: illegal UCC number\n", __func__);
0148         return -EINVAL;
0149     }
0150 
0151     /* Check that 'max_rx_buf_length' is properly aligned (4). */
0152     if (uf_info->max_rx_buf_length & (UCC_FAST_MRBLR_ALIGNMENT - 1)) {
0153         printk(KERN_ERR "%s: max_rx_buf_length not aligned\n",
0154             __func__);
0155         return -EINVAL;
0156     }
0157 
0158     /* Validate Virtual Fifo register values */
0159     if (uf_info->urfs < UCC_FAST_URFS_MIN_VAL) {
0160         printk(KERN_ERR "%s: urfs is too small\n", __func__);
0161         return -EINVAL;
0162     }
0163 
0164     if (uf_info->urfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
0165         printk(KERN_ERR "%s: urfs is not aligned\n", __func__);
0166         return -EINVAL;
0167     }
0168 
0169     if (uf_info->urfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
0170         printk(KERN_ERR "%s: urfet is not aligned.\n", __func__);
0171         return -EINVAL;
0172     }
0173 
0174     if (uf_info->urfset & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
0175         printk(KERN_ERR "%s: urfset is not aligned\n", __func__);
0176         return -EINVAL;
0177     }
0178 
0179     if (uf_info->utfs & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
0180         printk(KERN_ERR "%s: utfs is not aligned\n", __func__);
0181         return -EINVAL;
0182     }
0183 
0184     if (uf_info->utfet & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
0185         printk(KERN_ERR "%s: utfet is not aligned\n", __func__);
0186         return -EINVAL;
0187     }
0188 
0189     if (uf_info->utftt & (UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT - 1)) {
0190         printk(KERN_ERR "%s: utftt is not aligned\n", __func__);
0191         return -EINVAL;
0192     }
0193 
0194     uccf = kzalloc(sizeof(struct ucc_fast_private), GFP_KERNEL);
0195     if (!uccf) {
0196         printk(KERN_ERR "%s: Cannot allocate private data\n",
0197             __func__);
0198         return -ENOMEM;
0199     }
0200     uccf->ucc_fast_tx_virtual_fifo_base_offset = -1;
0201     uccf->ucc_fast_rx_virtual_fifo_base_offset = -1;
0202 
0203     /* Fill fast UCC structure */
0204     uccf->uf_info = uf_info;
0205     /* Set the PHY base address */
0206     uccf->uf_regs = ioremap(uf_info->regs, sizeof(struct ucc_fast));
0207     if (uccf->uf_regs == NULL) {
0208         printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
0209         kfree(uccf);
0210         return -ENOMEM;
0211     }
0212 
0213     uccf->enabled_tx = 0;
0214     uccf->enabled_rx = 0;
0215     uccf->stopped_tx = 0;
0216     uccf->stopped_rx = 0;
0217     uf_regs = uccf->uf_regs;
0218     uccf->p_ucce = &uf_regs->ucce;
0219     uccf->p_uccm = &uf_regs->uccm;
0220 #ifdef CONFIG_UGETH_TX_ON_DEMAND
0221     uccf->p_utodr = &uf_regs->utodr;
0222 #endif
0223 #ifdef STATISTICS
0224     uccf->tx_frames = 0;
0225     uccf->rx_frames = 0;
0226     uccf->rx_discarded = 0;
0227 #endif              /* STATISTICS */
0228 
0229     /* Set UCC to fast type */
0230     ret = ucc_set_type(uf_info->ucc_num, UCC_SPEED_TYPE_FAST);
0231     if (ret) {
0232         printk(KERN_ERR "%s: cannot set UCC type\n", __func__);
0233         ucc_fast_free(uccf);
0234         return ret;
0235     }
0236 
0237     uccf->mrblr = uf_info->max_rx_buf_length;
0238 
0239     /* Set GUMR */
0240     /* For more details see the hardware spec. */
0241     gumr = uf_info->ttx_trx;
0242     if (uf_info->tci)
0243         gumr |= UCC_FAST_GUMR_TCI;
0244     if (uf_info->cdp)
0245         gumr |= UCC_FAST_GUMR_CDP;
0246     if (uf_info->ctsp)
0247         gumr |= UCC_FAST_GUMR_CTSP;
0248     if (uf_info->cds)
0249         gumr |= UCC_FAST_GUMR_CDS;
0250     if (uf_info->ctss)
0251         gumr |= UCC_FAST_GUMR_CTSS;
0252     if (uf_info->txsy)
0253         gumr |= UCC_FAST_GUMR_TXSY;
0254     if (uf_info->rsyn)
0255         gumr |= UCC_FAST_GUMR_RSYN;
0256     gumr |= uf_info->synl;
0257     if (uf_info->rtsm)
0258         gumr |= UCC_FAST_GUMR_RTSM;
0259     gumr |= uf_info->renc;
0260     if (uf_info->revd)
0261         gumr |= UCC_FAST_GUMR_REVD;
0262     gumr |= uf_info->tenc;
0263     gumr |= uf_info->tcrc;
0264     gumr |= uf_info->mode;
0265     iowrite32be(gumr, &uf_regs->gumr);
0266 
0267     /* Allocate memory for Tx Virtual Fifo */
0268     uccf->ucc_fast_tx_virtual_fifo_base_offset =
0269         qe_muram_alloc(uf_info->utfs, UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
0270     if (uccf->ucc_fast_tx_virtual_fifo_base_offset < 0) {
0271         printk(KERN_ERR "%s: cannot allocate MURAM for TX FIFO\n",
0272             __func__);
0273         ucc_fast_free(uccf);
0274         return -ENOMEM;
0275     }
0276 
0277     /* Allocate memory for Rx Virtual Fifo */
0278     uccf->ucc_fast_rx_virtual_fifo_base_offset =
0279         qe_muram_alloc(uf_info->urfs +
0280                UCC_FAST_RECEIVE_VIRTUAL_FIFO_SIZE_FUDGE_FACTOR,
0281                UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
0282     if (uccf->ucc_fast_rx_virtual_fifo_base_offset < 0) {
0283         printk(KERN_ERR "%s: cannot allocate MURAM for RX FIFO\n",
0284             __func__);
0285         ucc_fast_free(uccf);
0286         return -ENOMEM;
0287     }
0288 
0289     /* Set Virtual Fifo registers */
0290     iowrite16be(uf_info->urfs, &uf_regs->urfs);
0291     iowrite16be(uf_info->urfet, &uf_regs->urfet);
0292     iowrite16be(uf_info->urfset, &uf_regs->urfset);
0293     iowrite16be(uf_info->utfs, &uf_regs->utfs);
0294     iowrite16be(uf_info->utfet, &uf_regs->utfet);
0295     iowrite16be(uf_info->utftt, &uf_regs->utftt);
0296     /* utfb, urfb are offsets from MURAM base */
0297     iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
0298                &uf_regs->utfb);
0299     iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
0300                &uf_regs->urfb);
0301 
0302     /* Mux clocking */
0303     /* Grant Support */
0304     ucc_set_qe_mux_grant(uf_info->ucc_num, uf_info->grant_support);
0305     /* Breakpoint Support */
0306     ucc_set_qe_mux_bkpt(uf_info->ucc_num, uf_info->brkpt_support);
0307     /* Set Tsa or NMSI mode. */
0308     ucc_set_qe_mux_tsa(uf_info->ucc_num, uf_info->tsa);
0309     /* If NMSI (not Tsa), set Tx and Rx clock. */
0310     if (!uf_info->tsa) {
0311         /* Rx clock routing */
0312         if ((uf_info->rx_clock != QE_CLK_NONE) &&
0313             ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->rx_clock,
0314                     COMM_DIR_RX)) {
0315             printk(KERN_ERR "%s: illegal value for RX clock\n",
0316                    __func__);
0317             ucc_fast_free(uccf);
0318             return -EINVAL;
0319         }
0320         /* Tx clock routing */
0321         if ((uf_info->tx_clock != QE_CLK_NONE) &&
0322             ucc_set_qe_mux_rxtx(uf_info->ucc_num, uf_info->tx_clock,
0323                     COMM_DIR_TX)) {
0324             printk(KERN_ERR "%s: illegal value for TX clock\n",
0325                    __func__);
0326             ucc_fast_free(uccf);
0327             return -EINVAL;
0328         }
0329     } else {
0330         /* tdm Rx clock routing */
0331         if ((uf_info->rx_clock != QE_CLK_NONE) &&
0332             ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->rx_clock,
0333                      COMM_DIR_RX)) {
0334             pr_err("%s: illegal value for RX clock", __func__);
0335             ucc_fast_free(uccf);
0336             return -EINVAL;
0337         }
0338 
0339         /* tdm Tx clock routing */
0340         if ((uf_info->tx_clock != QE_CLK_NONE) &&
0341             ucc_set_tdm_rxtx_clk(uf_info->tdm_num, uf_info->tx_clock,
0342                      COMM_DIR_TX)) {
0343             pr_err("%s: illegal value for TX clock", __func__);
0344             ucc_fast_free(uccf);
0345             return -EINVAL;
0346         }
0347 
0348         /* tdm Rx sync clock routing */
0349         if ((uf_info->rx_sync != QE_CLK_NONE) &&
0350             ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->rx_sync,
0351                       COMM_DIR_RX)) {
0352             pr_err("%s: illegal value for RX clock", __func__);
0353             ucc_fast_free(uccf);
0354             return -EINVAL;
0355         }
0356 
0357         /* tdm Tx sync clock routing */
0358         if ((uf_info->tx_sync != QE_CLK_NONE) &&
0359             ucc_set_tdm_rxtx_sync(uf_info->tdm_num, uf_info->tx_sync,
0360                       COMM_DIR_TX)) {
0361             pr_err("%s: illegal value for TX clock", __func__);
0362             ucc_fast_free(uccf);
0363             return -EINVAL;
0364         }
0365     }
0366 
0367     /* Set interrupt mask register at UCC level. */
0368     iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
0369 
0370     /* First, clear anything pending at UCC level,
0371      * otherwise, old garbage may come through
0372      * as soon as the dam is opened. */
0373 
0374     /* Writing '1' clears */
0375     iowrite32be(0xffffffff, &uf_regs->ucce);
0376 
0377     *uccf_ret = uccf;
0378     return 0;
0379 }
0380 EXPORT_SYMBOL(ucc_fast_init);
0381 
0382 void ucc_fast_free(struct ucc_fast_private * uccf)
0383 {
0384     if (!uccf)
0385         return;
0386 
0387     qe_muram_free(uccf->ucc_fast_tx_virtual_fifo_base_offset);
0388     qe_muram_free(uccf->ucc_fast_rx_virtual_fifo_base_offset);
0389 
0390     if (uccf->uf_regs)
0391         iounmap(uccf->uf_regs);
0392 
0393     kfree(uccf);
0394 }
0395 EXPORT_SYMBOL(ucc_fast_free);
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