fsl/qe/qe_io.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * arch/powerpc/sysdev/qe_lib/qe_io.c
0004  *
0005  * QE Parallel I/O ports configuration routines
0006  *
0007  * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
0008  *
0009  * Author: Li Yang <LeoLi@freescale.com>
0010  * Based on code from Shlomi Gridish <gridish@freescale.com>
0011  */
0012
0013 #include <linux/stddef.h>
0014 #include <linux/kernel.h>
0015 #include <linux/errno.h>
0016 #include <linux/module.h>
0017 #include <linux/ioport.h>
0018
0019 #include <asm/io.h>
0020 #include <soc/fsl/qe/qe.h>
0021
0022 #undef DEBUG
0023
0024 static struct qe_pio_regs __iomem *par_io;
0025 static int num_par_io_ports = 0;
0026
0027 int par_io_init(struct device_node *np)
0028 {
0029     struct resource res;
0030     int ret;
0031     u32 num_ports;
0032
0033     /* Map Parallel I/O ports registers */
0034     ret = of_address_to_resource(np, 0, &res);
0035     if (ret)
0036         return ret;
0037     par_io = ioremap(res.start, resource_size(&res));
0038     if (!par_io)
0039         return -ENOMEM;
0040
0041     if (!of_property_read_u32(np, "num-ports", &num_ports))
0042         num_par_io_ports = num_ports;
0043
0044     return 0;
0045 }
0046
0047 void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
0048              int open_drain, int assignment, int has_irq)
0049 {
0050     u32 pin_mask1bit;
0051     u32 pin_mask2bits;
0052     u32 new_mask2bits;
0053     u32 tmp_val;
0054
0055     /* calculate pin location for single and 2 bits information */
0056     pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
0057
0058     /* Set open drain, if required */
0059     tmp_val = ioread32be(&par_io->cpodr);
0060     if (open_drain)
0061         iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
0062     else
0063         iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
0064
0065     /* define direction */
0066     tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
0067         ioread32be(&par_io->cpdir2) :
0068         ioread32be(&par_io->cpdir1);
0069
0070     /* get all bits mask for 2 bit per port */
0071     pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
0072                 (pin % (QE_PIO_PINS / 2) + 1) * 2));
0073
0074     /* Get the final mask we need for the right definition */
0075     new_mask2bits = (u32) (dir << (QE_PIO_PINS -
0076                 (pin % (QE_PIO_PINS / 2) + 1) * 2));
0077
0078     /* clear and set 2 bits mask */
0079     if (pin > (QE_PIO_PINS / 2) - 1) {
0080         iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
0081         tmp_val &= ~pin_mask2bits;
0082         iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
0083     } else {
0084         iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
0085         tmp_val &= ~pin_mask2bits;
0086         iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
0087     }
0088     /* define pin assignment */
0089     tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
0090         ioread32be(&par_io->cppar2) :
0091         ioread32be(&par_io->cppar1);
0092
0093     new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
0094             (pin % (QE_PIO_PINS / 2) + 1) * 2));
0095     /* clear and set 2 bits mask */
0096     if (pin > (QE_PIO_PINS / 2) - 1) {
0097         iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
0098         tmp_val &= ~pin_mask2bits;
0099         iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
0100     } else {
0101         iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
0102         tmp_val &= ~pin_mask2bits;
0103         iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
0104     }
0105 }
0106 EXPORT_SYMBOL(__par_io_config_pin);
0107
0108 int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
0109               int assignment, int has_irq)
0110 {
0111     if (!par_io || port >= num_par_io_ports)
0112         return -EINVAL;
0113
0114     __par_io_config_pin(&par_io[port], pin, dir, open_drain, assignment,
0115                 has_irq);
0116     return 0;
0117 }
0118 EXPORT_SYMBOL(par_io_config_pin);
0119
0120 int par_io_data_set(u8 port, u8 pin, u8 val)
0121 {
0122     u32 pin_mask, tmp_val;
0123
0124     if (port >= num_par_io_ports)
0125         return -EINVAL;
0126     if (pin >= QE_PIO_PINS)
0127         return -EINVAL;
0128     /* calculate pin location */
0129     pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
0130
0131     tmp_val = ioread32be(&par_io[port].cpdata);
0132
0133     if (val == 0)       /* clear */
0134         iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
0135     else            /* set */
0136         iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
0137
0138     return 0;
0139 }
0140 EXPORT_SYMBOL(par_io_data_set);
0141
0142 int par_io_of_config(struct device_node *np)
0143 {
0144     struct device_node *pio;
0145     int pio_map_len;
0146     const __be32 *pio_map;
0147
0148     if (par_io == NULL) {
0149         printk(KERN_ERR "par_io not initialized\n");
0150         return -1;
0151     }
0152
0153     pio = of_parse_phandle(np, "pio-handle", 0);
0154     if (pio == NULL) {
0155         printk(KERN_ERR "pio-handle not available\n");
0156         return -1;
0157     }
0158
0159     pio_map = of_get_property(pio, "pio-map", &pio_map_len);
0160     if (pio_map == NULL) {
0161         printk(KERN_ERR "pio-map is not set!\n");
0162         return -1;
0163     }
0164     pio_map_len /= sizeof(unsigned int);
0165     if ((pio_map_len % 6) != 0) {
0166         printk(KERN_ERR "pio-map format wrong!\n");
0167         return -1;
0168     }
0169
0170     while (pio_map_len > 0) {
0171         u8 port        = be32_to_cpu(pio_map[0]);
0172         u8 pin         = be32_to_cpu(pio_map[1]);
0173         int dir        = be32_to_cpu(pio_map[2]);
0174         int open_drain = be32_to_cpu(pio_map[3]);
0175         int assignment = be32_to_cpu(pio_map[4]);
0176         int has_irq    = be32_to_cpu(pio_map[5]);
0177
0178         par_io_config_pin(port, pin, dir, open_drain,
0179                   assignment, has_irq);
0180         pio_map += 6;
0181         pio_map_len -= 6;
0182     }
0183     of_node_put(pio);
0184     return 0;
0185 }
0186 EXPORT_SYMBOL(par_io_of_config);