fsl/qe/qe.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2006-2010 Freescale Semiconductor, Inc. All rights reserved.
0004  *
0005  * Authors:     Shlomi Gridish <gridish@freescale.com>
0006  *      Li Yang <leoli@freescale.com>
0007  * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
0008  *
0009  * Description:
0010  * General Purpose functions for the global management of the
0011  * QUICC Engine (QE).
0012  */
0013 #include <linux/bitmap.h>
0014 #include <linux/errno.h>
0015 #include <linux/sched.h>
0016 #include <linux/kernel.h>
0017 #include <linux/param.h>
0018 #include <linux/string.h>
0019 #include <linux/spinlock.h>
0020 #include <linux/mm.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/module.h>
0023 #include <linux/delay.h>
0024 #include <linux/ioport.h>
0025 #include <linux/iopoll.h>
0026 #include <linux/crc32.h>
0027 #include <linux/mod_devicetable.h>
0028 #include <linux/of_platform.h>
0029 #include <soc/fsl/qe/immap_qe.h>
0030 #include <soc/fsl/qe/qe.h>
0031
0032 static void qe_snums_init(void);
0033 static int qe_sdma_init(void);
0034
0035 static DEFINE_SPINLOCK(qe_lock);
0036 DEFINE_SPINLOCK(cmxgcr_lock);
0037 EXPORT_SYMBOL(cmxgcr_lock);
0038
0039 /* We allocate this here because it is used almost exclusively for
0040  * the communication processor devices.
0041  */
0042 struct qe_immap __iomem *qe_immr;
0043 EXPORT_SYMBOL(qe_immr);
0044
0045 static u8 snums[QE_NUM_OF_SNUM];    /* Dynamically allocated SNUMs */
0046 static DECLARE_BITMAP(snum_state, QE_NUM_OF_SNUM);
0047 static unsigned int qe_num_of_snum;
0048
0049 static phys_addr_t qebase = -1;
0050
0051 static struct device_node *qe_get_device_node(void)
0052 {
0053     struct device_node *qe;
0054
0055     /*
0056      * Newer device trees have an "fsl,qe" compatible property for the QE
0057      * node, but we still need to support older device trees.
0058      */
0059     qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
0060     if (qe)
0061         return qe;
0062     return of_find_node_by_type(NULL, "qe");
0063 }
0064
0065 static phys_addr_t get_qe_base(void)
0066 {
0067     struct device_node *qe;
0068     int ret;
0069     struct resource res;
0070
0071     if (qebase != -1)
0072         return qebase;
0073
0074     qe = qe_get_device_node();
0075     if (!qe)
0076         return qebase;
0077
0078     ret = of_address_to_resource(qe, 0, &res);
0079     if (!ret)
0080         qebase = res.start;
0081     of_node_put(qe);
0082
0083     return qebase;
0084 }
0085
0086 void qe_reset(void)
0087 {
0088     if (qe_immr == NULL)
0089         qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
0090
0091     qe_snums_init();
0092
0093     qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
0094              QE_CR_PROTOCOL_UNSPECIFIED, 0);
0095
0096     /* Reclaim the MURAM memory for our use. */
0097     qe_muram_init();
0098
0099     if (qe_sdma_init())
0100         panic("sdma init failed!");
0101 }
0102
0103 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
0104 {
0105     unsigned long flags;
0106     u8 mcn_shift = 0, dev_shift = 0;
0107     u32 val;
0108     int ret;
0109
0110     spin_lock_irqsave(&qe_lock, flags);
0111     if (cmd == QE_RESET) {
0112         iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
0113     } else {
0114         if (cmd == QE_ASSIGN_PAGE) {
0115             /* Here device is the SNUM, not sub-block */
0116             dev_shift = QE_CR_SNUM_SHIFT;
0117         } else if (cmd == QE_ASSIGN_RISC) {
0118             /* Here device is the SNUM, and mcnProtocol is
0119              * e_QeCmdRiscAssignment value */
0120             dev_shift = QE_CR_SNUM_SHIFT;
0121             mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
0122         } else {
0123             if (device == QE_CR_SUBBLOCK_USB)
0124                 mcn_shift = QE_CR_MCN_USB_SHIFT;
0125             else
0126                 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
0127         }
0128
0129         iowrite32be(cmd_input, &qe_immr->cp.cecdr);
0130         iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
0131                    &qe_immr->cp.cecr);
0132     }
0133
0134     /* wait for the QE_CR_FLG to clear */
0135     ret = readx_poll_timeout_atomic(ioread32be, &qe_immr->cp.cecr, val,
0136                     (val & QE_CR_FLG) == 0, 0, 100);
0137     /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
0138     spin_unlock_irqrestore(&qe_lock, flags);
0139
0140     return ret == 0;
0141 }
0142 EXPORT_SYMBOL(qe_issue_cmd);
0143
0144 /* Set a baud rate generator. This needs lots of work. There are
0145  * 16 BRGs, which can be connected to the QE channels or output
0146  * as clocks. The BRGs are in two different block of internal
0147  * memory mapped space.
0148  * The BRG clock is the QE clock divided by 2.
0149  * It was set up long ago during the initial boot phase and is
0150  * given to us.
0151  * Baud rate clocks are zero-based in the driver code (as that maps
0152  * to port numbers). Documentation uses 1-based numbering.
0153  */
0154 static unsigned int brg_clk = 0;
0155
0156 #define CLK_GRAN    (1000)
0157 #define CLK_GRAN_LIMIT  (5)
0158
0159 unsigned int qe_get_brg_clk(void)
0160 {
0161     struct device_node *qe;
0162     u32 brg;
0163     unsigned int mod;
0164
0165     if (brg_clk)
0166         return brg_clk;
0167
0168     qe = qe_get_device_node();
0169     if (!qe)
0170         return brg_clk;
0171
0172     if (!of_property_read_u32(qe, "brg-frequency", &brg))
0173         brg_clk = brg;
0174
0175     of_node_put(qe);
0176
0177     /* round this if near to a multiple of CLK_GRAN */
0178     mod = brg_clk % CLK_GRAN;
0179     if (mod) {
0180         if (mod < CLK_GRAN_LIMIT)
0181             brg_clk -= mod;
0182         else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
0183             brg_clk += CLK_GRAN - mod;
0184     }
0185
0186     return brg_clk;
0187 }
0188 EXPORT_SYMBOL(qe_get_brg_clk);
0189
0190 #define PVR_VER_836x    0x8083
0191 #define PVR_VER_832x    0x8084
0192
0193 static bool qe_general4_errata(void)
0194 {
0195 #ifdef CONFIG_PPC32
0196     return pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x);
0197 #endif
0198     return false;
0199 }
0200
0201 /* Program the BRG to the given sampling rate and multiplier
0202  *
0203  * @brg: the BRG, QE_BRG1 - QE_BRG16
0204  * @rate: the desired sampling rate
0205  * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
0206  * GUMR_L[TDCR].  E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
0207  * then 'multiplier' should be 8.
0208  */
0209 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
0210 {
0211     u32 divisor, tempval;
0212     u32 div16 = 0;
0213
0214     if ((brg < QE_BRG1) || (brg > QE_BRG16))
0215         return -EINVAL;
0216
0217     divisor = qe_get_brg_clk() / (rate * multiplier);
0218
0219     if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
0220         div16 = QE_BRGC_DIV16;
0221         divisor /= 16;
0222     }
0223
0224     /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
0225        that the BRG divisor must be even if you're not using divide-by-16
0226        mode. */
0227     if (qe_general4_errata())
0228         if (!div16 && (divisor & 1) && (divisor > 3))
0229             divisor++;
0230
0231     tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
0232         QE_BRGC_ENABLE | div16;
0233
0234     iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
0235
0236     return 0;
0237 }
0238 EXPORT_SYMBOL(qe_setbrg);
0239
0240 /* Convert a string to a QE clock source enum
0241  *
0242  * This function takes a string, typically from a property in the device
0243  * tree, and returns the corresponding "enum qe_clock" value.
0244 */
0245 enum qe_clock qe_clock_source(const char *source)
0246 {
0247     unsigned int i;
0248
0249     if (strcasecmp(source, "none") == 0)
0250         return QE_CLK_NONE;
0251
0252     if (strcmp(source, "tsync_pin") == 0)
0253         return QE_TSYNC_PIN;
0254
0255     if (strcmp(source, "rsync_pin") == 0)
0256         return QE_RSYNC_PIN;
0257
0258     if (strncasecmp(source, "brg", 3) == 0) {
0259         i = simple_strtoul(source + 3, NULL, 10);
0260         if ((i >= 1) && (i <= 16))
0261             return (QE_BRG1 - 1) + i;
0262         else
0263             return QE_CLK_DUMMY;
0264     }
0265
0266     if (strncasecmp(source, "clk", 3) == 0) {
0267         i = simple_strtoul(source + 3, NULL, 10);
0268         if ((i >= 1) && (i <= 24))
0269             return (QE_CLK1 - 1) + i;
0270         else
0271             return QE_CLK_DUMMY;
0272     }
0273
0274     return QE_CLK_DUMMY;
0275 }
0276 EXPORT_SYMBOL(qe_clock_source);
0277
0278 /* Initialize SNUMs (thread serial numbers) according to
0279  * QE Module Control chapter, SNUM table
0280  */
0281 static void qe_snums_init(void)
0282 {
0283     static const u8 snum_init_76[] = {
0284         0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0285         0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0286         0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
0287         0xD8, 0xD9, 0xE8, 0xE9, 0x44, 0x45, 0x4C, 0x4D,
0288         0x54, 0x55, 0x5C, 0x5D, 0x64, 0x65, 0x6C, 0x6D,
0289         0x74, 0x75, 0x7C, 0x7D, 0x84, 0x85, 0x8C, 0x8D,
0290         0x94, 0x95, 0x9C, 0x9D, 0xA4, 0xA5, 0xAC, 0xAD,
0291         0xB4, 0xB5, 0xBC, 0xBD, 0xC4, 0xC5, 0xCC, 0xCD,
0292         0xD4, 0xD5, 0xDC, 0xDD, 0xE4, 0xE5, 0xEC, 0xED,
0293         0xF4, 0xF5, 0xFC, 0xFD,
0294     };
0295     static const u8 snum_init_46[] = {
0296         0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
0297         0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
0298         0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
0299         0xD8, 0xD9, 0xE8, 0xE9, 0x08, 0x09, 0x18, 0x19,
0300         0x28, 0x29, 0x38, 0x39, 0x48, 0x49, 0x58, 0x59,
0301         0x68, 0x69, 0x78, 0x79, 0x80, 0x81,
0302     };
0303     struct device_node *qe;
0304     const u8 *snum_init;
0305     int i;
0306
0307     bitmap_zero(snum_state, QE_NUM_OF_SNUM);
0308     qe_num_of_snum = 28; /* The default number of snum for threads is 28 */
0309     qe = qe_get_device_node();
0310     if (qe) {
0311         i = of_property_read_variable_u8_array(qe, "fsl,qe-snums",
0312                                snums, 1, QE_NUM_OF_SNUM);
0313         if (i > 0) {
0314             of_node_put(qe);
0315             qe_num_of_snum = i;
0316             return;
0317         }
0318         /*
0319          * Fall back to legacy binding of using the value of
0320          * fsl,qe-num-snums to choose one of the static arrays
0321          * above.
0322          */
0323         of_property_read_u32(qe, "fsl,qe-num-snums", &qe_num_of_snum);
0324         of_node_put(qe);
0325     }
0326
0327     if (qe_num_of_snum == 76) {
0328         snum_init = snum_init_76;
0329     } else if (qe_num_of_snum == 28 || qe_num_of_snum == 46) {
0330         snum_init = snum_init_46;
0331     } else {
0332         pr_err("QE: unsupported value of fsl,qe-num-snums: %u\n", qe_num_of_snum);
0333         return;
0334     }
0335     memcpy(snums, snum_init, qe_num_of_snum);
0336 }
0337
0338 int qe_get_snum(void)
0339 {
0340     unsigned long flags;
0341     int snum = -EBUSY;
0342     int i;
0343
0344     spin_lock_irqsave(&qe_lock, flags);
0345     i = find_first_zero_bit(snum_state, qe_num_of_snum);
0346     if (i < qe_num_of_snum) {
0347         set_bit(i, snum_state);
0348         snum = snums[i];
0349     }
0350     spin_unlock_irqrestore(&qe_lock, flags);
0351
0352     return snum;
0353 }
0354 EXPORT_SYMBOL(qe_get_snum);
0355
0356 void qe_put_snum(u8 snum)
0357 {
0358     const u8 *p = memchr(snums, snum, qe_num_of_snum);
0359
0360     if (p)
0361         clear_bit(p - snums, snum_state);
0362 }
0363 EXPORT_SYMBOL(qe_put_snum);
0364
0365 static int qe_sdma_init(void)
0366 {
0367     struct sdma __iomem *sdma = &qe_immr->sdma;
0368     static s32 sdma_buf_offset = -ENOMEM;
0369
0370     /* allocate 2 internal temporary buffers (512 bytes size each) for
0371      * the SDMA */
0372     if (sdma_buf_offset < 0) {
0373         sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
0374         if (sdma_buf_offset < 0)
0375             return -ENOMEM;
0376     }
0377
0378     iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
0379                &sdma->sdebcr);
0380     iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
0381                &sdma->sdmr);
0382
0383     return 0;
0384 }
0385
0386 /* The maximum number of RISCs we support */
0387 #define MAX_QE_RISC     4
0388
0389 /* Firmware information stored here for qe_get_firmware_info() */
0390 static struct qe_firmware_info qe_firmware_info;
0391
0392 /*
0393  * Set to 1 if QE firmware has been uploaded, and therefore
0394  * qe_firmware_info contains valid data.
0395  */
0396 static int qe_firmware_uploaded;
0397
0398 /*
0399  * Upload a QE microcode
0400  *
0401  * This function is a worker function for qe_upload_firmware().  It does
0402  * the actual uploading of the microcode.
0403  */
0404 static void qe_upload_microcode(const void *base,
0405     const struct qe_microcode *ucode)
0406 {
0407     const __be32 *code = base + be32_to_cpu(ucode->code_offset);
0408     unsigned int i;
0409
0410     if (ucode->major || ucode->minor || ucode->revision)
0411         printk(KERN_INFO "qe-firmware: "
0412             "uploading microcode '%s' version %u.%u.%u\n",
0413             ucode->id, ucode->major, ucode->minor, ucode->revision);
0414     else
0415         printk(KERN_INFO "qe-firmware: "
0416             "uploading microcode '%s'\n", ucode->id);
0417
0418     /* Use auto-increment */
0419     iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
0420                &qe_immr->iram.iadd);
0421
0422     for (i = 0; i < be32_to_cpu(ucode->count); i++)
0423         iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
0424
0425     /* Set I-RAM Ready Register */
0426     iowrite32be(QE_IRAM_READY, &qe_immr->iram.iready);
0427 }
0428
0429 /*
0430  * Upload a microcode to the I-RAM at a specific address.
0431  *
0432  * See Documentation/powerpc/qe_firmware.rst for information on QE microcode
0433  * uploading.
0434  *
0435  * Currently, only version 1 is supported, so the 'version' field must be
0436  * set to 1.
0437  *
0438  * The SOC model and revision are not validated, they are only displayed for
0439  * informational purposes.
0440  *
0441  * 'calc_size' is the calculated size, in bytes, of the firmware structure and
0442  * all of the microcode structures, minus the CRC.
0443  *
0444  * 'length' is the size that the structure says it is, including the CRC.
0445  */
0446 int qe_upload_firmware(const struct qe_firmware *firmware)
0447 {
0448     unsigned int i;
0449     unsigned int j;
0450     u32 crc;
0451     size_t calc_size;
0452     size_t length;
0453     const struct qe_header *hdr;
0454
0455     if (!firmware) {
0456         printk(KERN_ERR "qe-firmware: invalid pointer\n");
0457         return -EINVAL;
0458     }
0459
0460     hdr = &firmware->header;
0461     length = be32_to_cpu(hdr->length);
0462
0463     /* Check the magic */
0464     if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
0465         (hdr->magic[2] != 'F')) {
0466         printk(KERN_ERR "qe-firmware: not a microcode\n");
0467         return -EPERM;
0468     }
0469
0470     /* Check the version */
0471     if (hdr->version != 1) {
0472         printk(KERN_ERR "qe-firmware: unsupported version\n");
0473         return -EPERM;
0474     }
0475
0476     /* Validate some of the fields */
0477     if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
0478         printk(KERN_ERR "qe-firmware: invalid data\n");
0479         return -EINVAL;
0480     }
0481
0482     /* Validate the length and check if there's a CRC */
0483     calc_size = struct_size(firmware, microcode, firmware->count);
0484
0485     for (i = 0; i < firmware->count; i++)
0486         /*
0487          * For situations where the second RISC uses the same microcode
0488          * as the first, the 'code_offset' and 'count' fields will be
0489          * zero, so it's okay to add those.
0490          */
0491         calc_size += sizeof(__be32) *
0492             be32_to_cpu(firmware->microcode[i].count);
0493
0494     /* Validate the length */
0495     if (length != calc_size + sizeof(__be32)) {
0496         printk(KERN_ERR "qe-firmware: invalid length\n");
0497         return -EPERM;
0498     }
0499
0500     /* Validate the CRC */
0501     crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
0502     if (crc != crc32(0, firmware, calc_size)) {
0503         printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
0504         return -EIO;
0505     }
0506
0507     /*
0508      * If the microcode calls for it, split the I-RAM.
0509      */
0510     if (!firmware->split)
0511         qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
0512
0513     if (firmware->soc.model)
0514         printk(KERN_INFO
0515             "qe-firmware: firmware '%s' for %u V%u.%u\n",
0516             firmware->id, be16_to_cpu(firmware->soc.model),
0517             firmware->soc.major, firmware->soc.minor);
0518     else
0519         printk(KERN_INFO "qe-firmware: firmware '%s'\n",
0520             firmware->id);
0521
0522     /*
0523      * The QE only supports one microcode per RISC, so clear out all the
0524      * saved microcode information and put in the new.
0525      */
0526     memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
0527     strlcpy(qe_firmware_info.id, firmware->id, sizeof(qe_firmware_info.id));
0528     qe_firmware_info.extended_modes = be64_to_cpu(firmware->extended_modes);
0529     memcpy(qe_firmware_info.vtraps, firmware->vtraps,
0530         sizeof(firmware->vtraps));
0531
0532     /* Loop through each microcode. */
0533     for (i = 0; i < firmware->count; i++) {
0534         const struct qe_microcode *ucode = &firmware->microcode[i];
0535
0536         /* Upload a microcode if it's present */
0537         if (ucode->code_offset)
0538             qe_upload_microcode(firmware, ucode);
0539
0540         /* Program the traps for this processor */
0541         for (j = 0; j < 16; j++) {
0542             u32 trap = be32_to_cpu(ucode->traps[j]);
0543
0544             if (trap)
0545                 iowrite32be(trap,
0546                            &qe_immr->rsp[i].tibcr[j]);
0547         }
0548
0549         /* Enable traps */
0550         iowrite32be(be32_to_cpu(ucode->eccr),
0551                    &qe_immr->rsp[i].eccr);
0552     }
0553
0554     qe_firmware_uploaded = 1;
0555
0556     return 0;
0557 }
0558 EXPORT_SYMBOL(qe_upload_firmware);
0559
0560 /*
0561  * Get info on the currently-loaded firmware
0562  *
0563  * This function also checks the device tree to see if the boot loader has
0564  * uploaded a firmware already.
0565  */
0566 struct qe_firmware_info *qe_get_firmware_info(void)
0567 {
0568     static int initialized;
0569     struct device_node *qe;
0570     struct device_node *fw = NULL;
0571     const char *sprop;
0572
0573     /*
0574      * If we haven't checked yet, and a driver hasn't uploaded a firmware
0575      * yet, then check the device tree for information.
0576      */
0577     if (qe_firmware_uploaded)
0578         return &qe_firmware_info;
0579
0580     if (initialized)
0581         return NULL;
0582
0583     initialized = 1;
0584
0585     qe = qe_get_device_node();
0586     if (!qe)
0587         return NULL;
0588
0589     /* Find the 'firmware' child node */
0590     fw = of_get_child_by_name(qe, "firmware");
0591     of_node_put(qe);
0592
0593     /* Did we find the 'firmware' node? */
0594     if (!fw)
0595         return NULL;
0596
0597     qe_firmware_uploaded = 1;
0598
0599     /* Copy the data into qe_firmware_info*/
0600     sprop = of_get_property(fw, "id", NULL);
0601     if (sprop)
0602         strlcpy(qe_firmware_info.id, sprop,
0603             sizeof(qe_firmware_info.id));
0604
0605     of_property_read_u64(fw, "extended-modes",
0606                  &qe_firmware_info.extended_modes);
0607
0608     of_property_read_u32_array(fw, "virtual-traps", qe_firmware_info.vtraps,
0609                    ARRAY_SIZE(qe_firmware_info.vtraps));
0610
0611     of_node_put(fw);
0612
0613     return &qe_firmware_info;
0614 }
0615 EXPORT_SYMBOL(qe_get_firmware_info);
0616
0617 unsigned int qe_get_num_of_risc(void)
0618 {
0619     struct device_node *qe;
0620     unsigned int num_of_risc = 0;
0621
0622     qe = qe_get_device_node();
0623     if (!qe)
0624         return num_of_risc;
0625
0626     of_property_read_u32(qe, "fsl,qe-num-riscs", &num_of_risc);
0627
0628     of_node_put(qe);
0629
0630     return num_of_risc;
0631 }
0632 EXPORT_SYMBOL(qe_get_num_of_risc);
0633
0634 unsigned int qe_get_num_of_snums(void)
0635 {
0636     return qe_num_of_snum;
0637 }
0638 EXPORT_SYMBOL(qe_get_num_of_snums);
0639
0640 static int __init qe_init(void)
0641 {
0642     struct device_node *np;
0643
0644     np = of_find_compatible_node(NULL, NULL, "fsl,qe");
0645     if (!np)
0646         return -ENODEV;
0647     qe_reset();
0648     of_node_put(np);
0649     return 0;
0650 }
0651 subsys_initcall(qe_init);
0652
0653 #if defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx)
0654 static int qe_resume(struct platform_device *ofdev)
0655 {
0656     if (!qe_alive_during_sleep())
0657         qe_reset();
0658     return 0;
0659 }
0660
0661 static int qe_probe(struct platform_device *ofdev)
0662 {
0663     return 0;
0664 }
0665
0666 static const struct of_device_id qe_ids[] = {
0667     { .compatible = "fsl,qe", },
0668     { },
0669 };
0670
0671 static struct platform_driver qe_driver = {
0672     .driver = {
0673         .name = "fsl-qe",
0674         .of_match_table = qe_ids,
0675     },
0676     .probe = qe_probe,
0677     .resume = qe_resume,
0678 };
0679
0680 builtin_platform_driver(qe_driver);
0681 #endif /* defined(CONFIG_SUSPEND) && defined(CONFIG_PPC_85xx) */