fsl/qe/gpio.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * QUICC Engine GPIOs
0004  *
0005  * Copyright (c) MontaVista Software, Inc. 2008.
0006  *
0007  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/init.h>
0012 #include <linux/spinlock.h>
0013 #include <linux/err.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_gpio.h>
0017 #include <linux/gpio/driver.h>
0018 /* FIXME: needed for gpio_to_chip() get rid of this */
0019 #include <linux/gpio.h>
0020 #include <linux/slab.h>
0021 #include <linux/export.h>
0022 #include <soc/fsl/qe/qe.h>
0023
0024 struct qe_gpio_chip {
0025     struct of_mm_gpio_chip mm_gc;
0026     spinlock_t lock;
0027
0028     unsigned long pin_flags[QE_PIO_PINS];
0029 #define QE_PIN_REQUESTED 0
0030
0031     /* shadowed data register to clear/set bits safely */
0032     u32 cpdata;
0033
0034     /* saved_regs used to restore dedicated functions */
0035     struct qe_pio_regs saved_regs;
0036 };
0037
0038 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
0039 {
0040     struct qe_gpio_chip *qe_gc =
0041         container_of(mm_gc, struct qe_gpio_chip, mm_gc);
0042     struct qe_pio_regs __iomem *regs = mm_gc->regs;
0043
0044     qe_gc->cpdata = ioread32be(&regs->cpdata);
0045     qe_gc->saved_regs.cpdata = qe_gc->cpdata;
0046     qe_gc->saved_regs.cpdir1 = ioread32be(&regs->cpdir1);
0047     qe_gc->saved_regs.cpdir2 = ioread32be(&regs->cpdir2);
0048     qe_gc->saved_regs.cppar1 = ioread32be(&regs->cppar1);
0049     qe_gc->saved_regs.cppar2 = ioread32be(&regs->cppar2);
0050     qe_gc->saved_regs.cpodr = ioread32be(&regs->cpodr);
0051 }
0052
0053 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
0054 {
0055     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0056     struct qe_pio_regs __iomem *regs = mm_gc->regs;
0057     u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
0058
0059     return !!(ioread32be(&regs->cpdata) & pin_mask);
0060 }
0061
0062 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
0063 {
0064     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0065     struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
0066     struct qe_pio_regs __iomem *regs = mm_gc->regs;
0067     unsigned long flags;
0068     u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
0069
0070     spin_lock_irqsave(&qe_gc->lock, flags);
0071
0072     if (val)
0073         qe_gc->cpdata |= pin_mask;
0074     else
0075         qe_gc->cpdata &= ~pin_mask;
0076
0077     iowrite32be(qe_gc->cpdata, &regs->cpdata);
0078
0079     spin_unlock_irqrestore(&qe_gc->lock, flags);
0080 }
0081
0082 static void qe_gpio_set_multiple(struct gpio_chip *gc,
0083                  unsigned long *mask, unsigned long *bits)
0084 {
0085     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0086     struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
0087     struct qe_pio_regs __iomem *regs = mm_gc->regs;
0088     unsigned long flags;
0089     int i;
0090
0091     spin_lock_irqsave(&qe_gc->lock, flags);
0092
0093     for (i = 0; i < gc->ngpio; i++) {
0094         if (*mask == 0)
0095             break;
0096         if (__test_and_clear_bit(i, mask)) {
0097             if (test_bit(i, bits))
0098                 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
0099             else
0100                 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
0101         }
0102     }
0103
0104     iowrite32be(qe_gc->cpdata, &regs->cpdata);
0105
0106     spin_unlock_irqrestore(&qe_gc->lock, flags);
0107 }
0108
0109 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
0110 {
0111     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0112     struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
0113     unsigned long flags;
0114
0115     spin_lock_irqsave(&qe_gc->lock, flags);
0116
0117     __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
0118
0119     spin_unlock_irqrestore(&qe_gc->lock, flags);
0120
0121     return 0;
0122 }
0123
0124 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
0125 {
0126     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0127     struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
0128     unsigned long flags;
0129
0130     qe_gpio_set(gc, gpio, val);
0131
0132     spin_lock_irqsave(&qe_gc->lock, flags);
0133
0134     __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
0135
0136     spin_unlock_irqrestore(&qe_gc->lock, flags);
0137
0138     return 0;
0139 }
0140
0141 struct qe_pin {
0142     /*
0143      * The qe_gpio_chip name is unfortunate, we should change that to
0144      * something like qe_pio_controller. Someday.
0145      */
0146     struct qe_gpio_chip *controller;
0147     int num;
0148 };
0149
0150 /**
0151  * qe_pin_request - Request a QE pin
0152  * @np:     device node to get a pin from
0153  * @index:  index of a pin in the device tree
0154  * Context: non-atomic
0155  *
0156  * This function return qe_pin so that you could use it with the rest of
0157  * the QE Pin Multiplexing API.
0158  */
0159 struct qe_pin *qe_pin_request(struct device_node *np, int index)
0160 {
0161     struct qe_pin *qe_pin;
0162     struct gpio_chip *gc;
0163     struct qe_gpio_chip *qe_gc;
0164     int err;
0165     unsigned long flags;
0166
0167     qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
0168     if (!qe_pin) {
0169         pr_debug("%s: can't allocate memory\n", __func__);
0170         return ERR_PTR(-ENOMEM);
0171     }
0172
0173     err = of_get_gpio(np, index);
0174     if (err < 0)
0175         goto err0;
0176     gc = gpio_to_chip(err);
0177     if (WARN_ON(!gc)) {
0178         err = -ENODEV;
0179         goto err0;
0180     }
0181
0182     if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
0183         pr_debug("%s: tried to get a non-qe pin\n", __func__);
0184         err = -EINVAL;
0185         goto err0;
0186     }
0187
0188     qe_gc = gpiochip_get_data(gc);
0189
0190     spin_lock_irqsave(&qe_gc->lock, flags);
0191
0192     err -= gc->base;
0193     if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
0194         qe_pin->controller = qe_gc;
0195         qe_pin->num = err;
0196         err = 0;
0197     } else {
0198         err = -EBUSY;
0199     }
0200
0201     spin_unlock_irqrestore(&qe_gc->lock, flags);
0202
0203     if (!err)
0204         return qe_pin;
0205 err0:
0206     kfree(qe_pin);
0207     pr_debug("%s failed with status %d\n", __func__, err);
0208     return ERR_PTR(err);
0209 }
0210 EXPORT_SYMBOL(qe_pin_request);
0211
0212 /**
0213  * qe_pin_free - Free a pin
0214  * @qe_pin: pointer to the qe_pin structure
0215  * Context: any
0216  *
0217  * This function frees the qe_pin structure and makes a pin available
0218  * for further qe_pin_request() calls.
0219  */
0220 void qe_pin_free(struct qe_pin *qe_pin)
0221 {
0222     struct qe_gpio_chip *qe_gc = qe_pin->controller;
0223     unsigned long flags;
0224     const int pin = qe_pin->num;
0225
0226     spin_lock_irqsave(&qe_gc->lock, flags);
0227     test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
0228     spin_unlock_irqrestore(&qe_gc->lock, flags);
0229
0230     kfree(qe_pin);
0231 }
0232 EXPORT_SYMBOL(qe_pin_free);
0233
0234 /**
0235  * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
0236  * @qe_pin: pointer to the qe_pin structure
0237  * Context: any
0238  *
0239  * This function resets a pin to a dedicated peripheral function that
0240  * has been set up by the firmware.
0241  */
0242 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
0243 {
0244     struct qe_gpio_chip *qe_gc = qe_pin->controller;
0245     struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
0246     struct qe_pio_regs *sregs = &qe_gc->saved_regs;
0247     int pin = qe_pin->num;
0248     u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
0249     u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
0250     bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
0251     unsigned long flags;
0252
0253     spin_lock_irqsave(&qe_gc->lock, flags);
0254
0255     if (second_reg) {
0256         qe_clrsetbits_be32(&regs->cpdir2, mask2,
0257                    sregs->cpdir2 & mask2);
0258         qe_clrsetbits_be32(&regs->cppar2, mask2,
0259                    sregs->cppar2 & mask2);
0260     } else {
0261         qe_clrsetbits_be32(&regs->cpdir1, mask2,
0262                    sregs->cpdir1 & mask2);
0263         qe_clrsetbits_be32(&regs->cppar1, mask2,
0264                    sregs->cppar1 & mask2);
0265     }
0266
0267     if (sregs->cpdata & mask1)
0268         qe_gc->cpdata |= mask1;
0269     else
0270         qe_gc->cpdata &= ~mask1;
0271
0272     iowrite32be(qe_gc->cpdata, &regs->cpdata);
0273     qe_clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
0274
0275     spin_unlock_irqrestore(&qe_gc->lock, flags);
0276 }
0277 EXPORT_SYMBOL(qe_pin_set_dedicated);
0278
0279 /**
0280  * qe_pin_set_gpio - Set a pin to the GPIO mode
0281  * @qe_pin: pointer to the qe_pin structure
0282  * Context: any
0283  *
0284  * This function sets a pin to the GPIO mode.
0285  */
0286 void qe_pin_set_gpio(struct qe_pin *qe_pin)
0287 {
0288     struct qe_gpio_chip *qe_gc = qe_pin->controller;
0289     struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
0290     unsigned long flags;
0291
0292     spin_lock_irqsave(&qe_gc->lock, flags);
0293
0294     /* Let's make it input by default, GPIO API is able to change that. */
0295     __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
0296
0297     spin_unlock_irqrestore(&qe_gc->lock, flags);
0298 }
0299 EXPORT_SYMBOL(qe_pin_set_gpio);
0300
0301 static int __init qe_add_gpiochips(void)
0302 {
0303     struct device_node *np;
0304
0305     for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
0306         int ret;
0307         struct qe_gpio_chip *qe_gc;
0308         struct of_mm_gpio_chip *mm_gc;
0309         struct gpio_chip *gc;
0310
0311         qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
0312         if (!qe_gc) {
0313             ret = -ENOMEM;
0314             goto err;
0315         }
0316
0317         spin_lock_init(&qe_gc->lock);
0318
0319         mm_gc = &qe_gc->mm_gc;
0320         gc = &mm_gc->gc;
0321
0322         mm_gc->save_regs = qe_gpio_save_regs;
0323         gc->ngpio = QE_PIO_PINS;
0324         gc->direction_input = qe_gpio_dir_in;
0325         gc->direction_output = qe_gpio_dir_out;
0326         gc->get = qe_gpio_get;
0327         gc->set = qe_gpio_set;
0328         gc->set_multiple = qe_gpio_set_multiple;
0329
0330         ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
0331         if (ret)
0332             goto err;
0333         continue;
0334 err:
0335         pr_err("%pOF: registration failed with status %d\n",
0336                np, ret);
0337         kfree(qe_gc);
0338         /* try others anyway */
0339     }
0340     return 0;
0341 }
0342 arch_initcall(qe_add_gpiochips);