fsl/qbman/qman_priv.h

0001 /* Copyright 2008 - 2016 Freescale Semiconductor, Inc.
0002  *
0003  * Redistribution and use in source and binary forms, with or without
0004  * modification, are permitted provided that the following conditions are met:
0005  *     * Redistributions of source code must retain the above copyright
0006  *   notice, this list of conditions and the following disclaimer.
0007  *     * Redistributions in binary form must reproduce the above copyright
0008  *   notice, this list of conditions and the following disclaimer in the
0009  *   documentation and/or other materials provided with the distribution.
0010  *     * Neither the name of Freescale Semiconductor nor the
0011  *   names of its contributors may be used to endorse or promote products
0012  *   derived from this software without specific prior written permission.
0013  *
0014  * ALTERNATIVELY, this software may be distributed under the terms of the
0015  * GNU General Public License ("GPL") as published by the Free Software
0016  * Foundation, either version 2 of that License or (at your option) any
0017  * later version.
0018  *
0019  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
0020  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
0021  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
0022  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
0023  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
0024  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
0025  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0026  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
0027  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
0028  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0029  */
0030
0031 #include "dpaa_sys.h"
0032
0033 #include <soc/fsl/qman.h>
0034 #include <linux/dma-mapping.h>
0035 #include <linux/iommu.h>
0036
0037 #if defined(CONFIG_FSL_PAMU)
0038 #include <asm/fsl_pamu_stash.h>
0039 #endif
0040
0041 struct qm_mcr_querywq {
0042     u8 verb;
0043     u8 result;
0044     u16 channel_wq; /* ignores wq (3 lsbits): _res[0-2] */
0045     u8 __reserved[28];
0046     u32 wq_len[8];
0047 } __packed;
0048
0049 static inline u16 qm_mcr_querywq_get_chan(const struct qm_mcr_querywq *wq)
0050 {
0051     return wq->channel_wq >> 3;
0052 }
0053
0054 struct __qm_mcr_querycongestion {
0055     u32 state[8];
0056 };
0057
0058 /* "Query Congestion Group State" */
0059 struct qm_mcr_querycongestion {
0060     u8 verb;
0061     u8 result;
0062     u8 __reserved[30];
0063     /* Access this struct using qman_cgrs_get() */
0064     struct __qm_mcr_querycongestion state;
0065 } __packed;
0066
0067 /* "Query CGR" */
0068 struct qm_mcr_querycgr {
0069     u8 verb;
0070     u8 result;
0071     u16 __reserved1;
0072     struct __qm_mc_cgr cgr; /* CGR fields */
0073     u8 __reserved2[6];
0074     u8 i_bcnt_hi;   /* high 8-bits of 40-bit "Instant" */
0075     __be32 i_bcnt_lo;   /* low 32-bits of 40-bit */
0076     u8 __reserved3[3];
0077     u8 a_bcnt_hi;   /* high 8-bits of 40-bit "Average" */
0078     __be32 a_bcnt_lo;   /* low 32-bits of 40-bit */
0079     __be32 cscn_targ_swp[4];
0080 } __packed;
0081
0082 static inline u64 qm_mcr_querycgr_i_get64(const struct qm_mcr_querycgr *q)
0083 {
0084     return ((u64)q->i_bcnt_hi << 32) | be32_to_cpu(q->i_bcnt_lo);
0085 }
0086 static inline u64 qm_mcr_querycgr_a_get64(const struct qm_mcr_querycgr *q)
0087 {
0088     return ((u64)q->a_bcnt_hi << 32) | be32_to_cpu(q->a_bcnt_lo);
0089 }
0090
0091 /* Congestion Groups */
0092
0093 /*
0094  * This wrapper represents a bit-array for the state of the 256 QMan congestion
0095  * groups. Is also used as a *mask* for congestion groups, eg. so we ignore
0096  * those that don't concern us. We harness the structure and accessor details
0097  * already used in the management command to query congestion groups.
0098  */
0099 #define CGR_BITS_PER_WORD 5
0100 #define CGR_WORD(x) ((x) >> CGR_BITS_PER_WORD)
0101 #define CGR_BIT(x)  (BIT(31) >> ((x) & 0x1f))
0102 #define CGR_NUM (sizeof(struct __qm_mcr_querycongestion) << 3)
0103
0104 struct qman_cgrs {
0105     struct __qm_mcr_querycongestion q;
0106 };
0107
0108 static inline void qman_cgrs_init(struct qman_cgrs *c)
0109 {
0110     memset(c, 0, sizeof(*c));
0111 }
0112
0113 static inline void qman_cgrs_fill(struct qman_cgrs *c)
0114 {
0115     memset(c, 0xff, sizeof(*c));
0116 }
0117
0118 static inline int qman_cgrs_get(struct qman_cgrs *c, u8 cgr)
0119 {
0120     return c->q.state[CGR_WORD(cgr)] & CGR_BIT(cgr);
0121 }
0122
0123 static inline void qman_cgrs_cp(struct qman_cgrs *dest,
0124                 const struct qman_cgrs *src)
0125 {
0126     *dest = *src;
0127 }
0128
0129 static inline void qman_cgrs_and(struct qman_cgrs *dest,
0130             const struct qman_cgrs *a, const struct qman_cgrs *b)
0131 {
0132     int ret;
0133     u32 *_d = dest->q.state;
0134     const u32 *_a = a->q.state;
0135     const u32 *_b = b->q.state;
0136
0137     for (ret = 0; ret < 8; ret++)
0138         *_d++ = *_a++ & *_b++;
0139 }
0140
0141 static inline void qman_cgrs_xor(struct qman_cgrs *dest,
0142             const struct qman_cgrs *a, const struct qman_cgrs *b)
0143 {
0144     int ret;
0145     u32 *_d = dest->q.state;
0146     const u32 *_a = a->q.state;
0147     const u32 *_b = b->q.state;
0148
0149     for (ret = 0; ret < 8; ret++)
0150         *_d++ = *_a++ ^ *_b++;
0151 }
0152
0153 void qman_init_cgr_all(void);
0154
0155 struct qm_portal_config {
0156     /* Portal addresses */
0157     void *addr_virt_ce;
0158     void __iomem *addr_virt_ci;
0159     struct device *dev;
0160     struct iommu_domain *iommu_domain;
0161     /* Allow these to be joined in lists */
0162     struct list_head list;
0163     /* User-visible portal configuration settings */
0164     /* portal is affined to this cpu */
0165     int cpu;
0166     /* portal interrupt line */
0167     int irq;
0168     /*
0169      * the portal's dedicated channel id, used initialising
0170      * frame queues to target this portal when scheduled
0171      */
0172     u16 channel;
0173     /*
0174      * mask of pool channels this portal has dequeue access to
0175      * (using QM_SDQCR_CHANNELS_POOL(n) for the bitmask)
0176      */
0177     u32 pools;
0178 };
0179
0180 /* Revision info (for errata and feature handling) */
0181 #define QMAN_REV11 0x0101
0182 #define QMAN_REV12 0x0102
0183 #define QMAN_REV20 0x0200
0184 #define QMAN_REV30 0x0300
0185 #define QMAN_REV31 0x0301
0186 #define QMAN_REV32 0x0302
0187 extern u16 qman_ip_rev; /* 0 if uninitialised, otherwise QMAN_REVx */
0188
0189 #define QM_FQID_RANGE_START 1 /* FQID 0 reserved for internal use */
0190 extern struct gen_pool *qm_fqalloc; /* FQID allocator */
0191 extern struct gen_pool *qm_qpalloc; /* pool-channel allocator */
0192 extern struct gen_pool *qm_cgralloc; /* CGR ID allocator */
0193 u32 qm_get_pools_sdqcr(void);
0194
0195 int qman_wq_alloc(void);
0196 #ifdef CONFIG_FSL_PAMU
0197 #define qman_liodn_fixup __qman_liodn_fixup
0198 #else
0199 static inline void qman_liodn_fixup(u16 channel)
0200 {
0201 }
0202 #endif
0203 void __qman_liodn_fixup(u16 channel);
0204 void qman_set_sdest(u16 channel, unsigned int cpu_idx);
0205
0206 struct qman_portal *qman_create_affine_portal(
0207             const struct qm_portal_config *config,
0208             const struct qman_cgrs *cgrs);
0209 const struct qm_portal_config *qman_destroy_affine_portal(void);
0210
0211 /*
0212  * qman_query_fq - Queries FQD fields (via h/w query command)
0213  * @fq: the frame queue object to be queried
0214  * @fqd: storage for the queried FQD fields
0215  */
0216 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
0217
0218 int qman_alloc_fq_table(u32 num_fqids);
0219
0220 /*   QMan s/w corenet portal, low-level i/face   */
0221
0222 /*
0223  * For qm_dqrr_sdqcr_set(); Choose one SOURCE. Choose one COUNT. Choose one
0224  * dequeue TYPE. Choose TOKEN (8-bit).
0225  * If SOURCE == CHANNELS,
0226  *   Choose CHANNELS_DEDICATED and/or CHANNELS_POOL(n).
0227  *   You can choose DEDICATED_PRECEDENCE if the portal channel should have
0228  *   priority.
0229  * If SOURCE == SPECIFICWQ,
0230  *     Either select the work-queue ID with SPECIFICWQ_WQ(), or select the
0231  *     channel (SPECIFICWQ_DEDICATED or SPECIFICWQ_POOL()) and specify the
0232  *     work-queue priority (0-7) with SPECIFICWQ_WQ() - either way, you get the
0233  *     same value.
0234  */
0235 #define QM_SDQCR_SOURCE_CHANNELS    0x0
0236 #define QM_SDQCR_SOURCE_SPECIFICWQ  0x40000000
0237 #define QM_SDQCR_COUNT_EXACT1       0x0
0238 #define QM_SDQCR_COUNT_UPTO3        0x20000000
0239 #define QM_SDQCR_DEDICATED_PRECEDENCE   0x10000000
0240 #define QM_SDQCR_TYPE_MASK      0x03000000
0241 #define QM_SDQCR_TYPE_NULL      0x0
0242 #define QM_SDQCR_TYPE_PRIO_QOS      0x01000000
0243 #define QM_SDQCR_TYPE_ACTIVE_QOS    0x02000000
0244 #define QM_SDQCR_TYPE_ACTIVE        0x03000000
0245 #define QM_SDQCR_TOKEN_MASK     0x00ff0000
0246 #define QM_SDQCR_TOKEN_SET(v)       (((v) & 0xff) << 16)
0247 #define QM_SDQCR_TOKEN_GET(v)       (((v) >> 16) & 0xff)
0248 #define QM_SDQCR_CHANNELS_DEDICATED 0x00008000
0249 #define QM_SDQCR_SPECIFICWQ_MASK    0x000000f7
0250 #define QM_SDQCR_SPECIFICWQ_DEDICATED   0x00000000
0251 #define QM_SDQCR_SPECIFICWQ_POOL(n) ((n) << 4)
0252 #define QM_SDQCR_SPECIFICWQ_WQ(n)   (n)
0253
0254 /* For qm_dqrr_vdqcr_set(): use FQID(n) to fill in the frame queue ID */
0255 #define QM_VDQCR_FQID_MASK      0x00ffffff
0256 #define QM_VDQCR_FQID(n)        ((n) & QM_VDQCR_FQID_MASK)
0257
0258 /*
0259  * Used by all portal interrupt registers except 'inhibit'
0260  * Channels with frame availability
0261  */
0262 #define QM_PIRQ_DQAVAIL 0x0000ffff
0263
0264 /* The DQAVAIL interrupt fields break down into these bits; */
0265 #define QM_DQAVAIL_PORTAL   0x8000      /* Portal channel */
0266 #define QM_DQAVAIL_POOL(n)  (0x8000 >> (n)) /* Pool channel, n==[1..15] */
0267 #define QM_DQAVAIL_MASK     0xffff
0268 /* This mask contains all the "irqsource" bits visible to API users */
0269 #define QM_PIRQ_VISIBLE (QM_PIRQ_SLOW | QM_PIRQ_DQRI)
0270
0271 extern struct qman_portal *affine_portals[NR_CPUS];
0272 extern struct qman_portal *qman_dma_portal;
0273 const struct qm_portal_config *qman_get_qm_portal_config(
0274                         struct qman_portal *portal);
0275
0276 unsigned int qm_get_fqid_maxcnt(void);
0277
0278 int qman_shutdown_fq(u32 fqid);
0279
0280 int qman_requires_cleanup(void);
0281 void qman_done_cleanup(void);
0282 void qman_enable_irqs(void);