brcmstb/pm/s2-arm.S

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright © 2014-2017 Broadcom
0004  */
0005
0006 #include <linux/linkage.h>
0007 #include <asm/assembler.h>
0008
0009 #include "pm.h"
0010
0011     .text
0012     .align  3
0013
0014 #define AON_CTRL_REG        r10
0015 #define DDR_PHY_STATUS_REG  r11
0016
0017 /*
0018  * r0: AON_CTRL base address
0019  * r1: DDRY PHY PLL status register address
0020  */
0021 ENTRY(brcmstb_pm_do_s2)
0022     stmfd   sp!, {r4-r11, lr}
0023     mov AON_CTRL_REG, r0
0024     mov DDR_PHY_STATUS_REG, r1
0025
0026     /* Flush memory transactions */
0027     dsb
0028
0029     /* Cache DDR_PHY_STATUS_REG translation */
0030     ldr r0, [DDR_PHY_STATUS_REG]
0031
0032     /* power down request */
0033     ldr r0, =PM_S2_COMMAND
0034     ldr r1, =0
0035     str r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
0036     ldr r1, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
0037     str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
0038     ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
0039
0040     /* Wait for interrupt */
0041     wfi
0042     nop
0043
0044     /* Bring MEMC back up */
0045 1:  ldr r0, [DDR_PHY_STATUS_REG]
0046     ands    r0, #1
0047     beq 1b
0048
0049     /* Power-up handshake */
0050     ldr r0, =1
0051     str r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
0052     ldr r0, [AON_CTRL_REG, #AON_CTRL_HOST_MISC_CMDS]
0053
0054     ldr r0, =0
0055     str r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
0056     ldr r0, [AON_CTRL_REG, #AON_CTRL_PM_CTRL]
0057
0058     /* Return to caller */
0059     ldr r0, =0
0060     ldmfd   sp!, {r4-r11, pc}
0061
0062     ENDPROC(brcmstb_pm_do_s2)
0063
0064     /* Place literal pool here */
0065     .ltorg
0066
0067 ENTRY(brcmstb_pm_do_s2_sz)
0068     .word   . - brcmstb_pm_do_s2