brcmstb/pm/pm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Definitions for Broadcom STB power management / Always ON (AON) block
0004  *
0005  * Copyright © 2016-2017 Broadcom
0006  */
0007
0008 #ifndef __BRCMSTB_PM_H__
0009 #define __BRCMSTB_PM_H__
0010
0011 #define AON_CTRL_RESET_CTRL     0x00
0012 #define AON_CTRL_PM_CTRL        0x04
0013 #define AON_CTRL_PM_STATUS      0x08
0014 #define AON_CTRL_PM_CPU_WAIT_COUNT  0x10
0015 #define AON_CTRL_PM_INITIATE        0x88
0016 #define AON_CTRL_HOST_MISC_CMDS     0x8c
0017 #define AON_CTRL_SYSTEM_DATA_RAM_OFS    0x200
0018
0019 /* MIPS PM constants */
0020 /* MEMC0 offsets */
0021 #define DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x10
0022 #define DDR40_PHY_CONTROL_REGS_0_STANDBY_CTRL   0xa4
0023
0024 /* TIMER offsets */
0025 #define TIMER_TIMER1_CTRL       0x0c
0026 #define TIMER_TIMER1_STAT       0x1c
0027
0028 /* TIMER defines */
0029 #define RESET_TIMER         0x0
0030 #define START_TIMER         0xbfffffff
0031 #define TIMER_MASK          0x3fffffff
0032
0033 /* PM_CTRL bitfield (Method #0) */
0034 #define PM_FAST_PWRDOWN         (1 << 6)
0035 #define PM_WARM_BOOT            (1 << 5)
0036 #define PM_DEEP_STANDBY         (1 << 4)
0037 #define PM_CPU_PWR          (1 << 3)
0038 #define PM_USE_CPU_RDY          (1 << 2)
0039 #define PM_PLL_PWRDOWN          (1 << 1)
0040 #define PM_PWR_DOWN         (1 << 0)
0041
0042 /* PM_CTRL bitfield (Method #1) */
0043 #define PM_DPHY_STANDBY_CLEAR       (1 << 20)
0044 #define PM_MIN_S3_WIDTH_TIMER_BYPASS    (1 << 7)
0045
0046 #define PM_S2_COMMAND   (PM_PLL_PWRDOWN | PM_USE_CPU_RDY | PM_PWR_DOWN)
0047
0048 /* Method 0 bitmasks */
0049 #define PM_COLD_CONFIG  (PM_PLL_PWRDOWN | PM_DEEP_STANDBY)
0050 #define PM_WARM_CONFIG  (PM_COLD_CONFIG | PM_USE_CPU_RDY | PM_WARM_BOOT)
0051
0052 /* Method 1 bitmask */
0053 #define M1_PM_WARM_CONFIG (PM_DPHY_STANDBY_CLEAR | \
0054                PM_MIN_S3_WIDTH_TIMER_BYPASS | \
0055                PM_WARM_BOOT | PM_DEEP_STANDBY | \
0056                PM_PLL_PWRDOWN | PM_PWR_DOWN)
0057
0058 #define M1_PM_COLD_CONFIG (PM_DPHY_STANDBY_CLEAR | \
0059                PM_MIN_S3_WIDTH_TIMER_BYPASS | \
0060                PM_DEEP_STANDBY | \
0061                PM_PLL_PWRDOWN | PM_PWR_DOWN)
0062
0063 #ifndef __ASSEMBLY__
0064
0065 #ifndef CONFIG_MIPS
0066 extern const unsigned long brcmstb_pm_do_s2_sz;
0067 extern asmlinkage int brcmstb_pm_do_s2(void __iomem *aon_ctrl_base,
0068         void __iomem *ddr_phy_pll_status);
0069 #else
0070 /* s2 asm */
0071 extern asmlinkage int brcm_pm_do_s2(u32 *s2_params);
0072
0073 /* s3 asm */
0074 extern asmlinkage int brcm_pm_do_s3(void __iomem *aon_ctrl_base,
0075         int dcache_linesz);
0076 extern int s3_reentry;
0077 #endif /* CONFIG_MIPS */
0078
0079 #endif
0080
0081 #endif /* __BRCMSTB_PM_H__ */