soc/atmel/soc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2015 Atmel
0004  *
0005  * Alexandre Belloni <alexandre.belloni@free-electrons.com
0006  * Boris Brezillon <boris.brezillon@free-electrons.com
0007  */
0008
0009 #define pr_fmt(fmt) "AT91: " fmt
0010
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/slab.h>
0016 #include <linux/sys_soc.h>
0017
0018 #include "soc.h"
0019
0020 #define AT91_DBGU_CIDR          0x40
0021 #define AT91_DBGU_EXID          0x44
0022 #define AT91_CHIPID_CIDR        0x00
0023 #define AT91_CHIPID_EXID        0x04
0024 #define AT91_CIDR_VERSION(x, m)     ((x) & (m))
0025 #define AT91_CIDR_VERSION_MASK      GENMASK(4, 0)
0026 #define AT91_CIDR_VERSION_MASK_SAMA7G5  GENMASK(3, 0)
0027 #define AT91_CIDR_EXT           BIT(31)
0028 #define AT91_CIDR_MATCH_MASK        GENMASK(30, 5)
0029 #define AT91_CIDR_MASK_SAMA7G5      GENMASK(27, 5)
0030
0031 static const struct at91_soc socs[] __initconst = {
0032 #ifdef CONFIG_SOC_AT91RM9200
0033     AT91_SOC(AT91RM9200_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0034          AT91_CIDR_VERSION_MASK, 0, "at91rm9200 BGA", "at91rm9200"),
0035 #endif
0036 #ifdef CONFIG_SOC_AT91SAM9
0037     AT91_SOC(AT91SAM9260_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0038          AT91_CIDR_VERSION_MASK, 0, "at91sam9260", NULL),
0039     AT91_SOC(AT91SAM9261_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0040          AT91_CIDR_VERSION_MASK, 0, "at91sam9261", NULL),
0041     AT91_SOC(AT91SAM9263_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0042          AT91_CIDR_VERSION_MASK, 0, "at91sam9263", NULL),
0043     AT91_SOC(AT91SAM9G20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0044          AT91_CIDR_VERSION_MASK, 0, "at91sam9g20", NULL),
0045     AT91_SOC(AT91SAM9RL64_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0046          AT91_CIDR_VERSION_MASK, 0, "at91sam9rl64", NULL),
0047     AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0048          AT91_CIDR_VERSION_MASK, AT91SAM9M11_EXID_MATCH,
0049          "at91sam9m11", "at91sam9g45"),
0050     AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0051          AT91_CIDR_VERSION_MASK, AT91SAM9M10_EXID_MATCH,
0052          "at91sam9m10", "at91sam9g45"),
0053     AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0054          AT91_CIDR_VERSION_MASK, AT91SAM9G46_EXID_MATCH,
0055          "at91sam9g46", "at91sam9g45"),
0056     AT91_SOC(AT91SAM9G45_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0057          AT91_CIDR_VERSION_MASK, AT91SAM9G45_EXID_MATCH,
0058          "at91sam9g45", "at91sam9g45"),
0059     AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0060          AT91_CIDR_VERSION_MASK, AT91SAM9G15_EXID_MATCH,
0061          "at91sam9g15", "at91sam9x5"),
0062     AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0063          AT91_CIDR_VERSION_MASK, AT91SAM9G35_EXID_MATCH,
0064          "at91sam9g35", "at91sam9x5"),
0065     AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0066          AT91_CIDR_VERSION_MASK, AT91SAM9X35_EXID_MATCH,
0067          "at91sam9x35", "at91sam9x5"),
0068     AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0069          AT91_CIDR_VERSION_MASK, AT91SAM9G25_EXID_MATCH,
0070          "at91sam9g25", "at91sam9x5"),
0071     AT91_SOC(AT91SAM9X5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0072          AT91_CIDR_VERSION_MASK, AT91SAM9X25_EXID_MATCH,
0073          "at91sam9x25", "at91sam9x5"),
0074     AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0075          AT91_CIDR_VERSION_MASK, AT91SAM9CN12_EXID_MATCH,
0076          "at91sam9cn12", "at91sam9n12"),
0077     AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0078          AT91_CIDR_VERSION_MASK, AT91SAM9N12_EXID_MATCH,
0079          "at91sam9n12", "at91sam9n12"),
0080     AT91_SOC(AT91SAM9N12_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0081          AT91_CIDR_VERSION_MASK, AT91SAM9CN11_EXID_MATCH,
0082          "at91sam9cn11", "at91sam9n12"),
0083     AT91_SOC(AT91SAM9XE128_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0084          AT91_CIDR_VERSION_MASK, 0, "at91sam9xe128", "at91sam9xe128"),
0085     AT91_SOC(AT91SAM9XE256_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0086          AT91_CIDR_VERSION_MASK, 0, "at91sam9xe256", "at91sam9xe256"),
0087     AT91_SOC(AT91SAM9XE512_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0088          AT91_CIDR_VERSION_MASK, 0, "at91sam9xe512", "at91sam9xe512"),
0089 #endif
0090 #ifdef CONFIG_SOC_SAM9X60
0091     AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0092          AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
0093          "sam9x60", "sam9x60"),
0094     AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0095          AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
0096          "sam9x60 64MiB DDR2 SiP", "sam9x60"),
0097     AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0098          AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
0099          "sam9x60 128MiB DDR2 SiP", "sam9x60"),
0100     AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0101          AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
0102          "sam9x60 8MiB SDRAM SiP", "sam9x60"),
0103 #endif
0104 #ifdef CONFIG_SOC_SAMA5
0105     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0106          AT91_CIDR_VERSION_MASK, SAMA5D21CU_EXID_MATCH,
0107          "sama5d21", "sama5d2"),
0108     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0109          AT91_CIDR_VERSION_MASK, SAMA5D22CU_EXID_MATCH,
0110          "sama5d22", "sama5d2"),
0111     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0112          AT91_CIDR_VERSION_MASK, SAMA5D225C_D1M_EXID_MATCH,
0113          "sama5d225c 16MiB SiP", "sama5d2"),
0114     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0115          AT91_CIDR_VERSION_MASK, SAMA5D23CU_EXID_MATCH,
0116          "sama5d23", "sama5d2"),
0117     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0118          AT91_CIDR_VERSION_MASK, SAMA5D24CX_EXID_MATCH,
0119          "sama5d24", "sama5d2"),
0120     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0121          AT91_CIDR_VERSION_MASK, SAMA5D24CU_EXID_MATCH,
0122          "sama5d24", "sama5d2"),
0123     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0124          AT91_CIDR_VERSION_MASK, SAMA5D26CU_EXID_MATCH,
0125          "sama5d26", "sama5d2"),
0126     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0127          AT91_CIDR_VERSION_MASK, SAMA5D27CU_EXID_MATCH,
0128          "sama5d27", "sama5d2"),
0129     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0130          AT91_CIDR_VERSION_MASK, SAMA5D27CN_EXID_MATCH,
0131          "sama5d27", "sama5d2"),
0132     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0133          AT91_CIDR_VERSION_MASK, SAMA5D27C_D1G_EXID_MATCH,
0134          "sama5d27c 128MiB SiP", "sama5d2"),
0135     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0136          AT91_CIDR_VERSION_MASK, SAMA5D27C_D5M_EXID_MATCH,
0137          "sama5d27c 64MiB SiP", "sama5d2"),
0138     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0139          AT91_CIDR_VERSION_MASK, SAMA5D27C_LD1G_EXID_MATCH,
0140          "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
0141     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0142          AT91_CIDR_VERSION_MASK, SAMA5D27C_LD2G_EXID_MATCH,
0143          "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
0144     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0145          AT91_CIDR_VERSION_MASK, SAMA5D28CU_EXID_MATCH,
0146          "sama5d28", "sama5d2"),
0147     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0148          AT91_CIDR_VERSION_MASK, SAMA5D28CN_EXID_MATCH,
0149          "sama5d28", "sama5d2"),
0150     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0151          AT91_CIDR_VERSION_MASK, SAMA5D28C_D1G_EXID_MATCH,
0152          "sama5d28c 128MiB SiP", "sama5d2"),
0153     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0154          AT91_CIDR_VERSION_MASK, SAMA5D28C_LD1G_EXID_MATCH,
0155          "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
0156     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0157          AT91_CIDR_VERSION_MASK, SAMA5D28C_LD2G_EXID_MATCH,
0158          "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
0159     AT91_SOC(SAMA5D2_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0160          AT91_CIDR_VERSION_MASK, SAMA5D29CN_EXID_MATCH,
0161          "sama5d29", "sama5d2"),
0162     AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0163          AT91_CIDR_VERSION_MASK, SAMA5D31_EXID_MATCH,
0164          "sama5d31", "sama5d3"),
0165     AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0166          AT91_CIDR_VERSION_MASK, SAMA5D33_EXID_MATCH,
0167          "sama5d33", "sama5d3"),
0168     AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0169          AT91_CIDR_VERSION_MASK, SAMA5D34_EXID_MATCH,
0170          "sama5d34", "sama5d3"),
0171     AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0172          AT91_CIDR_VERSION_MASK, SAMA5D35_EXID_MATCH,
0173          "sama5d35", "sama5d3"),
0174     AT91_SOC(SAMA5D3_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0175          AT91_CIDR_VERSION_MASK, SAMA5D36_EXID_MATCH,
0176          "sama5d36", "sama5d3"),
0177     AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0178          AT91_CIDR_VERSION_MASK, SAMA5D41_EXID_MATCH,
0179          "sama5d41", "sama5d4"),
0180     AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0181          AT91_CIDR_VERSION_MASK, SAMA5D42_EXID_MATCH,
0182          "sama5d42", "sama5d4"),
0183     AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0184          AT91_CIDR_VERSION_MASK, SAMA5D43_EXID_MATCH,
0185          "sama5d43", "sama5d4"),
0186     AT91_SOC(SAMA5D4_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0187          AT91_CIDR_VERSION_MASK, SAMA5D44_EXID_MATCH,
0188          "sama5d44", "sama5d4"),
0189 #endif
0190 #ifdef CONFIG_SOC_SAMV7
0191     AT91_SOC(SAME70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0192          AT91_CIDR_VERSION_MASK, SAME70Q21_EXID_MATCH,
0193          "same70q21", "same7"),
0194     AT91_SOC(SAME70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0195          AT91_CIDR_VERSION_MASK, SAME70Q20_EXID_MATCH,
0196          "same70q20", "same7"),
0197     AT91_SOC(SAME70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0198          AT91_CIDR_VERSION_MASK, SAME70Q19_EXID_MATCH,
0199          "same70q19", "same7"),
0200     AT91_SOC(SAMS70Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0201          AT91_CIDR_VERSION_MASK, SAMS70Q21_EXID_MATCH,
0202          "sams70q21", "sams7"),
0203     AT91_SOC(SAMS70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0204          AT91_CIDR_VERSION_MASK, SAMS70Q20_EXID_MATCH,
0205          "sams70q20", "sams7"),
0206     AT91_SOC(SAMS70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0207          AT91_CIDR_VERSION_MASK, SAMS70Q19_EXID_MATCH,
0208          "sams70q19", "sams7"),
0209     AT91_SOC(SAMV71Q21_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0210          AT91_CIDR_VERSION_MASK, SAMV71Q21_EXID_MATCH,
0211          "samv71q21", "samv7"),
0212     AT91_SOC(SAMV71Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0213          AT91_CIDR_VERSION_MASK, SAMV71Q20_EXID_MATCH,
0214          "samv71q20", "samv7"),
0215     AT91_SOC(SAMV71Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0216          AT91_CIDR_VERSION_MASK, SAMV71Q19_EXID_MATCH,
0217          "samv71q19", "samv7"),
0218     AT91_SOC(SAMV70Q20_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0219          AT91_CIDR_VERSION_MASK, SAMV70Q20_EXID_MATCH,
0220          "samv70q20", "samv7"),
0221     AT91_SOC(SAMV70Q19_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0222          AT91_CIDR_VERSION_MASK, SAMV70Q19_EXID_MATCH,
0223          "samv70q19", "samv7"),
0224 #endif
0225 #ifdef CONFIG_SOC_SAMA7
0226     AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0227          AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G51_EXID_MATCH,
0228          "sama7g51", "sama7g5"),
0229     AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0230          AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G52_EXID_MATCH,
0231          "sama7g52", "sama7g5"),
0232     AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0233          AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G53_EXID_MATCH,
0234          "sama7g53", "sama7g5"),
0235     AT91_SOC(SAMA7G5_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
0236          AT91_CIDR_VERSION_MASK_SAMA7G5, SAMA7G54_EXID_MATCH,
0237          "sama7g54", "sama7g5"),
0238 #endif
0239     { /* sentinel */ },
0240 };
0241
0242 static int __init at91_get_cidr_exid_from_dbgu(u32 *cidr, u32 *exid)
0243 {
0244     struct device_node *np;
0245     void __iomem *regs;
0246
0247     np = of_find_compatible_node(NULL, NULL, "atmel,at91rm9200-dbgu");
0248     if (!np)
0249         np = of_find_compatible_node(NULL, NULL,
0250                          "atmel,at91sam9260-dbgu");
0251     if (!np)
0252         return -ENODEV;
0253
0254     regs = of_iomap(np, 0);
0255     of_node_put(np);
0256
0257     if (!regs) {
0258         pr_warn("Could not map DBGU iomem range");
0259         return -ENXIO;
0260     }
0261
0262     *cidr = readl(regs + AT91_DBGU_CIDR);
0263     *exid = readl(regs + AT91_DBGU_EXID);
0264
0265     iounmap(regs);
0266
0267     return 0;
0268 }
0269
0270 static int __init at91_get_cidr_exid_from_chipid(u32 *cidr, u32 *exid)
0271 {
0272     struct device_node *np;
0273     void __iomem *regs;
0274     static const struct of_device_id chipids[] = {
0275         { .compatible = "atmel,sama5d2-chipid" },
0276         { .compatible = "microchip,sama7g5-chipid" },
0277         { },
0278     };
0279
0280     np = of_find_matching_node(NULL, chipids);
0281     if (!np)
0282         return -ENODEV;
0283
0284     regs = of_iomap(np, 0);
0285     of_node_put(np);
0286
0287     if (!regs) {
0288         pr_warn("Could not map DBGU iomem range");
0289         return -ENXIO;
0290     }
0291
0292     *cidr = readl(regs + AT91_CHIPID_CIDR);
0293     *exid = readl(regs + AT91_CHIPID_EXID);
0294
0295     iounmap(regs);
0296
0297     return 0;
0298 }
0299
0300 struct soc_device * __init at91_soc_init(const struct at91_soc *socs)
0301 {
0302     struct soc_device_attribute *soc_dev_attr;
0303     const struct at91_soc *soc;
0304     struct soc_device *soc_dev;
0305     u32 cidr, exid;
0306     int ret;
0307
0308     /*
0309      * With SAMA5D2 and later SoCs, CIDR and EXID registers are no more
0310      * in the dbgu device but in the chipid device whose purpose is only
0311      * to expose these two registers.
0312      */
0313     ret = at91_get_cidr_exid_from_dbgu(&cidr, &exid);
0314     if (ret)
0315         ret = at91_get_cidr_exid_from_chipid(&cidr, &exid);
0316     if (ret) {
0317         if (ret == -ENODEV)
0318             pr_warn("Could not find identification node");
0319         return NULL;
0320     }
0321
0322     for (soc = socs; soc->name; soc++) {
0323         if (soc->cidr_match != (cidr & soc->cidr_mask))
0324             continue;
0325
0326         if (!(cidr & AT91_CIDR_EXT) || soc->exid_match == exid)
0327             break;
0328     }
0329
0330     if (!soc->name) {
0331         pr_warn("Could not find matching SoC description\n");
0332         return NULL;
0333     }
0334
0335     soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
0336     if (!soc_dev_attr)
0337         return NULL;
0338
0339     soc_dev_attr->family = soc->family;
0340     soc_dev_attr->soc_id = soc->name;
0341     soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X",
0342                        AT91_CIDR_VERSION(cidr, soc->version_mask));
0343     soc_dev = soc_device_register(soc_dev_attr);
0344     if (IS_ERR(soc_dev)) {
0345         kfree(soc_dev_attr->revision);
0346         kfree(soc_dev_attr);
0347         pr_warn("Could not register SoC device\n");
0348         return NULL;
0349     }
0350
0351     if (soc->family)
0352         pr_info("Detected SoC family: %s\n", soc->family);
0353     pr_info("Detected SoC: %s, revision %X\n", soc->name,
0354         AT91_CIDR_VERSION(cidr, soc->version_mask));
0355
0356     return soc_dev;
0357 }
0358
0359 static const struct of_device_id at91_soc_allowed_list[] __initconst = {
0360     { .compatible = "atmel,at91rm9200", },
0361     { .compatible = "atmel,at91sam9", },
0362     { .compatible = "atmel,sama5", },
0363     { .compatible = "atmel,samv7", },
0364     { .compatible = "microchip,sama7g5", },
0365     { }
0366 };
0367
0368 static int __init atmel_soc_device_init(void)
0369 {
0370     struct device_node *np = of_find_node_by_path("/");
0371
0372     if (!of_match_node(at91_soc_allowed_list, np))
0373         return 0;
0374
0375     at91_soc_init(socs);
0376
0377     return 0;
0378 }
0379 subsys_initcall(atmel_soc_device_init);