0001 # SPDX-License-Identifier: GPL-2.0-only
0002
0003 if ARCH_ASPEED || COMPILE_TEST
0004
0005 menu "ASPEED SoC drivers"
0006
0007 config ASPEED_LPC_CTRL
0008 tristate "ASPEED LPC firmware cycle control"
0009 select REGMAP
0010 select MFD_SYSCON
0011 default ARCH_ASPEED
0012 help
0013 Control LPC firmware cycle mappings through ioctl()s. The driver
0014 also provides a read/write interface to a BMC ram region where the
0015 host LPC read/write region can be buffered.
0016
0017 config ASPEED_LPC_SNOOP
0018 tristate "ASPEED LPC snoop support"
0019 select REGMAP
0020 select MFD_SYSCON
0021 default ARCH_ASPEED
0022 help
0023 Provides a driver to control the LPC snoop interface which
0024 allows the BMC to listen on and save the data written by
0025 the host to an arbitrary LPC I/O port.
0026
0027 config ASPEED_UART_ROUTING
0028 tristate "ASPEED uart routing control"
0029 select REGMAP
0030 select MFD_SYSCON
0031 default ARCH_ASPEED
0032 help
0033 Provides a driver to control the UART routing paths, allowing
0034 users to perform runtime configuration of the RX muxes among
0035 the UART controllers and I/O pins.
0036
0037 config ASPEED_P2A_CTRL
0038 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
0039 select REGMAP
0040 select MFD_SYSCON
0041 default ARCH_ASPEED
0042 help
0043 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The
0044 driver also provides an interface for userspace mappings to a
0045 pre-defined region.
0046
0047 config ASPEED_SOCINFO
0048 bool "ASPEED SoC Information driver"
0049 default ARCH_ASPEED
0050 select SOC_BUS
0051 default ARCH_ASPEED
0052 help
0053 Say yes to support decoding of ASPEED BMC information.
0054
0055 endmenu
0056
0057 endif
