0001 # SPDX-License-Identifier: GPL-2.0-only
0002
0003 if ARCH_APPLE || COMPILE_TEST
0004
0005 menu "Apple SoC drivers"
0006
0007 config APPLE_PMGR_PWRSTATE
0008 bool "Apple SoC PMGR power state control"
0009 depends on PM
0010 select REGMAP
0011 select MFD_SYSCON
0012 select PM_GENERIC_DOMAINS
0013 select RESET_CONTROLLER
0014 default ARCH_APPLE
0015 help
0016 The PMGR block in Apple SoCs provides high-level power state
0017 controls for SoC devices. This driver manages them through the
0018 generic power domain framework, and also provides reset support.
0019
0020 config APPLE_RTKIT
0021 tristate "Apple RTKit co-processor IPC protocol"
0022 depends on MAILBOX
0023 depends on ARCH_APPLE || COMPILE_TEST
0024 default ARCH_APPLE
0025 help
0026 Apple SoCs such as the M1 come with various co-processors running
0027 their proprietary RTKit operating system. This option enables support
0028 for the protocol library used to communicate with those. It is used
0029 by various client drivers.
0030
0031 Say 'y' here if you have an Apple SoC.
0032
0033 config APPLE_SART
0034 tristate "Apple SART DMA address filter"
0035 depends on ARCH_APPLE || COMPILE_TEST
0036 default ARCH_APPLE
0037 help
0038 Apple SART is a simple DMA address filter used on Apple SoCs such
0039 as the M1. It is usually required for the NVMe coprocessor which does
0040 not use a proper IOMMU.
0041
0042 Say 'y' here if you have an Apple SoC.
0043
0044 endmenu
0045
0046 endif
