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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2011-2017, The Linux Foundation
0004  */
0005 
0006 #include <linux/irq.h>
0007 #include <linux/kernel.h>
0008 #include <linux/init.h>
0009 #include <linux/slab.h>
0010 #include <linux/io.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/delay.h>
0014 #include <linux/clk.h>
0015 #include <linux/of.h>
0016 #include <linux/pm_runtime.h>
0017 #include "slimbus.h"
0018 
0019 /* Manager registers */
0020 #define MGR_CFG     0x200
0021 #define MGR_STATUS  0x204
0022 #define MGR_INT_EN  0x210
0023 #define MGR_INT_STAT    0x214
0024 #define MGR_INT_CLR 0x218
0025 #define MGR_TX_MSG  0x230
0026 #define MGR_RX_MSG  0x270
0027 #define MGR_IE_STAT 0x2F0
0028 #define MGR_VE_STAT 0x300
0029 #define MGR_CFG_ENABLE  1
0030 
0031 /* Framer registers */
0032 #define FRM_CFG     0x400
0033 #define FRM_STAT    0x404
0034 #define FRM_INT_EN  0x410
0035 #define FRM_INT_STAT    0x414
0036 #define FRM_INT_CLR 0x418
0037 #define FRM_WAKEUP  0x41C
0038 #define FRM_CLKCTL_DONE 0x420
0039 #define FRM_IE_STAT 0x430
0040 #define FRM_VE_STAT 0x440
0041 
0042 /* Interface registers */
0043 #define INTF_CFG    0x600
0044 #define INTF_STAT   0x604
0045 #define INTF_INT_EN 0x610
0046 #define INTF_INT_STAT   0x614
0047 #define INTF_INT_CLR    0x618
0048 #define INTF_IE_STAT    0x630
0049 #define INTF_VE_STAT    0x640
0050 
0051 /* Interrupt status bits */
0052 #define MGR_INT_TX_NACKED_2 BIT(25)
0053 #define MGR_INT_MSG_BUF_CONTE   BIT(26)
0054 #define MGR_INT_RX_MSG_RCVD BIT(30)
0055 #define MGR_INT_TX_MSG_SENT BIT(31)
0056 
0057 /* Framer config register settings */
0058 #define FRM_ACTIVE  1
0059 #define CLK_GEAR    7
0060 #define ROOT_FREQ   11
0061 #define REF_CLK_GEAR    15
0062 #define INTR_WAKE   19
0063 
0064 #define SLIM_MSG_ASM_FIRST_WORD(l, mt, mc, dt, ad) \
0065         ((l) | ((mt) << 5) | ((mc) << 8) | ((dt) << 15) | ((ad) << 16))
0066 
0067 #define SLIM_ROOT_FREQ 24576000
0068 #define QCOM_SLIM_AUTOSUSPEND 1000
0069 
0070 /* MAX message size over control channel */
0071 #define SLIM_MSGQ_BUF_LEN   40
0072 #define QCOM_TX_MSGS 2
0073 #define QCOM_RX_MSGS    8
0074 #define QCOM_BUF_ALLOC_RETRIES  10
0075 
0076 #define CFG_PORT(r, v) ((v) ? CFG_PORT_V2(r) : CFG_PORT_V1(r))
0077 
0078 /* V2 Component registers */
0079 #define CFG_PORT_V2(r) ((r ## _V2))
0080 #define COMP_CFG_V2     4
0081 #define COMP_TRUST_CFG_V2   0x3000
0082 
0083 /* V1 Component registers */
0084 #define CFG_PORT_V1(r) ((r ## _V1))
0085 #define COMP_CFG_V1     0
0086 #define COMP_TRUST_CFG_V1   0x14
0087 
0088 /* Resource group info for manager, and non-ported generic device-components */
0089 #define EE_MGR_RSC_GRP  (1 << 10)
0090 #define EE_NGD_2    (2 << 6)
0091 #define EE_NGD_1    0
0092 
0093 struct slim_ctrl_buf {
0094     void        *base;
0095     spinlock_t  lock;
0096     int     head;
0097     int     tail;
0098     int     sl_sz;
0099     int     n;
0100 };
0101 
0102 struct qcom_slim_ctrl {
0103     struct slim_controller  ctrl;
0104     struct slim_framer  framer;
0105     struct device       *dev;
0106     void __iomem        *base;
0107     void __iomem        *slew_reg;
0108 
0109     struct slim_ctrl_buf    rx;
0110     struct slim_ctrl_buf    tx;
0111 
0112     struct completion   **wr_comp;
0113     int         irq;
0114     struct workqueue_struct *rxwq;
0115     struct work_struct  wd;
0116     struct clk      *rclk;
0117     struct clk      *hclk;
0118 };
0119 
0120 static void qcom_slim_queue_tx(struct qcom_slim_ctrl *ctrl, void *buf,
0121                    u8 len, u32 tx_reg)
0122 {
0123     int count = (len + 3) >> 2;
0124 
0125     __iowrite32_copy(ctrl->base + tx_reg, buf, count);
0126 
0127     /* Ensure Oder of subsequent writes */
0128     mb();
0129 }
0130 
0131 static void *slim_alloc_rxbuf(struct qcom_slim_ctrl *ctrl)
0132 {
0133     unsigned long flags;
0134     int idx;
0135 
0136     spin_lock_irqsave(&ctrl->rx.lock, flags);
0137     if ((ctrl->rx.tail + 1) % ctrl->rx.n == ctrl->rx.head) {
0138         spin_unlock_irqrestore(&ctrl->rx.lock, flags);
0139         dev_err(ctrl->dev, "RX QUEUE full!");
0140         return NULL;
0141     }
0142     idx = ctrl->rx.tail;
0143     ctrl->rx.tail = (ctrl->rx.tail + 1) % ctrl->rx.n;
0144     spin_unlock_irqrestore(&ctrl->rx.lock, flags);
0145 
0146     return ctrl->rx.base + (idx * ctrl->rx.sl_sz);
0147 }
0148 
0149 static void slim_ack_txn(struct qcom_slim_ctrl *ctrl, int err)
0150 {
0151     struct completion *comp;
0152     unsigned long flags;
0153     int idx;
0154 
0155     spin_lock_irqsave(&ctrl->tx.lock, flags);
0156     idx = ctrl->tx.head;
0157     ctrl->tx.head = (ctrl->tx.head + 1) % ctrl->tx.n;
0158     spin_unlock_irqrestore(&ctrl->tx.lock, flags);
0159 
0160     comp = ctrl->wr_comp[idx];
0161     ctrl->wr_comp[idx] = NULL;
0162 
0163     complete(comp);
0164 }
0165 
0166 static irqreturn_t qcom_slim_handle_tx_irq(struct qcom_slim_ctrl *ctrl,
0167                        u32 stat)
0168 {
0169     int err = 0;
0170 
0171     if (stat & MGR_INT_TX_MSG_SENT)
0172         writel_relaxed(MGR_INT_TX_MSG_SENT,
0173                    ctrl->base + MGR_INT_CLR);
0174 
0175     if (stat & MGR_INT_TX_NACKED_2) {
0176         u32 mgr_stat = readl_relaxed(ctrl->base + MGR_STATUS);
0177         u32 mgr_ie_stat = readl_relaxed(ctrl->base + MGR_IE_STAT);
0178         u32 frm_stat = readl_relaxed(ctrl->base + FRM_STAT);
0179         u32 frm_cfg = readl_relaxed(ctrl->base + FRM_CFG);
0180         u32 frm_intr_stat = readl_relaxed(ctrl->base + FRM_INT_STAT);
0181         u32 frm_ie_stat = readl_relaxed(ctrl->base + FRM_IE_STAT);
0182         u32 intf_stat = readl_relaxed(ctrl->base + INTF_STAT);
0183         u32 intf_intr_stat = readl_relaxed(ctrl->base + INTF_INT_STAT);
0184         u32 intf_ie_stat = readl_relaxed(ctrl->base + INTF_IE_STAT);
0185 
0186         writel_relaxed(MGR_INT_TX_NACKED_2, ctrl->base + MGR_INT_CLR);
0187 
0188         dev_err(ctrl->dev, "TX Nack MGR:int:0x%x, stat:0x%x\n",
0189             stat, mgr_stat);
0190         dev_err(ctrl->dev, "TX Nack MGR:ie:0x%x\n", mgr_ie_stat);
0191         dev_err(ctrl->dev, "TX Nack FRM:int:0x%x, stat:0x%x\n",
0192             frm_intr_stat, frm_stat);
0193         dev_err(ctrl->dev, "TX Nack FRM:cfg:0x%x, ie:0x%x\n",
0194             frm_cfg, frm_ie_stat);
0195         dev_err(ctrl->dev, "TX Nack INTF:intr:0x%x, stat:0x%x\n",
0196             intf_intr_stat, intf_stat);
0197         dev_err(ctrl->dev, "TX Nack INTF:ie:0x%x\n",
0198             intf_ie_stat);
0199         err = -ENOTCONN;
0200     }
0201 
0202     slim_ack_txn(ctrl, err);
0203 
0204     return IRQ_HANDLED;
0205 }
0206 
0207 static irqreturn_t qcom_slim_handle_rx_irq(struct qcom_slim_ctrl *ctrl,
0208                        u32 stat)
0209 {
0210     u32 *rx_buf, pkt[10];
0211     bool q_rx = false;
0212     u8 mc, mt, len;
0213 
0214     pkt[0] = readl_relaxed(ctrl->base + MGR_RX_MSG);
0215     mt = SLIM_HEADER_GET_MT(pkt[0]);
0216     len = SLIM_HEADER_GET_RL(pkt[0]);
0217     mc = SLIM_HEADER_GET_MC(pkt[0]>>8);
0218 
0219     /*
0220      * this message cannot be handled by ISR, so
0221      * let work-queue handle it
0222      */
0223     if (mt == SLIM_MSG_MT_CORE && mc == SLIM_MSG_MC_REPORT_PRESENT) {
0224         rx_buf = (u32 *)slim_alloc_rxbuf(ctrl);
0225         if (!rx_buf) {
0226             dev_err(ctrl->dev, "dropping RX:0x%x due to RX full\n",
0227                     pkt[0]);
0228             goto rx_ret_irq;
0229         }
0230         rx_buf[0] = pkt[0];
0231 
0232     } else {
0233         rx_buf = pkt;
0234     }
0235 
0236     __ioread32_copy(rx_buf + 1, ctrl->base + MGR_RX_MSG + 4,
0237             DIV_ROUND_UP(len, 4));
0238 
0239     switch (mc) {
0240 
0241     case SLIM_MSG_MC_REPORT_PRESENT:
0242         q_rx = true;
0243         break;
0244     case SLIM_MSG_MC_REPLY_INFORMATION:
0245     case SLIM_MSG_MC_REPLY_VALUE:
0246         slim_msg_response(&ctrl->ctrl, (u8 *)(rx_buf + 1),
0247                   (u8)(*rx_buf >> 24), (len - 4));
0248         break;
0249     default:
0250         dev_err(ctrl->dev, "unsupported MC,%x MT:%x\n",
0251             mc, mt);
0252         break;
0253     }
0254 rx_ret_irq:
0255     writel(MGR_INT_RX_MSG_RCVD, ctrl->base +
0256                MGR_INT_CLR);
0257     if (q_rx)
0258         queue_work(ctrl->rxwq, &ctrl->wd);
0259 
0260     return IRQ_HANDLED;
0261 }
0262 
0263 static irqreturn_t qcom_slim_interrupt(int irq, void *d)
0264 {
0265     struct qcom_slim_ctrl *ctrl = d;
0266     u32 stat = readl_relaxed(ctrl->base + MGR_INT_STAT);
0267     int ret = IRQ_NONE;
0268 
0269     if (stat & MGR_INT_TX_MSG_SENT || stat & MGR_INT_TX_NACKED_2)
0270         ret = qcom_slim_handle_tx_irq(ctrl, stat);
0271 
0272     if (stat & MGR_INT_RX_MSG_RCVD)
0273         ret = qcom_slim_handle_rx_irq(ctrl, stat);
0274 
0275     return ret;
0276 }
0277 
0278 static int qcom_clk_pause_wakeup(struct slim_controller *sctrl)
0279 {
0280     struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
0281 
0282     clk_prepare_enable(ctrl->hclk);
0283     clk_prepare_enable(ctrl->rclk);
0284     enable_irq(ctrl->irq);
0285 
0286     writel_relaxed(1, ctrl->base + FRM_WAKEUP);
0287     /* Make sure framer wakeup write goes through before ISR fires */
0288     mb();
0289     /*
0290      * HW Workaround: Currently, slave is reporting lost-sync messages
0291      * after SLIMbus comes out of clock pause.
0292      * Transaction with slave fail before slave reports that message
0293      * Give some time for that report to come
0294      * SLIMbus wakes up in clock gear 10 at 24.576MHz. With each superframe
0295      * being 250 usecs, we wait for 5-10 superframes here to ensure
0296      * we get the message
0297      */
0298     usleep_range(1250, 2500);
0299     return 0;
0300 }
0301 
0302 static void *slim_alloc_txbuf(struct qcom_slim_ctrl *ctrl,
0303                   struct slim_msg_txn *txn,
0304                   struct completion *done)
0305 {
0306     unsigned long flags;
0307     int idx;
0308 
0309     spin_lock_irqsave(&ctrl->tx.lock, flags);
0310     if (((ctrl->tx.head + 1) % ctrl->tx.n) == ctrl->tx.tail) {
0311         spin_unlock_irqrestore(&ctrl->tx.lock, flags);
0312         dev_err(ctrl->dev, "controller TX buf unavailable");
0313         return NULL;
0314     }
0315     idx = ctrl->tx.tail;
0316     ctrl->wr_comp[idx] = done;
0317     ctrl->tx.tail = (ctrl->tx.tail + 1) % ctrl->tx.n;
0318 
0319     spin_unlock_irqrestore(&ctrl->tx.lock, flags);
0320 
0321     return ctrl->tx.base + (idx * ctrl->tx.sl_sz);
0322 }
0323 
0324 
0325 static int qcom_xfer_msg(struct slim_controller *sctrl,
0326              struct slim_msg_txn *txn)
0327 {
0328     struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
0329     DECLARE_COMPLETION_ONSTACK(done);
0330     void *pbuf = slim_alloc_txbuf(ctrl, txn, &done);
0331     unsigned long ms = txn->rl + HZ;
0332     u8 *puc;
0333     int ret = 0, timeout, retries = QCOM_BUF_ALLOC_RETRIES;
0334     u8 la = txn->la;
0335     u32 *head;
0336     /* HW expects length field to be excluded */
0337     txn->rl--;
0338 
0339     /* spin till buffer is made available */
0340     if (!pbuf) {
0341         while (retries--) {
0342             usleep_range(10000, 15000);
0343             pbuf = slim_alloc_txbuf(ctrl, txn, &done);
0344             if (pbuf)
0345                 break;
0346         }
0347     }
0348 
0349     if (retries < 0 && !pbuf)
0350         return -ENOMEM;
0351 
0352     puc = (u8 *)pbuf;
0353     head = (u32 *)pbuf;
0354 
0355     if (txn->dt == SLIM_MSG_DEST_LOGICALADDR) {
0356         *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
0357                         txn->mc, 0, la);
0358         puc += 3;
0359     } else {
0360         *head = SLIM_MSG_ASM_FIRST_WORD(txn->rl, txn->mt,
0361                         txn->mc, 1, la);
0362         puc += 2;
0363     }
0364 
0365     if (slim_tid_txn(txn->mt, txn->mc))
0366         *(puc++) = txn->tid;
0367 
0368     if (slim_ec_txn(txn->mt, txn->mc)) {
0369         *(puc++) = (txn->ec & 0xFF);
0370         *(puc++) = (txn->ec >> 8) & 0xFF;
0371     }
0372 
0373     if (txn->msg && txn->msg->wbuf)
0374         memcpy(puc, txn->msg->wbuf, txn->msg->num_bytes);
0375 
0376     qcom_slim_queue_tx(ctrl, head, txn->rl, MGR_TX_MSG);
0377     timeout = wait_for_completion_timeout(&done, msecs_to_jiffies(ms));
0378 
0379     if (!timeout) {
0380         dev_err(ctrl->dev, "TX timed out:MC:0x%x,mt:0x%x", txn->mc,
0381                     txn->mt);
0382         ret = -ETIMEDOUT;
0383     }
0384 
0385     return ret;
0386 
0387 }
0388 
0389 static int qcom_set_laddr(struct slim_controller *sctrl,
0390                 struct slim_eaddr *ead, u8 laddr)
0391 {
0392     struct qcom_slim_ctrl *ctrl = dev_get_drvdata(sctrl->dev);
0393     struct {
0394         __be16 manf_id;
0395         __be16 prod_code;
0396         u8 dev_index;
0397         u8 instance;
0398         u8 laddr;
0399     } __packed p;
0400     struct slim_val_inf msg = {0};
0401     DEFINE_SLIM_EDEST_TXN(txn, SLIM_MSG_MC_ASSIGN_LOGICAL_ADDRESS,
0402                   10, laddr, &msg);
0403     int ret;
0404 
0405     p.manf_id = cpu_to_be16(ead->manf_id);
0406     p.prod_code = cpu_to_be16(ead->prod_code);
0407     p.dev_index = ead->dev_index;
0408     p.instance = ead->instance;
0409     p.laddr = laddr;
0410 
0411     msg.wbuf = (void *)&p;
0412     msg.num_bytes = 7;
0413     ret = slim_do_transfer(&ctrl->ctrl, &txn);
0414 
0415     if (ret)
0416         dev_err(ctrl->dev, "set LA:0x%x failed:ret:%d\n",
0417                   laddr, ret);
0418     return ret;
0419 }
0420 
0421 static int slim_get_current_rxbuf(struct qcom_slim_ctrl *ctrl, void *buf)
0422 {
0423     unsigned long flags;
0424 
0425     spin_lock_irqsave(&ctrl->rx.lock, flags);
0426     if (ctrl->rx.tail == ctrl->rx.head) {
0427         spin_unlock_irqrestore(&ctrl->rx.lock, flags);
0428         return -ENODATA;
0429     }
0430     memcpy(buf, ctrl->rx.base + (ctrl->rx.head * ctrl->rx.sl_sz),
0431                 ctrl->rx.sl_sz);
0432 
0433     ctrl->rx.head = (ctrl->rx.head + 1) % ctrl->rx.n;
0434     spin_unlock_irqrestore(&ctrl->rx.lock, flags);
0435 
0436     return 0;
0437 }
0438 
0439 static void qcom_slim_rxwq(struct work_struct *work)
0440 {
0441     u8 buf[SLIM_MSGQ_BUF_LEN];
0442     u8 mc, mt;
0443     int ret;
0444     struct qcom_slim_ctrl *ctrl = container_of(work, struct qcom_slim_ctrl,
0445                          wd);
0446 
0447     while ((slim_get_current_rxbuf(ctrl, buf)) != -ENODATA) {
0448         mt = SLIM_HEADER_GET_MT(buf[0]);
0449         mc = SLIM_HEADER_GET_MC(buf[1]);
0450         if (mt == SLIM_MSG_MT_CORE &&
0451             mc == SLIM_MSG_MC_REPORT_PRESENT) {
0452             struct slim_eaddr ea;
0453             u8 laddr;
0454 
0455             ea.manf_id = be16_to_cpup((__be16 *)&buf[2]);
0456             ea.prod_code = be16_to_cpup((__be16 *)&buf[4]);
0457             ea.dev_index = buf[6];
0458             ea.instance = buf[7];
0459 
0460             ret = slim_device_report_present(&ctrl->ctrl, &ea,
0461                              &laddr);
0462             if (ret < 0)
0463                 dev_err(ctrl->dev, "assign laddr failed:%d\n",
0464                     ret);
0465         } else {
0466             dev_err(ctrl->dev, "unexpected message:mc:%x, mt:%x\n",
0467                 mc, mt);
0468         }
0469     }
0470 }
0471 
0472 static void qcom_slim_prg_slew(struct platform_device *pdev,
0473                 struct qcom_slim_ctrl *ctrl)
0474 {
0475     if (!ctrl->slew_reg) {
0476         /* SLEW RATE register for this SLIMbus */
0477         ctrl->slew_reg = devm_platform_ioremap_resource_byname(pdev, "slew");
0478         if (IS_ERR(ctrl->slew_reg))
0479             return;
0480     }
0481 
0482     writel_relaxed(1, ctrl->slew_reg);
0483     /* Make sure SLIMbus-slew rate enabling goes through */
0484     wmb();
0485 }
0486 
0487 static int qcom_slim_probe(struct platform_device *pdev)
0488 {
0489     struct qcom_slim_ctrl *ctrl;
0490     struct slim_controller *sctrl;
0491     struct resource *slim_mem;
0492     int ret, ver;
0493 
0494     ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
0495     if (!ctrl)
0496         return -ENOMEM;
0497 
0498     ctrl->hclk = devm_clk_get(&pdev->dev, "iface");
0499     if (IS_ERR(ctrl->hclk))
0500         return PTR_ERR(ctrl->hclk);
0501 
0502     ctrl->rclk = devm_clk_get(&pdev->dev, "core");
0503     if (IS_ERR(ctrl->rclk))
0504         return PTR_ERR(ctrl->rclk);
0505 
0506     ret = clk_set_rate(ctrl->rclk, SLIM_ROOT_FREQ);
0507     if (ret) {
0508         dev_err(&pdev->dev, "ref-clock set-rate failed:%d\n", ret);
0509         return ret;
0510     }
0511 
0512     ctrl->irq = platform_get_irq(pdev, 0);
0513     if (ctrl->irq < 0)
0514         return ctrl->irq;
0515 
0516     sctrl = &ctrl->ctrl;
0517     sctrl->dev = &pdev->dev;
0518     ctrl->dev = &pdev->dev;
0519     platform_set_drvdata(pdev, ctrl);
0520     dev_set_drvdata(ctrl->dev, ctrl);
0521 
0522     slim_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctrl");
0523     ctrl->base = devm_ioremap_resource(ctrl->dev, slim_mem);
0524     if (IS_ERR(ctrl->base))
0525         return PTR_ERR(ctrl->base);
0526 
0527     sctrl->set_laddr = qcom_set_laddr;
0528     sctrl->xfer_msg = qcom_xfer_msg;
0529     sctrl->wakeup =  qcom_clk_pause_wakeup;
0530     ctrl->tx.n = QCOM_TX_MSGS;
0531     ctrl->tx.sl_sz = SLIM_MSGQ_BUF_LEN;
0532     ctrl->rx.n = QCOM_RX_MSGS;
0533     ctrl->rx.sl_sz = SLIM_MSGQ_BUF_LEN;
0534     ctrl->wr_comp = kcalloc(QCOM_TX_MSGS, sizeof(struct completion *),
0535                 GFP_KERNEL);
0536     if (!ctrl->wr_comp)
0537         return -ENOMEM;
0538 
0539     spin_lock_init(&ctrl->rx.lock);
0540     spin_lock_init(&ctrl->tx.lock);
0541     INIT_WORK(&ctrl->wd, qcom_slim_rxwq);
0542     ctrl->rxwq = create_singlethread_workqueue("qcom_slim_rx");
0543     if (!ctrl->rxwq) {
0544         dev_err(ctrl->dev, "Failed to start Rx WQ\n");
0545         return -ENOMEM;
0546     }
0547 
0548     ctrl->framer.rootfreq = SLIM_ROOT_FREQ / 8;
0549     ctrl->framer.superfreq =
0550         ctrl->framer.rootfreq / SLIM_CL_PER_SUPERFRAME_DIV8;
0551     sctrl->a_framer = &ctrl->framer;
0552     sctrl->clkgear = SLIM_MAX_CLK_GEAR;
0553 
0554     qcom_slim_prg_slew(pdev, ctrl);
0555 
0556     ret = devm_request_irq(&pdev->dev, ctrl->irq, qcom_slim_interrupt,
0557                 IRQF_TRIGGER_HIGH, "qcom_slim_irq", ctrl);
0558     if (ret) {
0559         dev_err(&pdev->dev, "request IRQ failed\n");
0560         goto err_request_irq_failed;
0561     }
0562 
0563     ret = clk_prepare_enable(ctrl->hclk);
0564     if (ret)
0565         goto err_hclk_enable_failed;
0566 
0567     ret = clk_prepare_enable(ctrl->rclk);
0568     if (ret)
0569         goto err_rclk_enable_failed;
0570 
0571     ctrl->tx.base = devm_kcalloc(&pdev->dev, ctrl->tx.n, ctrl->tx.sl_sz,
0572                      GFP_KERNEL);
0573     if (!ctrl->tx.base) {
0574         ret = -ENOMEM;
0575         goto err;
0576     }
0577 
0578     ctrl->rx.base = devm_kcalloc(&pdev->dev,ctrl->rx.n, ctrl->rx.sl_sz,
0579                      GFP_KERNEL);
0580     if (!ctrl->rx.base) {
0581         ret = -ENOMEM;
0582         goto err;
0583     }
0584 
0585     /* Register with framework before enabling frame, clock */
0586     ret = slim_register_controller(&ctrl->ctrl);
0587     if (ret) {
0588         dev_err(ctrl->dev, "error adding controller\n");
0589         goto err;
0590     }
0591 
0592     ver = readl_relaxed(ctrl->base);
0593     /* Version info in 16 MSbits */
0594     ver >>= 16;
0595     /* Component register initialization */
0596     writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
0597     writel((EE_MGR_RSC_GRP | EE_NGD_2 | EE_NGD_1),
0598                 ctrl->base + CFG_PORT(COMP_TRUST_CFG, ver));
0599 
0600     writel((MGR_INT_TX_NACKED_2 |
0601             MGR_INT_MSG_BUF_CONTE | MGR_INT_RX_MSG_RCVD |
0602             MGR_INT_TX_MSG_SENT), ctrl->base + MGR_INT_EN);
0603     writel(1, ctrl->base + MGR_CFG);
0604     /* Framer register initialization */
0605     writel((1 << INTR_WAKE) | (0xA << REF_CLK_GEAR) |
0606         (0xA << CLK_GEAR) | (1 << ROOT_FREQ) | (1 << FRM_ACTIVE) | 1,
0607         ctrl->base + FRM_CFG);
0608     writel(MGR_CFG_ENABLE, ctrl->base + MGR_CFG);
0609     writel(1, ctrl->base + INTF_CFG);
0610     writel(1, ctrl->base + CFG_PORT(COMP_CFG, ver));
0611 
0612     pm_runtime_use_autosuspend(&pdev->dev);
0613     pm_runtime_set_autosuspend_delay(&pdev->dev, QCOM_SLIM_AUTOSUSPEND);
0614     pm_runtime_set_active(&pdev->dev);
0615     pm_runtime_mark_last_busy(&pdev->dev);
0616     pm_runtime_enable(&pdev->dev);
0617 
0618     dev_dbg(ctrl->dev, "QCOM SB controller is up:ver:0x%x!\n", ver);
0619     return 0;
0620 
0621 err:
0622     clk_disable_unprepare(ctrl->rclk);
0623 err_rclk_enable_failed:
0624     clk_disable_unprepare(ctrl->hclk);
0625 err_hclk_enable_failed:
0626 err_request_irq_failed:
0627     destroy_workqueue(ctrl->rxwq);
0628     return ret;
0629 }
0630 
0631 static int qcom_slim_remove(struct platform_device *pdev)
0632 {
0633     struct qcom_slim_ctrl *ctrl = platform_get_drvdata(pdev);
0634 
0635     pm_runtime_disable(&pdev->dev);
0636     slim_unregister_controller(&ctrl->ctrl);
0637     clk_disable_unprepare(ctrl->rclk);
0638     clk_disable_unprepare(ctrl->hclk);
0639     destroy_workqueue(ctrl->rxwq);
0640     return 0;
0641 }
0642 
0643 /*
0644  * If PM_RUNTIME is not defined, these 2 functions become helper
0645  * functions to be called from system suspend/resume.
0646  */
0647 #ifdef CONFIG_PM
0648 static int qcom_slim_runtime_suspend(struct device *device)
0649 {
0650     struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
0651     int ret;
0652 
0653     dev_dbg(device, "pm_runtime: suspending...\n");
0654     ret = slim_ctrl_clk_pause(&ctrl->ctrl, false, SLIM_CLK_UNSPECIFIED);
0655     if (ret) {
0656         dev_err(device, "clk pause not entered:%d", ret);
0657     } else {
0658         disable_irq(ctrl->irq);
0659         clk_disable_unprepare(ctrl->hclk);
0660         clk_disable_unprepare(ctrl->rclk);
0661     }
0662     return ret;
0663 }
0664 
0665 static int qcom_slim_runtime_resume(struct device *device)
0666 {
0667     struct qcom_slim_ctrl *ctrl = dev_get_drvdata(device);
0668     int ret = 0;
0669 
0670     dev_dbg(device, "pm_runtime: resuming...\n");
0671     ret = slim_ctrl_clk_pause(&ctrl->ctrl, true, 0);
0672     if (ret)
0673         dev_err(device, "clk pause not exited:%d", ret);
0674     return ret;
0675 }
0676 #endif
0677 
0678 #ifdef CONFIG_PM_SLEEP
0679 static int qcom_slim_suspend(struct device *dev)
0680 {
0681     int ret = 0;
0682 
0683     if (!pm_runtime_enabled(dev) ||
0684         (!pm_runtime_suspended(dev))) {
0685         dev_dbg(dev, "system suspend");
0686         ret = qcom_slim_runtime_suspend(dev);
0687     }
0688 
0689     return ret;
0690 }
0691 
0692 static int qcom_slim_resume(struct device *dev)
0693 {
0694     if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
0695         int ret;
0696 
0697         dev_dbg(dev, "system resume");
0698         ret = qcom_slim_runtime_resume(dev);
0699         if (!ret) {
0700             pm_runtime_mark_last_busy(dev);
0701             pm_request_autosuspend(dev);
0702         }
0703         return ret;
0704 
0705     }
0706     return 0;
0707 }
0708 #endif /* CONFIG_PM_SLEEP */
0709 
0710 static const struct dev_pm_ops qcom_slim_dev_pm_ops = {
0711     SET_SYSTEM_SLEEP_PM_OPS(qcom_slim_suspend, qcom_slim_resume)
0712     SET_RUNTIME_PM_OPS(
0713                qcom_slim_runtime_suspend,
0714                qcom_slim_runtime_resume,
0715                NULL
0716     )
0717 };
0718 
0719 static const struct of_device_id qcom_slim_dt_match[] = {
0720     { .compatible = "qcom,slim", },
0721     { .compatible = "qcom,apq8064-slim", },
0722     {}
0723 };
0724 
0725 static struct platform_driver qcom_slim_driver = {
0726     .probe = qcom_slim_probe,
0727     .remove = qcom_slim_remove,
0728     .driver = {
0729         .name = "qcom_slim_ctrl",
0730         .of_match_table = qcom_slim_dt_match,
0731         .pm = &qcom_slim_dev_pm_ops,
0732     },
0733 };
0734 module_platform_driver(qcom_slim_driver);
0735 
0736 MODULE_LICENSE("GPL v2");
0737 MODULE_DESCRIPTION("Qualcomm SLIMbus Controller");
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