sh/intc/core.c

0001 /*
0002  * Shared interrupt handling code for IPR and INTC2 types of IRQs.
0003  *
0004  * Copyright (C) 2007, 2008 Magnus Damm
0005  * Copyright (C) 2009 - 2012 Paul Mundt
0006  *
0007  * Based on intc2.c and ipr.c
0008  *
0009  * Copyright (C) 1999  Niibe Yutaka & Takeshi Yaegashi
0010  * Copyright (C) 2000  Kazumoto Kojima
0011  * Copyright (C) 2001  David J. Mckay (david.mckay@st.com)
0012  * Copyright (C) 2003  Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
0013  * Copyright (C) 2005, 2006  Paul Mundt
0014  *
0015  * This file is subject to the terms and conditions of the GNU General Public
0016  * License.  See the file "COPYING" in the main directory of this archive
0017  * for more details.
0018  */
0019 #define pr_fmt(fmt) "intc: " fmt
0020
0021 #include <linux/init.h>
0022 #include <linux/irq.h>
0023 #include <linux/io.h>
0024 #include <linux/slab.h>
0025 #include <linux/stat.h>
0026 #include <linux/interrupt.h>
0027 #include <linux/sh_intc.h>
0028 #include <linux/irqdomain.h>
0029 #include <linux/device.h>
0030 #include <linux/syscore_ops.h>
0031 #include <linux/list.h>
0032 #include <linux/spinlock.h>
0033 #include <linux/radix-tree.h>
0034 #include <linux/export.h>
0035 #include <linux/sort.h>
0036 #include "internals.h"
0037
0038 LIST_HEAD(intc_list);
0039 DEFINE_RAW_SPINLOCK(intc_big_lock);
0040 static unsigned int nr_intc_controllers;
0041
0042 /*
0043  * Default priority level
0044  * - this needs to be at least 2 for 5-bit priorities on 7780
0045  */
0046 static unsigned int default_prio_level = 2; /* 2 - 16 */
0047 static unsigned int intc_prio_level[INTC_NR_IRQS];  /* for now */
0048
0049 unsigned int intc_get_dfl_prio_level(void)
0050 {
0051     return default_prio_level;
0052 }
0053
0054 unsigned int intc_get_prio_level(unsigned int irq)
0055 {
0056     return intc_prio_level[irq];
0057 }
0058
0059 void intc_set_prio_level(unsigned int irq, unsigned int level)
0060 {
0061     unsigned long flags;
0062
0063     raw_spin_lock_irqsave(&intc_big_lock, flags);
0064     intc_prio_level[irq] = level;
0065     raw_spin_unlock_irqrestore(&intc_big_lock, flags);
0066 }
0067
0068 static void intc_redirect_irq(struct irq_desc *desc)
0069 {
0070     generic_handle_irq((unsigned int)irq_desc_get_handler_data(desc));
0071 }
0072
0073 static void __init intc_register_irq(struct intc_desc *desc,
0074                      struct intc_desc_int *d,
0075                      intc_enum enum_id,
0076                      unsigned int irq)
0077 {
0078     struct intc_handle_int *hp;
0079     struct irq_data *irq_data;
0080     unsigned int data[2], primary;
0081     unsigned long flags;
0082
0083     raw_spin_lock_irqsave(&intc_big_lock, flags);
0084     radix_tree_insert(&d->tree, enum_id, intc_irq_xlate_get(irq));
0085     raw_spin_unlock_irqrestore(&intc_big_lock, flags);
0086
0087     /*
0088      * Prefer single interrupt source bitmap over other combinations:
0089      *
0090      * 1. bitmap, single interrupt source
0091      * 2. priority, single interrupt source
0092      * 3. bitmap, multiple interrupt sources (groups)
0093      * 4. priority, multiple interrupt sources (groups)
0094      */
0095     data[0] = intc_get_mask_handle(desc, d, enum_id, 0);
0096     data[1] = intc_get_prio_handle(desc, d, enum_id, 0);
0097
0098     primary = 0;
0099     if (!data[0] && data[1])
0100         primary = 1;
0101
0102     if (!data[0] && !data[1])
0103         pr_warn("missing unique irq mask for irq %d (vect 0x%04x)\n",
0104             irq, irq2evt(irq));
0105
0106     data[0] = data[0] ? data[0] : intc_get_mask_handle(desc, d, enum_id, 1);
0107     data[1] = data[1] ? data[1] : intc_get_prio_handle(desc, d, enum_id, 1);
0108
0109     if (!data[primary])
0110         primary ^= 1;
0111
0112     BUG_ON(!data[primary]); /* must have primary masking method */
0113
0114     irq_data = irq_get_irq_data(irq);
0115
0116     disable_irq_nosync(irq);
0117     irq_set_chip_and_handler_name(irq, &d->chip, handle_level_irq,
0118                       "level");
0119     irq_set_chip_data(irq, (void *)data[primary]);
0120
0121     /*
0122      * set priority level
0123      */
0124     intc_set_prio_level(irq, intc_get_dfl_prio_level());
0125
0126     /* enable secondary masking method if present */
0127     if (data[!primary])
0128         _intc_enable(irq_data, data[!primary]);
0129
0130     /* add irq to d->prio list if priority is available */
0131     if (data[1]) {
0132         hp = d->prio + d->nr_prio;
0133         hp->irq = irq;
0134         hp->handle = data[1];
0135
0136         if (primary) {
0137             /*
0138              * only secondary priority should access registers, so
0139              * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
0140              */
0141             hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
0142             hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
0143         }
0144         d->nr_prio++;
0145     }
0146
0147     /* add irq to d->sense list if sense is available */
0148     data[0] = intc_get_sense_handle(desc, d, enum_id);
0149     if (data[0]) {
0150         (d->sense + d->nr_sense)->irq = irq;
0151         (d->sense + d->nr_sense)->handle = data[0];
0152         d->nr_sense++;
0153     }
0154
0155     /* irq should be disabled by default */
0156     d->chip.irq_mask(irq_data);
0157
0158     intc_set_ack_handle(irq, desc, d, enum_id);
0159     intc_set_dist_handle(irq, desc, d, enum_id);
0160
0161     activate_irq(irq);
0162 }
0163
0164 static unsigned int __init save_reg(struct intc_desc_int *d,
0165                     unsigned int cnt,
0166                     unsigned long value,
0167                     unsigned int smp)
0168 {
0169     if (value) {
0170         value = intc_phys_to_virt(d, value);
0171
0172         d->reg[cnt] = value;
0173 #ifdef CONFIG_SMP
0174         d->smp[cnt] = smp;
0175 #endif
0176         return 1;
0177     }
0178
0179     return 0;
0180 }
0181
0182 static bool __init intc_map(struct irq_domain *domain, int irq)
0183 {
0184     if (!irq_to_desc(irq) && irq_alloc_desc_at(irq, NUMA_NO_NODE) != irq) {
0185         pr_err("uname to allocate IRQ %d\n", irq);
0186         return false;
0187     }
0188
0189     if (irq_domain_associate(domain, irq, irq)) {
0190         pr_err("domain association failure\n");
0191         return false;
0192     }
0193
0194     return true;
0195 }
0196
0197 int __init register_intc_controller(struct intc_desc *desc)
0198 {
0199     unsigned int i, k, smp;
0200     struct intc_hw_desc *hw = &desc->hw;
0201     struct intc_desc_int *d;
0202     struct resource *res;
0203
0204     pr_info("Registered controller '%s' with %u IRQs\n",
0205         desc->name, hw->nr_vectors);
0206
0207     d = kzalloc(sizeof(*d), GFP_NOWAIT);
0208     if (!d)
0209         goto err0;
0210
0211     INIT_LIST_HEAD(&d->list);
0212     list_add_tail(&d->list, &intc_list);
0213
0214     raw_spin_lock_init(&d->lock);
0215     INIT_RADIX_TREE(&d->tree, GFP_ATOMIC);
0216
0217     d->index = nr_intc_controllers;
0218
0219     if (desc->num_resources) {
0220         d->nr_windows = desc->num_resources;
0221         d->window = kcalloc(d->nr_windows, sizeof(*d->window),
0222                     GFP_NOWAIT);
0223         if (!d->window)
0224             goto err1;
0225
0226         for (k = 0; k < d->nr_windows; k++) {
0227             res = desc->resource + k;
0228             WARN_ON(resource_type(res) != IORESOURCE_MEM);
0229             d->window[k].phys = res->start;
0230             d->window[k].size = resource_size(res);
0231             d->window[k].virt = ioremap(res->start,
0232                             resource_size(res));
0233             if (!d->window[k].virt)
0234                 goto err2;
0235         }
0236     }
0237
0238     d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
0239 #ifdef CONFIG_INTC_BALANCING
0240     if (d->nr_reg)
0241         d->nr_reg += hw->nr_mask_regs;
0242 #endif
0243     d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
0244     d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
0245     d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
0246     d->nr_reg += hw->subgroups ? hw->nr_subgroups : 0;
0247
0248     d->reg = kcalloc(d->nr_reg, sizeof(*d->reg), GFP_NOWAIT);
0249     if (!d->reg)
0250         goto err2;
0251
0252 #ifdef CONFIG_SMP
0253     d->smp = kcalloc(d->nr_reg, sizeof(*d->smp), GFP_NOWAIT);
0254     if (!d->smp)
0255         goto err3;
0256 #endif
0257     k = 0;
0258
0259     if (hw->mask_regs) {
0260         for (i = 0; i < hw->nr_mask_regs; i++) {
0261             smp = IS_SMP(hw->mask_regs[i]);
0262             k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
0263             k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
0264 #ifdef CONFIG_INTC_BALANCING
0265             k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0);
0266 #endif
0267         }
0268     }
0269
0270     if (hw->prio_regs) {
0271         d->prio = kcalloc(hw->nr_vectors, sizeof(*d->prio),
0272                   GFP_NOWAIT);
0273         if (!d->prio)
0274             goto err4;
0275
0276         for (i = 0; i < hw->nr_prio_regs; i++) {
0277             smp = IS_SMP(hw->prio_regs[i]);
0278             k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
0279             k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
0280         }
0281
0282         sort(d->prio, hw->nr_prio_regs, sizeof(*d->prio),
0283              intc_handle_int_cmp, NULL);
0284     }
0285
0286     if (hw->sense_regs) {
0287         d->sense = kcalloc(hw->nr_vectors, sizeof(*d->sense),
0288                    GFP_NOWAIT);
0289         if (!d->sense)
0290             goto err5;
0291
0292         for (i = 0; i < hw->nr_sense_regs; i++)
0293             k += save_reg(d, k, hw->sense_regs[i].reg, 0);
0294
0295         sort(d->sense, hw->nr_sense_regs, sizeof(*d->sense),
0296              intc_handle_int_cmp, NULL);
0297     }
0298
0299     if (hw->subgroups)
0300         for (i = 0; i < hw->nr_subgroups; i++)
0301             if (hw->subgroups[i].reg)
0302                 k+= save_reg(d, k, hw->subgroups[i].reg, 0);
0303
0304     memcpy(&d->chip, &intc_irq_chip, sizeof(struct irq_chip));
0305     d->chip.name = desc->name;
0306
0307     if (hw->ack_regs)
0308         for (i = 0; i < hw->nr_ack_regs; i++)
0309             k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
0310     else
0311         d->chip.irq_mask_ack = d->chip.irq_disable;
0312
0313     /* disable bits matching force_disable before registering irqs */
0314     if (desc->force_disable)
0315         intc_enable_disable_enum(desc, d, desc->force_disable, 0);
0316
0317     /* disable bits matching force_enable before registering irqs */
0318     if (desc->force_enable)
0319         intc_enable_disable_enum(desc, d, desc->force_enable, 0);
0320
0321     BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
0322
0323     intc_irq_domain_init(d, hw);
0324
0325     /* register the vectors one by one */
0326     for (i = 0; i < hw->nr_vectors; i++) {
0327         struct intc_vect *vect = hw->vectors + i;
0328         unsigned int irq = evt2irq(vect->vect);
0329
0330         if (!vect->enum_id)
0331             continue;
0332
0333         if (!intc_map(d->domain, irq))
0334             continue;
0335
0336         intc_irq_xlate_set(irq, vect->enum_id, d);
0337         intc_register_irq(desc, d, vect->enum_id, irq);
0338
0339         for (k = i + 1; k < hw->nr_vectors; k++) {
0340             struct intc_vect *vect2 = hw->vectors + k;
0341             unsigned int irq2 = evt2irq(vect2->vect);
0342
0343             if (vect->enum_id != vect2->enum_id)
0344                 continue;
0345
0346             /*
0347              * In the case of multi-evt handling and sparse
0348              * IRQ support, each vector still needs to have
0349              * its own backing irq_desc.
0350              */
0351             if (!intc_map(d->domain, irq2))
0352                 continue;
0353
0354             vect2->enum_id = 0;
0355
0356             /* redirect this interrupts to the first one */
0357             irq_set_chip(irq2, &dummy_irq_chip);
0358             irq_set_chained_handler_and_data(irq2,
0359                              intc_redirect_irq,
0360                              (void *)irq);
0361         }
0362     }
0363
0364     intc_subgroup_init(desc, d);
0365
0366     /* enable bits matching force_enable after registering irqs */
0367     if (desc->force_enable)
0368         intc_enable_disable_enum(desc, d, desc->force_enable, 1);
0369
0370     d->skip_suspend = desc->skip_syscore_suspend;
0371
0372     nr_intc_controllers++;
0373
0374     return 0;
0375 err5:
0376     kfree(d->prio);
0377 err4:
0378 #ifdef CONFIG_SMP
0379     kfree(d->smp);
0380 err3:
0381 #endif
0382     kfree(d->reg);
0383 err2:
0384     for (k = 0; k < d->nr_windows; k++)
0385         if (d->window[k].virt)
0386             iounmap(d->window[k].virt);
0387
0388     kfree(d->window);
0389 err1:
0390     kfree(d);
0391 err0:
0392     pr_err("unable to allocate INTC memory\n");
0393
0394     return -ENOMEM;
0395 }
0396
0397 static int intc_suspend(void)
0398 {
0399     struct intc_desc_int *d;
0400
0401     list_for_each_entry(d, &intc_list, list) {
0402         int irq;
0403
0404         if (d->skip_suspend)
0405             continue;
0406
0407         /* enable wakeup irqs belonging to this intc controller */
0408         for_each_active_irq(irq) {
0409             struct irq_data *data;
0410             struct irq_chip *chip;
0411
0412             data = irq_get_irq_data(irq);
0413             chip = irq_data_get_irq_chip(data);
0414             if (chip != &d->chip)
0415                 continue;
0416             if (irqd_is_wakeup_set(data))
0417                 chip->irq_enable(data);
0418         }
0419     }
0420     return 0;
0421 }
0422
0423 static void intc_resume(void)
0424 {
0425     struct intc_desc_int *d;
0426
0427     list_for_each_entry(d, &intc_list, list) {
0428         int irq;
0429
0430         if (d->skip_suspend)
0431             continue;
0432
0433         for_each_active_irq(irq) {
0434             struct irq_data *data;
0435             struct irq_chip *chip;
0436
0437             data = irq_get_irq_data(irq);
0438             chip = irq_data_get_irq_chip(data);
0439             /*
0440              * This will catch the redirect and VIRQ cases
0441              * due to the dummy_irq_chip being inserted.
0442              */
0443             if (chip != &d->chip)
0444                 continue;
0445             if (irqd_irq_disabled(data))
0446                 chip->irq_disable(data);
0447             else
0448                 chip->irq_enable(data);
0449         }
0450     }
0451 }
0452
0453 struct syscore_ops intc_syscore_ops = {
0454     .suspend    = intc_suspend,
0455     .resume     = intc_resume,
0456 };
0457
0458 struct bus_type intc_subsys = {
0459     .name       = "intc",
0460     .dev_name   = "intc",
0461 };
0462
0463 static ssize_t
0464 show_intc_name(struct device *dev, struct device_attribute *attr, char *buf)
0465 {
0466     struct intc_desc_int *d;
0467
0468     d = container_of(dev, struct intc_desc_int, dev);
0469
0470     return sprintf(buf, "%s\n", d->chip.name);
0471 }
0472
0473 static DEVICE_ATTR(name, S_IRUGO, show_intc_name, NULL);
0474
0475 static int __init register_intc_devs(void)
0476 {
0477     struct intc_desc_int *d;
0478     int error;
0479
0480     register_syscore_ops(&intc_syscore_ops);
0481
0482     error = subsys_system_register(&intc_subsys, NULL);
0483     if (!error) {
0484         list_for_each_entry(d, &intc_list, list) {
0485             d->dev.id = d->index;
0486             d->dev.bus = &intc_subsys;
0487             error = device_register(&d->dev);
0488             if (error == 0)
0489                 error = device_create_file(&d->dev,
0490                                &dev_attr_name);
0491             if (error)
0492                 break;
0493         }
0494     }
0495
0496     if (error)
0497         pr_err("device registration error\n");
0498
0499     return error;
0500 }
0501 device_initcall(register_intc_devs);