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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * ESP front-end for Amiga ZORRO SCSI systems.
0004  *
0005  * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
0006  *
0007  * Copyright (C) 2011,2018 Michael Schmitz (schmitz@debian.org) for
0008  *               migration to ESP SCSI core
0009  *
0010  * Copyright (C) 2013 Tuomas Vainikka (tuomas.vainikka@aalto.fi) for
0011  *               Blizzard 1230 DMA and probe function fixes
0012  */
0013 /*
0014  * ZORRO bus code from:
0015  */
0016 /*
0017  * Detection routine for the NCR53c710 based Amiga SCSI Controllers for Linux.
0018  *      Amiga MacroSystemUS WarpEngine SCSI controller.
0019  *      Amiga Technologies/DKB A4091 SCSI controller.
0020  *
0021  * Written 1997 by Alan Hourihane <alanh@fairlite.demon.co.uk>
0022  * plus modifications of the 53c7xx.c driver to support the Amiga.
0023  *
0024  * Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
0025  */
0026 
0027 #define pr_fmt(fmt)        KBUILD_MODNAME ": " fmt
0028 
0029 #include <linux/module.h>
0030 #include <linux/init.h>
0031 #include <linux/interrupt.h>
0032 #include <linux/dma-mapping.h>
0033 #include <linux/scatterlist.h>
0034 #include <linux/delay.h>
0035 #include <linux/zorro.h>
0036 #include <linux/slab.h>
0037 #include <linux/pgtable.h>
0038 
0039 #include <asm/page.h>
0040 #include <asm/cacheflush.h>
0041 #include <asm/amigahw.h>
0042 #include <asm/amigaints.h>
0043 
0044 #include <scsi/scsi_host.h>
0045 #include <scsi/scsi_transport_spi.h>
0046 #include <scsi/scsi_device.h>
0047 #include <scsi/scsi_tcq.h>
0048 
0049 #include "esp_scsi.h"
0050 
0051 MODULE_AUTHOR("Michael Schmitz <schmitz@debian.org>");
0052 MODULE_DESCRIPTION("Amiga Zorro NCR5C9x (ESP) driver");
0053 MODULE_LICENSE("GPL");
0054 
0055 /* per-board register layout definitions */
0056 
0057 /* Blizzard 1230 DMA interface */
0058 
0059 struct blz1230_dma_registers {
0060     unsigned char dma_addr;     /* DMA address      [0x0000] */
0061     unsigned char dmapad2[0x7fff];
0062     unsigned char dma_latch;    /* DMA latch        [0x8000] */
0063 };
0064 
0065 /* Blizzard 1230II DMA interface */
0066 
0067 struct blz1230II_dma_registers {
0068     unsigned char dma_addr;     /* DMA address      [0x0000] */
0069     unsigned char dmapad2[0xf];
0070     unsigned char dma_latch;    /* DMA latch        [0x0010] */
0071 };
0072 
0073 /* Blizzard 2060 DMA interface */
0074 
0075 struct blz2060_dma_registers {
0076     unsigned char dma_led_ctrl; /* DMA led control   [0x000] */
0077     unsigned char dmapad1[0x0f];
0078     unsigned char dma_addr0;    /* DMA address (MSB) [0x010] */
0079     unsigned char dmapad2[0x03];
0080     unsigned char dma_addr1;    /* DMA address       [0x014] */
0081     unsigned char dmapad3[0x03];
0082     unsigned char dma_addr2;    /* DMA address       [0x018] */
0083     unsigned char dmapad4[0x03];
0084     unsigned char dma_addr3;    /* DMA address (LSB) [0x01c] */
0085 };
0086 
0087 /* DMA control bits */
0088 #define DMA_WRITE 0x80000000
0089 
0090 /* Cyberstorm DMA interface */
0091 
0092 struct cyber_dma_registers {
0093     unsigned char dma_addr0;    /* DMA address (MSB) [0x000] */
0094     unsigned char dmapad1[1];
0095     unsigned char dma_addr1;    /* DMA address       [0x002] */
0096     unsigned char dmapad2[1];
0097     unsigned char dma_addr2;    /* DMA address       [0x004] */
0098     unsigned char dmapad3[1];
0099     unsigned char dma_addr3;    /* DMA address (LSB) [0x006] */
0100     unsigned char dmapad4[0x3fb];
0101     unsigned char cond_reg;     /* DMA cond    (ro)  [0x402] */
0102 #define ctrl_reg  cond_reg      /* DMA control (wo)  [0x402] */
0103 };
0104 
0105 /* DMA control bits */
0106 #define CYBER_DMA_WRITE  0x40   /* DMA direction. 1 = write */
0107 #define CYBER_DMA_Z3     0x20   /* 16 (Z2) or 32 (CHIP/Z3) bit DMA transfer */
0108 
0109 /* DMA status bits */
0110 #define CYBER_DMA_HNDL_INTR 0x80    /* DMA IRQ pending? */
0111 
0112 /* The CyberStorm II DMA interface */
0113 struct cyberII_dma_registers {
0114     unsigned char cond_reg;     /* DMA cond    (ro)  [0x000] */
0115 #define ctrl_reg  cond_reg      /* DMA control (wo)  [0x000] */
0116     unsigned char dmapad4[0x3f];
0117     unsigned char dma_addr0;    /* DMA address (MSB) [0x040] */
0118     unsigned char dmapad1[3];
0119     unsigned char dma_addr1;    /* DMA address       [0x044] */
0120     unsigned char dmapad2[3];
0121     unsigned char dma_addr2;    /* DMA address       [0x048] */
0122     unsigned char dmapad3[3];
0123     unsigned char dma_addr3;    /* DMA address (LSB) [0x04c] */
0124 };
0125 
0126 /* Fastlane DMA interface */
0127 
0128 struct fastlane_dma_registers {
0129     unsigned char cond_reg;     /* DMA status  (ro) [0x0000] */
0130 #define ctrl_reg  cond_reg      /* DMA control (wo) [0x0000] */
0131     char dmapad1[0x3f];
0132     unsigned char clear_strobe; /* DMA clear   (wo) [0x0040] */
0133 };
0134 
0135 /*
0136  * The controller registers can be found in the Z2 config area at these
0137  * offsets:
0138  */
0139 #define FASTLANE_ESP_ADDR   0x1000001
0140 
0141 /* DMA status bits */
0142 #define FASTLANE_DMA_MINT   0x80
0143 #define FASTLANE_DMA_IACT   0x40
0144 #define FASTLANE_DMA_CREQ   0x20
0145 
0146 /* DMA control bits */
0147 #define FASTLANE_DMA_FCODE  0xa0
0148 #define FASTLANE_DMA_MASK   0xf3
0149 #define FASTLANE_DMA_WRITE  0x08    /* 1 = write */
0150 #define FASTLANE_DMA_ENABLE 0x04    /* Enable DMA */
0151 #define FASTLANE_DMA_EDI    0x02    /* Enable DMA IRQ ? */
0152 #define FASTLANE_DMA_ESI    0x01    /* Enable SCSI IRQ */
0153 
0154 /*
0155  * private data used for driver
0156  */
0157 struct zorro_esp_priv {
0158     struct esp *esp;        /* our ESP instance - for Scsi_host* */
0159     void __iomem *board_base;   /* virtual address (Zorro III board) */
0160     int zorro3;         /* board is Zorro III */
0161     unsigned char ctrl_data;    /* shadow copy of ctrl_reg */
0162 };
0163 
0164 /*
0165  * On all implementations except for the Oktagon, padding between ESP
0166  * registers is three bytes.
0167  * On Oktagon, it is one byte - use a different accessor there.
0168  *
0169  * Oktagon needs PDMA - currently unsupported!
0170  */
0171 
0172 static void zorro_esp_write8(struct esp *esp, u8 val, unsigned long reg)
0173 {
0174     writeb(val, esp->regs + (reg * 4UL));
0175 }
0176 
0177 static u8 zorro_esp_read8(struct esp *esp, unsigned long reg)
0178 {
0179     return readb(esp->regs + (reg * 4UL));
0180 }
0181 
0182 static int zorro_esp_irq_pending(struct esp *esp)
0183 {
0184     /* check ESP status register; DMA has no status reg. */
0185     if (zorro_esp_read8(esp, ESP_STATUS) & ESP_STAT_INTR)
0186         return 1;
0187 
0188     return 0;
0189 }
0190 
0191 static int cyber_esp_irq_pending(struct esp *esp)
0192 {
0193     struct cyber_dma_registers __iomem *dregs = esp->dma_regs;
0194     unsigned char dma_status = readb(&dregs->cond_reg);
0195 
0196     /* It's important to check the DMA IRQ bit in the correct way! */
0197     return ((zorro_esp_read8(esp, ESP_STATUS) & ESP_STAT_INTR) &&
0198         (dma_status & CYBER_DMA_HNDL_INTR));
0199 }
0200 
0201 static int fastlane_esp_irq_pending(struct esp *esp)
0202 {
0203     struct fastlane_dma_registers __iomem *dregs = esp->dma_regs;
0204     unsigned char dma_status;
0205 
0206     dma_status = readb(&dregs->cond_reg);
0207 
0208     if (dma_status & FASTLANE_DMA_IACT)
0209         return 0;   /* not our IRQ */
0210 
0211     /* Return non-zero if ESP requested IRQ */
0212     return (
0213        (dma_status & FASTLANE_DMA_CREQ) &&
0214        (!(dma_status & FASTLANE_DMA_MINT)) &&
0215        (zorro_esp_read8(esp, ESP_STATUS) & ESP_STAT_INTR));
0216 }
0217 
0218 static u32 zorro_esp_dma_length_limit(struct esp *esp, u32 dma_addr,
0219                     u32 dma_len)
0220 {
0221     return dma_len > (1U << 16) ? (1U << 16) : dma_len;
0222 }
0223 
0224 static u32 fastlane_esp_dma_length_limit(struct esp *esp, u32 dma_addr,
0225                     u32 dma_len)
0226 {
0227     /* The old driver used 0xfffc as limit, so do that here too */
0228     return dma_len > 0xfffc ? 0xfffc : dma_len;
0229 }
0230 
0231 static void zorro_esp_reset_dma(struct esp *esp)
0232 {
0233     /* nothing to do here */
0234 }
0235 
0236 static void zorro_esp_dma_drain(struct esp *esp)
0237 {
0238     /* nothing to do here */
0239 }
0240 
0241 static void zorro_esp_dma_invalidate(struct esp *esp)
0242 {
0243     /* nothing to do here */
0244 }
0245 
0246 static void fastlane_esp_dma_invalidate(struct esp *esp)
0247 {
0248     struct zorro_esp_priv *zep = dev_get_drvdata(esp->dev);
0249     struct fastlane_dma_registers __iomem *dregs = esp->dma_regs;
0250     unsigned char *ctrl_data = &zep->ctrl_data;
0251 
0252     *ctrl_data = (*ctrl_data & FASTLANE_DMA_MASK);
0253     writeb(0, &dregs->clear_strobe);
0254     z_writel(0, zep->board_base);
0255 }
0256 
0257 /* Blizzard 1230/60 SCSI-IV DMA */
0258 
0259 static void zorro_esp_send_blz1230_dma_cmd(struct esp *esp, u32 addr,
0260             u32 esp_count, u32 dma_count, int write, u8 cmd)
0261 {
0262     struct blz1230_dma_registers __iomem *dregs = esp->dma_regs;
0263     u8 phase = esp->sreg & ESP_STAT_PMASK;
0264 
0265     /*
0266      * Use PIO if transferring message bytes to esp->command_block_dma.
0267      * PIO requires a virtual address, so substitute esp->command_block
0268      * for addr.
0269      */
0270     if (phase == ESP_MIP && addr == esp->command_block_dma) {
0271         esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count,
0272                  dma_count, write, cmd);
0273         return;
0274     }
0275 
0276     /* Clear the results of a possible prior esp->ops->send_dma_cmd() */
0277     esp->send_cmd_error = 0;
0278     esp->send_cmd_residual = 0;
0279 
0280     if (write)
0281         /* DMA receive */
0282         dma_sync_single_for_device(esp->dev, addr, esp_count,
0283                 DMA_FROM_DEVICE);
0284     else
0285         /* DMA send */
0286         dma_sync_single_for_device(esp->dev, addr, esp_count,
0287                 DMA_TO_DEVICE);
0288 
0289     addr >>= 1;
0290     if (write)
0291         addr &= ~(DMA_WRITE);
0292     else
0293         addr |= DMA_WRITE;
0294 
0295     writeb((addr >> 24) & 0xff, &dregs->dma_latch);
0296     writeb((addr >> 24) & 0xff, &dregs->dma_addr);
0297     writeb((addr >> 16) & 0xff, &dregs->dma_addr);
0298     writeb((addr >>  8) & 0xff, &dregs->dma_addr);
0299     writeb(addr & 0xff, &dregs->dma_addr);
0300 
0301     scsi_esp_cmd(esp, ESP_CMD_DMA);
0302     zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0303     zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0304 
0305     scsi_esp_cmd(esp, cmd);
0306 }
0307 
0308 /* Blizzard 1230-II DMA */
0309 
0310 static void zorro_esp_send_blz1230II_dma_cmd(struct esp *esp, u32 addr,
0311             u32 esp_count, u32 dma_count, int write, u8 cmd)
0312 {
0313     struct blz1230II_dma_registers __iomem *dregs = esp->dma_regs;
0314     u8 phase = esp->sreg & ESP_STAT_PMASK;
0315 
0316     /* Use PIO if transferring message bytes to esp->command_block_dma */
0317     if (phase == ESP_MIP && addr == esp->command_block_dma) {
0318         esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count,
0319                  dma_count, write, cmd);
0320         return;
0321     }
0322 
0323     esp->send_cmd_error = 0;
0324     esp->send_cmd_residual = 0;
0325 
0326     if (write)
0327         /* DMA receive */
0328         dma_sync_single_for_device(esp->dev, addr, esp_count,
0329                 DMA_FROM_DEVICE);
0330     else
0331         /* DMA send */
0332         dma_sync_single_for_device(esp->dev, addr, esp_count,
0333                 DMA_TO_DEVICE);
0334 
0335     addr >>= 1;
0336     if (write)
0337         addr &= ~(DMA_WRITE);
0338     else
0339         addr |= DMA_WRITE;
0340 
0341     writeb((addr >> 24) & 0xff, &dregs->dma_latch);
0342     writeb((addr >> 16) & 0xff, &dregs->dma_addr);
0343     writeb((addr >>  8) & 0xff, &dregs->dma_addr);
0344     writeb(addr & 0xff, &dregs->dma_addr);
0345 
0346     scsi_esp_cmd(esp, ESP_CMD_DMA);
0347     zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0348     zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0349 
0350     scsi_esp_cmd(esp, cmd);
0351 }
0352 
0353 /* Blizzard 2060 DMA */
0354 
0355 static void zorro_esp_send_blz2060_dma_cmd(struct esp *esp, u32 addr,
0356             u32 esp_count, u32 dma_count, int write, u8 cmd)
0357 {
0358     struct blz2060_dma_registers __iomem *dregs = esp->dma_regs;
0359     u8 phase = esp->sreg & ESP_STAT_PMASK;
0360 
0361     /* Use PIO if transferring message bytes to esp->command_block_dma */
0362     if (phase == ESP_MIP && addr == esp->command_block_dma) {
0363         esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count,
0364                  dma_count, write, cmd);
0365         return;
0366     }
0367 
0368     esp->send_cmd_error = 0;
0369     esp->send_cmd_residual = 0;
0370 
0371     if (write)
0372         /* DMA receive */
0373         dma_sync_single_for_device(esp->dev, addr, esp_count,
0374                 DMA_FROM_DEVICE);
0375     else
0376         /* DMA send */
0377         dma_sync_single_for_device(esp->dev, addr, esp_count,
0378                 DMA_TO_DEVICE);
0379 
0380     addr >>= 1;
0381     if (write)
0382         addr &= ~(DMA_WRITE);
0383     else
0384         addr |= DMA_WRITE;
0385 
0386     writeb(addr & 0xff, &dregs->dma_addr3);
0387     writeb((addr >>  8) & 0xff, &dregs->dma_addr2);
0388     writeb((addr >> 16) & 0xff, &dregs->dma_addr1);
0389     writeb((addr >> 24) & 0xff, &dregs->dma_addr0);
0390 
0391     scsi_esp_cmd(esp, ESP_CMD_DMA);
0392     zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0393     zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0394 
0395     scsi_esp_cmd(esp, cmd);
0396 }
0397 
0398 /* Cyberstorm I DMA */
0399 
0400 static void zorro_esp_send_cyber_dma_cmd(struct esp *esp, u32 addr,
0401             u32 esp_count, u32 dma_count, int write, u8 cmd)
0402 {
0403     struct zorro_esp_priv *zep = dev_get_drvdata(esp->dev);
0404     struct cyber_dma_registers __iomem *dregs = esp->dma_regs;
0405     u8 phase = esp->sreg & ESP_STAT_PMASK;
0406     unsigned char *ctrl_data = &zep->ctrl_data;
0407 
0408     /* Use PIO if transferring message bytes to esp->command_block_dma */
0409     if (phase == ESP_MIP && addr == esp->command_block_dma) {
0410         esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count,
0411                  dma_count, write, cmd);
0412         return;
0413     }
0414 
0415     esp->send_cmd_error = 0;
0416     esp->send_cmd_residual = 0;
0417 
0418     zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0419     zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0420 
0421     if (write) {
0422         /* DMA receive */
0423         dma_sync_single_for_device(esp->dev, addr, esp_count,
0424                 DMA_FROM_DEVICE);
0425         addr &= ~(1);
0426     } else {
0427         /* DMA send */
0428         dma_sync_single_for_device(esp->dev, addr, esp_count,
0429                 DMA_TO_DEVICE);
0430         addr |= 1;
0431     }
0432 
0433     writeb((addr >> 24) & 0xff, &dregs->dma_addr0);
0434     writeb((addr >> 16) & 0xff, &dregs->dma_addr1);
0435     writeb((addr >>  8) & 0xff, &dregs->dma_addr2);
0436     writeb(addr & 0xff, &dregs->dma_addr3);
0437 
0438     if (write)
0439         *ctrl_data &= ~(CYBER_DMA_WRITE);
0440     else
0441         *ctrl_data |= CYBER_DMA_WRITE;
0442 
0443     *ctrl_data &= ~(CYBER_DMA_Z3);  /* Z2, do 16 bit DMA */
0444 
0445     writeb(*ctrl_data, &dregs->ctrl_reg);
0446 
0447     scsi_esp_cmd(esp, cmd);
0448 }
0449 
0450 /* Cyberstorm II DMA */
0451 
0452 static void zorro_esp_send_cyberII_dma_cmd(struct esp *esp, u32 addr,
0453             u32 esp_count, u32 dma_count, int write, u8 cmd)
0454 {
0455     struct cyberII_dma_registers __iomem *dregs = esp->dma_regs;
0456     u8 phase = esp->sreg & ESP_STAT_PMASK;
0457 
0458     /* Use PIO if transferring message bytes to esp->command_block_dma */
0459     if (phase == ESP_MIP && addr == esp->command_block_dma) {
0460         esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count,
0461                  dma_count, write, cmd);
0462         return;
0463     }
0464 
0465     esp->send_cmd_error = 0;
0466     esp->send_cmd_residual = 0;
0467 
0468     zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0469     zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0470 
0471     if (write) {
0472         /* DMA receive */
0473         dma_sync_single_for_device(esp->dev, addr, esp_count,
0474                 DMA_FROM_DEVICE);
0475         addr &= ~(1);
0476     } else {
0477         /* DMA send */
0478         dma_sync_single_for_device(esp->dev, addr, esp_count,
0479                 DMA_TO_DEVICE);
0480         addr |= 1;
0481     }
0482 
0483     writeb((addr >> 24) & 0xff, &dregs->dma_addr0);
0484     writeb((addr >> 16) & 0xff, &dregs->dma_addr1);
0485     writeb((addr >>  8) & 0xff, &dregs->dma_addr2);
0486     writeb(addr & 0xff, &dregs->dma_addr3);
0487 
0488     scsi_esp_cmd(esp, cmd);
0489 }
0490 
0491 /* Fastlane DMA */
0492 
0493 static void zorro_esp_send_fastlane_dma_cmd(struct esp *esp, u32 addr,
0494             u32 esp_count, u32 dma_count, int write, u8 cmd)
0495 {
0496     struct zorro_esp_priv *zep = dev_get_drvdata(esp->dev);
0497     struct fastlane_dma_registers __iomem *dregs = esp->dma_regs;
0498     u8 phase = esp->sreg & ESP_STAT_PMASK;
0499     unsigned char *ctrl_data = &zep->ctrl_data;
0500 
0501     /* Use PIO if transferring message bytes to esp->command_block_dma */
0502     if (phase == ESP_MIP && addr == esp->command_block_dma) {
0503         esp_send_pio_cmd(esp, (u32)esp->command_block, esp_count,
0504                  dma_count, write, cmd);
0505         return;
0506     }
0507 
0508     esp->send_cmd_error = 0;
0509     esp->send_cmd_residual = 0;
0510 
0511     zorro_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0512     zorro_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0513 
0514     if (write) {
0515         /* DMA receive */
0516         dma_sync_single_for_device(esp->dev, addr, esp_count,
0517                 DMA_FROM_DEVICE);
0518         addr &= ~(1);
0519     } else {
0520         /* DMA send */
0521         dma_sync_single_for_device(esp->dev, addr, esp_count,
0522                 DMA_TO_DEVICE);
0523         addr |= 1;
0524     }
0525 
0526     writeb(0, &dregs->clear_strobe);
0527     z_writel(addr, ((addr & 0x00ffffff) + zep->board_base));
0528 
0529     if (write) {
0530         *ctrl_data = (*ctrl_data & FASTLANE_DMA_MASK) |
0531                 FASTLANE_DMA_ENABLE;
0532     } else {
0533         *ctrl_data = ((*ctrl_data & FASTLANE_DMA_MASK) |
0534                 FASTLANE_DMA_ENABLE |
0535                 FASTLANE_DMA_WRITE);
0536     }
0537 
0538     writeb(*ctrl_data, &dregs->ctrl_reg);
0539 
0540     scsi_esp_cmd(esp, cmd);
0541 }
0542 
0543 static int zorro_esp_dma_error(struct esp *esp)
0544 {
0545     return esp->send_cmd_error;
0546 }
0547 
0548 /* per-board ESP driver ops */
0549 
0550 static const struct esp_driver_ops blz1230_esp_ops = {
0551     .esp_write8     = zorro_esp_write8,
0552     .esp_read8      = zorro_esp_read8,
0553     .irq_pending        = zorro_esp_irq_pending,
0554     .dma_length_limit   = zorro_esp_dma_length_limit,
0555     .reset_dma      = zorro_esp_reset_dma,
0556     .dma_drain      = zorro_esp_dma_drain,
0557     .dma_invalidate     = zorro_esp_dma_invalidate,
0558     .send_dma_cmd       = zorro_esp_send_blz1230_dma_cmd,
0559     .dma_error      = zorro_esp_dma_error,
0560 };
0561 
0562 static const struct esp_driver_ops blz1230II_esp_ops = {
0563     .esp_write8     = zorro_esp_write8,
0564     .esp_read8      = zorro_esp_read8,
0565     .irq_pending        = zorro_esp_irq_pending,
0566     .dma_length_limit   = zorro_esp_dma_length_limit,
0567     .reset_dma      = zorro_esp_reset_dma,
0568     .dma_drain      = zorro_esp_dma_drain,
0569     .dma_invalidate     = zorro_esp_dma_invalidate,
0570     .send_dma_cmd       = zorro_esp_send_blz1230II_dma_cmd,
0571     .dma_error      = zorro_esp_dma_error,
0572 };
0573 
0574 static const struct esp_driver_ops blz2060_esp_ops = {
0575     .esp_write8     = zorro_esp_write8,
0576     .esp_read8      = zorro_esp_read8,
0577     .irq_pending        = zorro_esp_irq_pending,
0578     .dma_length_limit   = zorro_esp_dma_length_limit,
0579     .reset_dma      = zorro_esp_reset_dma,
0580     .dma_drain      = zorro_esp_dma_drain,
0581     .dma_invalidate     = zorro_esp_dma_invalidate,
0582     .send_dma_cmd       = zorro_esp_send_blz2060_dma_cmd,
0583     .dma_error      = zorro_esp_dma_error,
0584 };
0585 
0586 static const struct esp_driver_ops cyber_esp_ops = {
0587     .esp_write8     = zorro_esp_write8,
0588     .esp_read8      = zorro_esp_read8,
0589     .irq_pending        = cyber_esp_irq_pending,
0590     .dma_length_limit   = zorro_esp_dma_length_limit,
0591     .reset_dma      = zorro_esp_reset_dma,
0592     .dma_drain      = zorro_esp_dma_drain,
0593     .dma_invalidate     = zorro_esp_dma_invalidate,
0594     .send_dma_cmd       = zorro_esp_send_cyber_dma_cmd,
0595     .dma_error      = zorro_esp_dma_error,
0596 };
0597 
0598 static const struct esp_driver_ops cyberII_esp_ops = {
0599     .esp_write8     = zorro_esp_write8,
0600     .esp_read8      = zorro_esp_read8,
0601     .irq_pending        = zorro_esp_irq_pending,
0602     .dma_length_limit   = zorro_esp_dma_length_limit,
0603     .reset_dma      = zorro_esp_reset_dma,
0604     .dma_drain      = zorro_esp_dma_drain,
0605     .dma_invalidate     = zorro_esp_dma_invalidate,
0606     .send_dma_cmd       = zorro_esp_send_cyberII_dma_cmd,
0607     .dma_error      = zorro_esp_dma_error,
0608 };
0609 
0610 static const struct esp_driver_ops fastlane_esp_ops = {
0611     .esp_write8     = zorro_esp_write8,
0612     .esp_read8      = zorro_esp_read8,
0613     .irq_pending        = fastlane_esp_irq_pending,
0614     .dma_length_limit   = fastlane_esp_dma_length_limit,
0615     .reset_dma      = zorro_esp_reset_dma,
0616     .dma_drain      = zorro_esp_dma_drain,
0617     .dma_invalidate     = fastlane_esp_dma_invalidate,
0618     .send_dma_cmd       = zorro_esp_send_fastlane_dma_cmd,
0619     .dma_error      = zorro_esp_dma_error,
0620 };
0621 
0622 /* Zorro driver config data */
0623 
0624 struct zorro_driver_data {
0625     const char *name;
0626     unsigned long offset;
0627     unsigned long dma_offset;
0628     int absolute;   /* offset is absolute address */
0629     int scsi_option;
0630     const struct esp_driver_ops *esp_ops;
0631 };
0632 
0633 /* board types */
0634 
0635 enum {
0636     ZORRO_BLZ1230,
0637     ZORRO_BLZ1230II,
0638     ZORRO_BLZ2060,
0639     ZORRO_CYBER,
0640     ZORRO_CYBERII,
0641     ZORRO_FASTLANE,
0642 };
0643 
0644 /* per-board config data */
0645 
0646 static const struct zorro_driver_data zorro_esp_boards[] = {
0647     [ZORRO_BLZ1230] = {
0648                 .name       = "Blizzard 1230",
0649                 .offset     = 0x8000,
0650                 .dma_offset = 0x10000,
0651                 .scsi_option    = 1,
0652                 .esp_ops    = &blz1230_esp_ops,
0653     },
0654     [ZORRO_BLZ1230II] = {
0655                 .name       = "Blizzard 1230II",
0656                 .offset     = 0x10000,
0657                 .dma_offset = 0x10021,
0658                 .scsi_option    = 1,
0659                 .esp_ops    = &blz1230II_esp_ops,
0660     },
0661     [ZORRO_BLZ2060] = {
0662                 .name       = "Blizzard 2060",
0663                 .offset     = 0x1ff00,
0664                 .dma_offset = 0x1ffe0,
0665                 .esp_ops    = &blz2060_esp_ops,
0666     },
0667     [ZORRO_CYBER] = {
0668                 .name       = "CyberStormI",
0669                 .offset     = 0xf400,
0670                 .dma_offset = 0xf800,
0671                 .esp_ops    = &cyber_esp_ops,
0672     },
0673     [ZORRO_CYBERII] = {
0674                 .name       = "CyberStormII",
0675                 .offset     = 0x1ff03,
0676                 .dma_offset = 0x1ff43,
0677                 .scsi_option    = 1,
0678                 .esp_ops    = &cyberII_esp_ops,
0679     },
0680     [ZORRO_FASTLANE] = {
0681                 .name       = "Fastlane",
0682                 .offset     = 0x1000001,
0683                 .dma_offset = 0x1000041,
0684                 .esp_ops    = &fastlane_esp_ops,
0685     },
0686 };
0687 
0688 static const struct zorro_device_id zorro_esp_zorro_tbl[] = {
0689     {   /* Blizzard 1230 IV */
0690         .id = ZORRO_ID(PHASE5, 0x11, 0),
0691         .driver_data = ZORRO_BLZ1230,
0692     },
0693     {   /* Blizzard 1230 II (Zorro II) or Fastlane (Zorro III) */
0694         .id = ZORRO_ID(PHASE5, 0x0B, 0),
0695         .driver_data = ZORRO_BLZ1230II,
0696     },
0697     {   /* Blizzard 2060 */
0698         .id = ZORRO_ID(PHASE5, 0x18, 0),
0699         .driver_data = ZORRO_BLZ2060,
0700     },
0701     {   /* Cyberstorm */
0702         .id = ZORRO_ID(PHASE5, 0x0C, 0),
0703         .driver_data = ZORRO_CYBER,
0704     },
0705     {   /* Cyberstorm II */
0706         .id = ZORRO_ID(PHASE5, 0x19, 0),
0707         .driver_data = ZORRO_CYBERII,
0708     },
0709     { 0 }
0710 };
0711 MODULE_DEVICE_TABLE(zorro, zorro_esp_zorro_tbl);
0712 
0713 static int zorro_esp_probe(struct zorro_dev *z,
0714                        const struct zorro_device_id *ent)
0715 {
0716     struct scsi_host_template *tpnt = &scsi_esp_template;
0717     struct Scsi_Host *host;
0718     struct esp *esp;
0719     const struct zorro_driver_data *zdd;
0720     struct zorro_esp_priv *zep;
0721     unsigned long board, ioaddr, dmaaddr;
0722     int err;
0723 
0724     board = zorro_resource_start(z);
0725     zdd = &zorro_esp_boards[ent->driver_data];
0726 
0727     pr_info("%s found at address 0x%lx.\n", zdd->name, board);
0728 
0729     zep = kzalloc(sizeof(*zep), GFP_KERNEL);
0730     if (!zep) {
0731         pr_err("Can't allocate device private data!\n");
0732         return -ENOMEM;
0733     }
0734 
0735     /* let's figure out whether we have a Zorro II or Zorro III board */
0736     if ((z->rom.er_Type & ERT_TYPEMASK) == ERT_ZORROIII) {
0737         if (board > 0xffffff)
0738             zep->zorro3 = 1;
0739     } else {
0740         /*
0741          * Even though most of these boards identify as Zorro II,
0742          * they are in fact CPU expansion slot boards and have full
0743          * access to all of memory. Fix up DMA bitmask here.
0744          */
0745         z->dev.coherent_dma_mask = DMA_BIT_MASK(32);
0746     }
0747 
0748     /*
0749      * If Zorro III and ID matches Fastlane, our device table entry
0750      * contains data for the Blizzard 1230 II board which does share the
0751      * same ID. Fix up device table entry here.
0752      * TODO: Some Cyberstom060 boards also share this ID but would need
0753      * to use the Cyberstorm I driver data ... we catch this by checking
0754      * for presence of ESP chip later, but don't try to fix up yet.
0755      */
0756     if (zep->zorro3 && ent->driver_data == ZORRO_BLZ1230II) {
0757         pr_info("%s at address 0x%lx is Fastlane Z3, fixing data!\n",
0758             zdd->name, board);
0759         zdd = &zorro_esp_boards[ZORRO_FASTLANE];
0760     }
0761 
0762     if (zdd->absolute) {
0763         ioaddr  = zdd->offset;
0764         dmaaddr = zdd->dma_offset;
0765     } else {
0766         ioaddr  = board + zdd->offset;
0767         dmaaddr = board + zdd->dma_offset;
0768     }
0769 
0770     if (!zorro_request_device(z, zdd->name)) {
0771         pr_err("cannot reserve region 0x%lx, abort\n",
0772                board);
0773         err = -EBUSY;
0774         goto fail_free_zep;
0775     }
0776 
0777     host = scsi_host_alloc(tpnt, sizeof(struct esp));
0778 
0779     if (!host) {
0780         pr_err("No host detected; board configuration problem?\n");
0781         err = -ENOMEM;
0782         goto fail_release_device;
0783     }
0784 
0785     host->base      = ioaddr;
0786     host->this_id       = 7;
0787 
0788     esp         = shost_priv(host);
0789     esp->host       = host;
0790     esp->dev        = &z->dev;
0791 
0792     esp->scsi_id        = host->this_id;
0793     esp->scsi_id_mask   = (1 << esp->scsi_id);
0794 
0795     esp->cfreq = 40000000;
0796 
0797     zep->esp = esp;
0798 
0799     dev_set_drvdata(esp->dev, zep);
0800 
0801     /* additional setup required for Fastlane */
0802     if (zep->zorro3 && ent->driver_data == ZORRO_BLZ1230II) {
0803         /* map full address space up to ESP base for DMA */
0804         zep->board_base = ioremap(board, FASTLANE_ESP_ADDR - 1);
0805         if (!zep->board_base) {
0806             pr_err("Cannot allocate board address space\n");
0807             err = -ENOMEM;
0808             goto fail_free_host;
0809         }
0810         /* initialize DMA control shadow register */
0811         zep->ctrl_data = (FASTLANE_DMA_FCODE |
0812                   FASTLANE_DMA_EDI | FASTLANE_DMA_ESI);
0813     }
0814 
0815     esp->ops = zdd->esp_ops;
0816 
0817     if (ioaddr > 0xffffff)
0818         esp->regs = ioremap(ioaddr, 0x20);
0819     else
0820         /* ZorroII address space remapped nocache by early startup */
0821         esp->regs = ZTWO_VADDR(ioaddr);
0822 
0823     if (!esp->regs) {
0824         err = -ENOMEM;
0825         goto fail_unmap_fastlane;
0826     }
0827 
0828     esp->fifo_reg = esp->regs + ESP_FDATA * 4;
0829 
0830     /* Check whether a Blizzard 12x0 or CyberstormII really has SCSI */
0831     if (zdd->scsi_option) {
0832         zorro_esp_write8(esp, (ESP_CONFIG1_PENABLE | 7), ESP_CFG1);
0833         if (zorro_esp_read8(esp, ESP_CFG1) != (ESP_CONFIG1_PENABLE|7)) {
0834             err = -ENODEV;
0835             goto fail_unmap_regs;
0836         }
0837     }
0838 
0839     if (zep->zorro3) {
0840         /*
0841          * Only Fastlane Z3 for now - add switch for correct struct
0842          * dma_registers size if adding any more
0843          */
0844         esp->dma_regs = ioremap(dmaaddr,
0845                     sizeof(struct fastlane_dma_registers));
0846     } else
0847         /* ZorroII address space remapped nocache by early startup */
0848         esp->dma_regs = ZTWO_VADDR(dmaaddr);
0849 
0850     if (!esp->dma_regs) {
0851         err = -ENOMEM;
0852         goto fail_unmap_regs;
0853     }
0854 
0855     esp->command_block = dma_alloc_coherent(esp->dev, 16,
0856                         &esp->command_block_dma,
0857                         GFP_KERNEL);
0858 
0859     if (!esp->command_block) {
0860         err = -ENOMEM;
0861         goto fail_unmap_dma_regs;
0862     }
0863 
0864     host->irq = IRQ_AMIGA_PORTS;
0865     err = request_irq(host->irq, scsi_esp_intr, IRQF_SHARED,
0866               "Amiga Zorro ESP", esp);
0867     if (err < 0) {
0868         err = -ENODEV;
0869         goto fail_free_command_block;
0870     }
0871 
0872     /* register the chip */
0873     err = scsi_esp_register(esp);
0874 
0875     if (err) {
0876         err = -ENOMEM;
0877         goto fail_free_irq;
0878     }
0879 
0880     return 0;
0881 
0882 fail_free_irq:
0883     free_irq(host->irq, esp);
0884 
0885 fail_free_command_block:
0886     dma_free_coherent(esp->dev, 16,
0887               esp->command_block,
0888               esp->command_block_dma);
0889 
0890 fail_unmap_dma_regs:
0891     if (zep->zorro3)
0892         iounmap(esp->dma_regs);
0893 
0894 fail_unmap_regs:
0895     if (ioaddr > 0xffffff)
0896         iounmap(esp->regs);
0897 
0898 fail_unmap_fastlane:
0899     if (zep->zorro3)
0900         iounmap(zep->board_base);
0901 
0902 fail_free_host:
0903     scsi_host_put(host);
0904 
0905 fail_release_device:
0906     zorro_release_device(z);
0907 
0908 fail_free_zep:
0909     kfree(zep);
0910 
0911     return err;
0912 }
0913 
0914 static void zorro_esp_remove(struct zorro_dev *z)
0915 {
0916     struct zorro_esp_priv *zep = dev_get_drvdata(&z->dev);
0917     struct esp *esp = zep->esp;
0918     struct Scsi_Host *host = esp->host;
0919 
0920     scsi_esp_unregister(esp);
0921 
0922     free_irq(host->irq, esp);
0923     dma_free_coherent(esp->dev, 16,
0924               esp->command_block,
0925               esp->command_block_dma);
0926 
0927     if (zep->zorro3) {
0928         iounmap(zep->board_base);
0929         iounmap(esp->dma_regs);
0930     }
0931 
0932     if (host->base > 0xffffff)
0933         iounmap(esp->regs);
0934 
0935     scsi_host_put(host);
0936 
0937     zorro_release_device(z);
0938 
0939     kfree(zep);
0940 }
0941 
0942 static struct zorro_driver zorro_esp_driver = {
0943     .name     = KBUILD_MODNAME,
0944     .id_table = zorro_esp_zorro_tbl,
0945     .probe    = zorro_esp_probe,
0946     .remove   = zorro_esp_remove,
0947 };
0948 
0949 static int __init zorro_esp_scsi_init(void)
0950 {
0951     return zorro_register_driver(&zorro_esp_driver);
0952 }
0953 
0954 static void __exit zorro_esp_scsi_exit(void)
0955 {
0956     zorro_unregister_driver(&zorro_esp_driver);
0957 }
0958 
0959 module_init(zorro_esp_scsi_init);
0960 module_exit(zorro_esp_scsi_exit);
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