drivers/scsi/wd33c93.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *    wd33c93.h -  Linux device driver definitions for the
0004  *                 Commodore Amiga A2091/590 SCSI controller card
0005  *
0006  *    IMPORTANT: This file is for version 1.25 - 09/Jul/1997
0007  *
0008  * Copyright (c) 1996 John Shifflett, GeoLog Consulting
0009  *    john@geolog.com
0010  *    jshiffle@netcom.com
0011  */
0012 #ifndef WD33C93_H
0013 #define WD33C93_H
0014
0015
0016 #define PROC_INTERFACE     /* add code for /proc/scsi/wd33c93/xxx interface */
0017 #ifdef  PROC_INTERFACE
0018 #define PROC_STATISTICS    /* add code for keeping various real time stats */
0019 #endif
0020
0021 #define SYNC_DEBUG         /* extra info on sync negotiation printed */
0022 #define DEBUGGING_ON       /* enable command-line debugging bitmask */
0023 #define DEBUG_DEFAULTS 0   /* default debugging bitmask */
0024
0025
0026 #ifdef DEBUGGING_ON
0027 #define DB(f,a) if (hostdata->args & (f)) a;
0028 #else
0029 #define DB(f,a)
0030 #endif
0031
0032 #define uchar unsigned char
0033
0034
0035 /* wd register names */
0036 #define WD_OWN_ID    0x00
0037 #define WD_CONTROL      0x01
0038 #define WD_TIMEOUT_PERIOD  0x02
0039 #define WD_CDB_1     0x03
0040 #define WD_CDB_2     0x04
0041 #define WD_CDB_3     0x05
0042 #define WD_CDB_4     0x06
0043 #define WD_CDB_5     0x07
0044 #define WD_CDB_6     0x08
0045 #define WD_CDB_7     0x09
0046 #define WD_CDB_8     0x0a
0047 #define WD_CDB_9     0x0b
0048 #define WD_CDB_10    0x0c
0049 #define WD_CDB_11    0x0d
0050 #define WD_CDB_12    0x0e
0051 #define WD_TARGET_LUN      0x0f
0052 #define WD_COMMAND_PHASE   0x10
0053 #define WD_SYNCHRONOUS_TRANSFER 0x11
0054 #define WD_TRANSFER_COUNT_MSB 0x12
0055 #define WD_TRANSFER_COUNT  0x13
0056 #define WD_TRANSFER_COUNT_LSB 0x14
0057 #define WD_DESTINATION_ID  0x15
0058 #define WD_SOURCE_ID    0x16
0059 #define WD_SCSI_STATUS     0x17
0060 #define WD_COMMAND      0x18
0061 #define WD_DATA      0x19
0062 #define WD_QUEUE_TAG    0x1a
0063 #define WD_AUXILIARY_STATUS   0x1f
0064
0065 /* WD commands */
0066 #define WD_CMD_RESET    0x00
0067 #define WD_CMD_ABORT    0x01
0068 #define WD_CMD_ASSERT_ATN  0x02
0069 #define WD_CMD_NEGATE_ACK  0x03
0070 #define WD_CMD_DISCONNECT  0x04
0071 #define WD_CMD_RESELECT    0x05
0072 #define WD_CMD_SEL_ATN     0x06
0073 #define WD_CMD_SEL      0x07
0074 #define WD_CMD_SEL_ATN_XFER   0x08
0075 #define WD_CMD_SEL_XFER    0x09
0076 #define WD_CMD_RESEL_RECEIVE  0x0a
0077 #define WD_CMD_RESEL_SEND  0x0b
0078 #define WD_CMD_WAIT_SEL_RECEIVE 0x0c
0079 #define WD_CMD_TRANS_ADDR  0x18
0080 #define WD_CMD_TRANS_INFO  0x20
0081 #define WD_CMD_TRANSFER_PAD   0x21
0082 #define WD_CMD_SBT_MODE    0x80
0083
0084 /* ASR register */
0085 #define ASR_INT         (0x80)
0086 #define ASR_LCI         (0x40)
0087 #define ASR_BSY         (0x20)
0088 #define ASR_CIP         (0x10)
0089 #define ASR_PE          (0x02)
0090 #define ASR_DBR         (0x01)
0091
0092 /* SCSI Bus Phases */
0093 #define PHS_DATA_OUT    0x00
0094 #define PHS_DATA_IN     0x01
0095 #define PHS_COMMAND     0x02
0096 #define PHS_STATUS      0x03
0097 #define PHS_MESS_OUT    0x06
0098 #define PHS_MESS_IN     0x07
0099
0100 /* Command Status Register definitions */
0101
0102   /* reset state interrupts */
0103 #define CSR_RESET    0x00
0104 #define CSR_RESET_AF    0x01
0105
0106   /* successful completion interrupts */
0107 #define CSR_RESELECT    0x10
0108 #define CSR_SELECT      0x11
0109 #define CSR_SEL_XFER_DONE  0x16
0110 #define CSR_XFER_DONE      0x18
0111
0112   /* paused or aborted interrupts */
0113 #define CSR_MSGIN    0x20
0114 #define CSR_SDP         0x21
0115 #define CSR_SEL_ABORT      0x22
0116 #define CSR_RESEL_ABORT    0x25
0117 #define CSR_RESEL_ABORT_AM 0x27
0118 #define CSR_ABORT    0x28
0119
0120   /* terminated interrupts */
0121 #define CSR_INVALID     0x40
0122 #define CSR_UNEXP_DISC     0x41
0123 #define CSR_TIMEOUT     0x42
0124 #define CSR_PARITY      0x43
0125 #define CSR_PARITY_ATN     0x44
0126 #define CSR_BAD_STATUS     0x45
0127 #define CSR_UNEXP    0x48
0128
0129   /* service required interrupts */
0130 #define CSR_RESEL    0x80
0131 #define CSR_RESEL_AM    0x81
0132 #define CSR_DISC     0x85
0133 #define CSR_SRV_REQ     0x88
0134
0135    /* Own ID/CDB Size register */
0136 #define OWNID_EAF    0x08
0137 #define OWNID_EHP    0x10
0138 #define OWNID_RAF    0x20
0139 #define OWNID_FS_8   0x00
0140 #define OWNID_FS_12  0x40
0141 #define OWNID_FS_16  0x80
0142
0143    /* define these so we don't have to change a2091.c, etc. */
0144 #define WD33C93_FS_8_10  OWNID_FS_8
0145 #define WD33C93_FS_12_15 OWNID_FS_12
0146 #define WD33C93_FS_16_20 OWNID_FS_16
0147
0148    /* pass input-clock explicitly. accepted mhz values are 8-10,12-20 */
0149 #define WD33C93_FS_MHZ(mhz) (mhz)
0150
0151    /* Control register */
0152 #define CTRL_HSP     0x01
0153 #define CTRL_HA      0x02
0154 #define CTRL_IDI     0x04
0155 #define CTRL_EDI     0x08
0156 #define CTRL_HHP     0x10
0157 #define CTRL_POLLED  0x00
0158 #define CTRL_BURST   0x20
0159 #define CTRL_BUS     0x40
0160 #define CTRL_DMA     0x80
0161
0162    /* Timeout Period register */
0163 #define TIMEOUT_PERIOD_VALUE  20    /* 20 = 200 ms */
0164
0165    /* Synchronous Transfer Register */
0166 #define STR_FSS      0x80
0167
0168    /* Destination ID register */
0169 #define DSTID_DPD    0x40
0170 #define DATA_OUT_DIR 0
0171 #define DATA_IN_DIR  1
0172 #define DSTID_SCC    0x80
0173
0174    /* Source ID register */
0175 #define SRCID_MASK   0x07
0176 #define SRCID_SIV    0x08
0177 #define SRCID_DSP    0x20
0178 #define SRCID_ES     0x40
0179 #define SRCID_ER     0x80
0180
0181    /* This is what the 3393 chip looks like to us */
0182 typedef struct {
0183 #ifdef CONFIG_WD33C93_PIO
0184    unsigned int   SASR;
0185    unsigned int   SCMD;
0186 #else
0187    volatile unsigned char  *SASR;
0188    volatile unsigned char  *SCMD;
0189 #endif
0190 } wd33c93_regs;
0191
0192
0193 typedef int (*dma_setup_t) (struct scsi_cmnd *SCpnt, int dir_in);
0194 typedef void (*dma_stop_t) (struct Scsi_Host *instance,
0195         struct scsi_cmnd *SCpnt, int status);
0196
0197
0198 #define ILLEGAL_STATUS_BYTE   0xff
0199
0200 #define DEFAULT_SX_PER   376     /* (ns) fairly safe */
0201 #define DEFAULT_SX_OFF   0       /* aka async */
0202
0203 #define OPTIMUM_SX_PER   252     /* (ns) best we can do (mult-of-4) */
0204 #define OPTIMUM_SX_OFF   12      /* size of wd3393 fifo */
0205
0206 struct sx_period {
0207    unsigned int   period_ns;
0208    uchar          reg_value;
0209    };
0210
0211 /* FEF: defines for hostdata->dma_buffer_pool */
0212
0213 #define BUF_CHIP_ALLOCED 0
0214 #define BUF_SCSI_ALLOCED 1
0215
0216 struct WD33C93_hostdata {
0217     struct Scsi_Host *next;
0218     wd33c93_regs     regs;
0219     spinlock_t       lock;
0220     uchar            clock_freq;
0221     uchar            chip;             /* what kind of wd33c93? */
0222     uchar            microcode;        /* microcode rev */
0223     uchar            dma_buffer_pool;  /* FEF: buffer from chip_ram? */
0224     int              dma_dir;          /* data transfer dir. */
0225     dma_setup_t      dma_setup;
0226     dma_stop_t       dma_stop;
0227     unsigned int     dma_xfer_mask;
0228     uchar            *dma_bounce_buffer;
0229     unsigned int     dma_bounce_len;
0230     volatile uchar   busy[8];          /* index = target, bit = lun */
0231     volatile struct scsi_cmnd *input_Q;       /* commands waiting to be started */
0232     volatile struct scsi_cmnd *selecting;     /* trying to select this command */
0233     volatile struct scsi_cmnd *connected;     /* currently connected command */
0234     volatile struct scsi_cmnd *disconnected_Q;/* commands waiting for reconnect */
0235     uchar            state;            /* what we are currently doing */
0236     uchar            dma;              /* current state of DMA (on/off) */
0237     uchar            level2;           /* extent to which Level-2 commands are used */
0238     uchar            disconnect;       /* disconnect/reselect policy */
0239     unsigned int     args;             /* set from command-line argument */
0240     uchar            incoming_msg[8];  /* filled during message_in phase */
0241     int              incoming_ptr;     /* mainly used with EXTENDED messages */
0242     uchar            outgoing_msg[8];  /* send this during next message_out */
0243     int              outgoing_len;     /* length of outgoing message */
0244     unsigned int     default_sx_per;   /* default transfer period for SCSI bus */
0245     uchar            sync_xfer[8];     /* sync_xfer reg settings per target */
0246     uchar            sync_stat[8];     /* status of sync negotiation per target */
0247     uchar            no_sync;          /* bitmask: don't do sync on these targets */
0248     uchar            no_dma;           /* set this flag to disable DMA */
0249     uchar            dma_mode;         /* DMA Burst Mode or Single Byte DMA */
0250     uchar            fast;             /* set this flag to enable Fast SCSI */
0251     struct sx_period sx_table[9];      /* transfer periods for actual DTC-setting */
0252 #ifdef PROC_INTERFACE
0253     uchar            proc;             /* bitmask: what's in proc output */
0254 #ifdef PROC_STATISTICS
0255     unsigned long    cmd_cnt[8];       /* # of commands issued per target */
0256     unsigned long    int_cnt;          /* # of interrupts serviced */
0257     unsigned long    pio_cnt;          /* # of pio data transfers */
0258     unsigned long    dma_cnt;          /* # of DMA data transfers */
0259     unsigned long    disc_allowed_cnt[8]; /* # of disconnects allowed per target */
0260     unsigned long    disc_done_cnt[8]; /* # of disconnects done per target*/
0261 #endif
0262 #endif
0263     };
0264
0265 static inline struct scsi_pointer *WD33C93_scsi_pointer(struct scsi_cmnd *cmd)
0266 {
0267     return scsi_cmd_priv(cmd);
0268 }
0269
0270 /* defines for hostdata->chip */
0271
0272 #define C_WD33C93       0
0273 #define C_WD33C93A      1
0274 #define C_WD33C93B      2
0275 #define C_UNKNOWN_CHIP  100
0276
0277 /* defines for hostdata->state */
0278
0279 #define S_UNCONNECTED         0
0280 #define S_SELECTING           1
0281 #define S_RUNNING_LEVEL2      2
0282 #define S_CONNECTED           3
0283 #define S_PRE_TMP_DISC        4
0284 #define S_PRE_CMP_DISC        5
0285
0286 /* defines for hostdata->dma */
0287
0288 #define D_DMA_OFF          0
0289 #define D_DMA_RUNNING      1
0290
0291 /* defines for hostdata->level2 */
0292 /* NOTE: only the first 3 are implemented so far */
0293
0294 #define L2_NONE      1  /* no combination commands - we get lots of ints */
0295 #define L2_SELECT    2  /* start with SEL_ATN_XFER, but never resume it */
0296 #define L2_BASIC     3  /* resume after STATUS ints & RDP messages */
0297 #define L2_DATA      4  /* resume after DATA_IN/OUT ints */
0298 #define L2_MOST      5  /* resume after anything except a RESELECT int */
0299 #define L2_RESELECT  6  /* resume after everything, including RESELECT ints */
0300 #define L2_ALL       7  /* always resume */
0301
0302 /* defines for hostdata->disconnect */
0303
0304 #define DIS_NEVER    0
0305 #define DIS_ADAPTIVE 1
0306 #define DIS_ALWAYS   2
0307
0308 /* defines for hostdata->args */
0309
0310 #define DB_TEST1              1<<0
0311 #define DB_TEST2              1<<1
0312 #define DB_QUEUE_COMMAND      1<<2
0313 #define DB_EXECUTE            1<<3
0314 #define DB_INTR               1<<4
0315 #define DB_TRANSFER           1<<5
0316 #define DB_MASK               0x3f
0317
0318 /* defines for hostdata->sync_stat[] */
0319
0320 #define SS_UNSET     0
0321 #define SS_FIRST     1
0322 #define SS_WAITING   2
0323 #define SS_SET       3
0324
0325 /* defines for hostdata->proc */
0326
0327 #define PR_VERSION   1<<0
0328 #define PR_INFO      1<<1
0329 #define PR_STATISTICS 1<<2
0330 #define PR_CONNECTED 1<<3
0331 #define PR_INPUTQ    1<<4
0332 #define PR_DISCQ     1<<5
0333 #define PR_TEST      1<<6
0334 #define PR_STOP      1<<7
0335
0336
0337 void wd33c93_init (struct Scsi_Host *instance, const wd33c93_regs regs,
0338          dma_setup_t setup, dma_stop_t stop, int clock_freq);
0339 int wd33c93_abort (struct scsi_cmnd *cmd);
0340 int wd33c93_queuecommand (struct Scsi_Host *h, struct scsi_cmnd *cmd);
0341 void wd33c93_intr (struct Scsi_Host *instance);
0342 int wd33c93_show_info(struct seq_file *, struct Scsi_Host *);
0343 int wd33c93_write_info(struct Scsi_Host *, char *, int);
0344 int wd33c93_host_reset (struct scsi_cmnd *);
0345
0346 #endif /* WD33C93_H */