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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* sun_esp.c: ESP front-end for Sparc SBUS systems.
0003  *
0004  * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/types.h>
0009 #include <linux/delay.h>
0010 #include <linux/module.h>
0011 #include <linux/mm.h>
0012 #include <linux/init.h>
0013 #include <linux/dma-mapping.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/gfp.h>
0017 
0018 #include <asm/irq.h>
0019 #include <asm/io.h>
0020 #include <asm/dma.h>
0021 
0022 #include <scsi/scsi_host.h>
0023 
0024 #include "esp_scsi.h"
0025 
0026 #define DRV_MODULE_NAME     "sun_esp"
0027 #define PFX DRV_MODULE_NAME ": "
0028 #define DRV_VERSION     "1.100"
0029 #define DRV_MODULE_RELDATE  "August 27, 2008"
0030 
0031 #define dma_read32(REG) \
0032     sbus_readl(esp->dma_regs + (REG))
0033 #define dma_write32(VAL, REG) \
0034     sbus_writel((VAL), esp->dma_regs + (REG))
0035 
0036 /* DVMA chip revisions */
0037 enum dvma_rev {
0038     dvmarev0,
0039     dvmaesc1,
0040     dvmarev1,
0041     dvmarev2,
0042     dvmarev3,
0043     dvmarevplus,
0044     dvmahme
0045 };
0046 
0047 static int esp_sbus_setup_dma(struct esp *esp, struct platform_device *dma_of)
0048 {
0049     esp->dma = dma_of;
0050 
0051     esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
0052                    resource_size(&dma_of->resource[0]),
0053                    "espdma");
0054     if (!esp->dma_regs)
0055         return -ENOMEM;
0056 
0057     switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
0058     case DMA_VERS0:
0059         esp->dmarev = dvmarev0;
0060         break;
0061     case DMA_ESCV1:
0062         esp->dmarev = dvmaesc1;
0063         break;
0064     case DMA_VERS1:
0065         esp->dmarev = dvmarev1;
0066         break;
0067     case DMA_VERS2:
0068         esp->dmarev = dvmarev2;
0069         break;
0070     case DMA_VERHME:
0071         esp->dmarev = dvmahme;
0072         break;
0073     case DMA_VERSPLUS:
0074         esp->dmarev = dvmarevplus;
0075         break;
0076     }
0077 
0078     return 0;
0079 
0080 }
0081 
0082 static int esp_sbus_map_regs(struct esp *esp, int hme)
0083 {
0084     struct platform_device *op = to_platform_device(esp->dev);
0085     struct resource *res;
0086 
0087     /* On HME, two reg sets exist, first is DVMA,
0088      * second is ESP registers.
0089      */
0090     if (hme)
0091         res = &op->resource[1];
0092     else
0093         res = &op->resource[0];
0094 
0095     esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
0096     if (!esp->regs)
0097         return -ENOMEM;
0098 
0099     return 0;
0100 }
0101 
0102 static int esp_sbus_map_command_block(struct esp *esp)
0103 {
0104     esp->command_block = dma_alloc_coherent(esp->dev, 16,
0105                         &esp->command_block_dma,
0106                         GFP_KERNEL);
0107     if (!esp->command_block)
0108         return -ENOMEM;
0109     return 0;
0110 }
0111 
0112 static int esp_sbus_register_irq(struct esp *esp)
0113 {
0114     struct Scsi_Host *host = esp->host;
0115     struct platform_device *op = to_platform_device(esp->dev);
0116 
0117     host->irq = op->archdata.irqs[0];
0118     return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
0119 }
0120 
0121 static void esp_get_scsi_id(struct esp *esp, struct platform_device *espdma)
0122 {
0123     struct platform_device *op = to_platform_device(esp->dev);
0124     struct device_node *dp;
0125 
0126     dp = op->dev.of_node;
0127     esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
0128     if (esp->scsi_id != 0xff)
0129         goto done;
0130 
0131     esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
0132     if (esp->scsi_id != 0xff)
0133         goto done;
0134 
0135     esp->scsi_id = of_getintprop_default(espdma->dev.of_node,
0136                          "scsi-initiator-id", 7);
0137 
0138 done:
0139     esp->host->this_id = esp->scsi_id;
0140     esp->scsi_id_mask = (1 << esp->scsi_id);
0141 }
0142 
0143 static void esp_get_differential(struct esp *esp)
0144 {
0145     struct platform_device *op = to_platform_device(esp->dev);
0146     struct device_node *dp;
0147 
0148     dp = op->dev.of_node;
0149     if (of_find_property(dp, "differential", NULL))
0150         esp->flags |= ESP_FLAG_DIFFERENTIAL;
0151     else
0152         esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
0153 }
0154 
0155 static void esp_get_clock_params(struct esp *esp)
0156 {
0157     struct platform_device *op = to_platform_device(esp->dev);
0158     struct device_node *bus_dp, *dp;
0159     int fmhz;
0160 
0161     dp = op->dev.of_node;
0162     bus_dp = dp->parent;
0163 
0164     fmhz = of_getintprop_default(dp, "clock-frequency", 0);
0165     if (fmhz == 0)
0166         fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);
0167 
0168     esp->cfreq = fmhz;
0169 }
0170 
0171 static void esp_get_bursts(struct esp *esp, struct platform_device *dma_of)
0172 {
0173     struct device_node *dma_dp = dma_of->dev.of_node;
0174     struct platform_device *op = to_platform_device(esp->dev);
0175     struct device_node *dp;
0176     u8 bursts, val;
0177 
0178     dp = op->dev.of_node;
0179     bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
0180     val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
0181     if (val != 0xff)
0182         bursts &= val;
0183 
0184     val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
0185     if (val != 0xff)
0186         bursts &= val;
0187 
0188     if (bursts == 0xff ||
0189         (bursts & DMA_BURST16) == 0 ||
0190         (bursts & DMA_BURST32) == 0)
0191         bursts = (DMA_BURST32 - 1);
0192 
0193     esp->bursts = bursts;
0194 }
0195 
0196 static void esp_sbus_get_props(struct esp *esp, struct platform_device *espdma)
0197 {
0198     esp_get_scsi_id(esp, espdma);
0199     esp_get_differential(esp);
0200     esp_get_clock_params(esp);
0201     esp_get_bursts(esp, espdma);
0202 }
0203 
0204 static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
0205 {
0206     sbus_writeb(val, esp->regs + (reg * 4UL));
0207 }
0208 
0209 static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
0210 {
0211     return sbus_readb(esp->regs + (reg * 4UL));
0212 }
0213 
0214 static int sbus_esp_irq_pending(struct esp *esp)
0215 {
0216     if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
0217         return 1;
0218     return 0;
0219 }
0220 
0221 static void sbus_esp_reset_dma(struct esp *esp)
0222 {
0223     int can_do_burst16, can_do_burst32, can_do_burst64;
0224     int can_do_sbus64, lim;
0225     struct platform_device *op = to_platform_device(esp->dev);
0226     u32 val;
0227 
0228     can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
0229     can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
0230     can_do_burst64 = 0;
0231     can_do_sbus64 = 0;
0232     if (sbus_can_dma_64bit())
0233         can_do_sbus64 = 1;
0234     if (sbus_can_burst64())
0235         can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
0236 
0237     /* Put the DVMA into a known state. */
0238     if (esp->dmarev != dvmahme) {
0239         val = dma_read32(DMA_CSR);
0240         dma_write32(val | DMA_RST_SCSI, DMA_CSR);
0241         dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
0242     }
0243     switch (esp->dmarev) {
0244     case dvmahme:
0245         dma_write32(DMA_RESET_FAS366, DMA_CSR);
0246         dma_write32(DMA_RST_SCSI, DMA_CSR);
0247 
0248         esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
0249                     DMA_SCSI_DISAB | DMA_INT_ENAB);
0250 
0251         esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
0252                       DMA_BRST_SZ);
0253 
0254         if (can_do_burst64)
0255             esp->prev_hme_dmacsr |= DMA_BRST64;
0256         else if (can_do_burst32)
0257             esp->prev_hme_dmacsr |= DMA_BRST32;
0258 
0259         if (can_do_sbus64) {
0260             esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
0261             sbus_set_sbus64(&op->dev, esp->bursts);
0262         }
0263 
0264         lim = 1000;
0265         while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
0266             if (--lim == 0) {
0267                 printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
0268                        "will not clear!\n",
0269                        esp->host->unique_id);
0270                 break;
0271             }
0272             udelay(1);
0273         }
0274 
0275         dma_write32(0, DMA_CSR);
0276         dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
0277 
0278         dma_write32(0, DMA_ADDR);
0279         break;
0280 
0281     case dvmarev2:
0282         if (esp->rev != ESP100) {
0283             val = dma_read32(DMA_CSR);
0284             dma_write32(val | DMA_3CLKS, DMA_CSR);
0285         }
0286         break;
0287 
0288     case dvmarev3:
0289         val = dma_read32(DMA_CSR);
0290         val &= ~DMA_3CLKS;
0291         val |= DMA_2CLKS;
0292         if (can_do_burst32) {
0293             val &= ~DMA_BRST_SZ;
0294             val |= DMA_BRST32;
0295         }
0296         dma_write32(val, DMA_CSR);
0297         break;
0298 
0299     case dvmaesc1:
0300         val = dma_read32(DMA_CSR);
0301         val |= DMA_ADD_ENABLE;
0302         val &= ~DMA_BCNT_ENAB;
0303         if (!can_do_burst32 && can_do_burst16) {
0304             val |= DMA_ESC_BURST;
0305         } else {
0306             val &= ~(DMA_ESC_BURST);
0307         }
0308         dma_write32(val, DMA_CSR);
0309         break;
0310 
0311     default:
0312         break;
0313     }
0314 
0315     /* Enable interrupts.  */
0316     val = dma_read32(DMA_CSR);
0317     dma_write32(val | DMA_INT_ENAB, DMA_CSR);
0318 }
0319 
0320 static void sbus_esp_dma_drain(struct esp *esp)
0321 {
0322     u32 csr;
0323     int lim;
0324 
0325     if (esp->dmarev == dvmahme)
0326         return;
0327 
0328     csr = dma_read32(DMA_CSR);
0329     if (!(csr & DMA_FIFO_ISDRAIN))
0330         return;
0331 
0332     if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
0333         dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);
0334 
0335     lim = 1000;
0336     while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
0337         if (--lim == 0) {
0338             printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
0339                    esp->host->unique_id);
0340             break;
0341         }
0342         udelay(1);
0343     }
0344 }
0345 
0346 static void sbus_esp_dma_invalidate(struct esp *esp)
0347 {
0348     if (esp->dmarev == dvmahme) {
0349         dma_write32(DMA_RST_SCSI, DMA_CSR);
0350 
0351         esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
0352                      (DMA_PARITY_OFF | DMA_2CLKS |
0353                       DMA_SCSI_DISAB | DMA_INT_ENAB)) &
0354                     ~(DMA_ST_WRITE | DMA_ENABLE));
0355 
0356         dma_write32(0, DMA_CSR);
0357         dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
0358 
0359         /* This is necessary to avoid having the SCSI channel
0360          * engine lock up on us.
0361          */
0362         dma_write32(0, DMA_ADDR);
0363     } else {
0364         u32 val;
0365         int lim;
0366 
0367         lim = 1000;
0368         while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
0369             if (--lim == 0) {
0370                 printk(KERN_ALERT PFX "esp%d: DMA will not "
0371                        "invalidate!\n", esp->host->unique_id);
0372                 break;
0373             }
0374             udelay(1);
0375         }
0376 
0377         val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
0378         val |= DMA_FIFO_INV;
0379         dma_write32(val, DMA_CSR);
0380         val &= ~DMA_FIFO_INV;
0381         dma_write32(val, DMA_CSR);
0382     }
0383 }
0384 
0385 static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
0386                   u32 dma_count, int write, u8 cmd)
0387 {
0388     u32 csr;
0389 
0390     BUG_ON(!(cmd & ESP_CMD_DMA));
0391 
0392     sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
0393     sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
0394     if (esp->rev == FASHME) {
0395         sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
0396         sbus_esp_write8(esp, 0, FAS_RHI);
0397 
0398         scsi_esp_cmd(esp, cmd);
0399 
0400         csr = esp->prev_hme_dmacsr;
0401         csr |= DMA_SCSI_DISAB | DMA_ENABLE;
0402         if (write)
0403             csr |= DMA_ST_WRITE;
0404         else
0405             csr &= ~DMA_ST_WRITE;
0406         esp->prev_hme_dmacsr = csr;
0407 
0408         dma_write32(dma_count, DMA_COUNT);
0409         dma_write32(addr, DMA_ADDR);
0410         dma_write32(csr, DMA_CSR);
0411     } else {
0412         csr = dma_read32(DMA_CSR);
0413         csr |= DMA_ENABLE;
0414         if (write)
0415             csr |= DMA_ST_WRITE;
0416         else
0417             csr &= ~DMA_ST_WRITE;
0418         dma_write32(csr, DMA_CSR);
0419         if (esp->dmarev == dvmaesc1) {
0420             u32 end = PAGE_ALIGN(addr + dma_count + 16U);
0421             dma_write32(end - addr, DMA_COUNT);
0422         }
0423         dma_write32(addr, DMA_ADDR);
0424 
0425         scsi_esp_cmd(esp, cmd);
0426     }
0427 
0428 }
0429 
0430 static int sbus_esp_dma_error(struct esp *esp)
0431 {
0432     u32 csr = dma_read32(DMA_CSR);
0433 
0434     if (csr & DMA_HNDL_ERROR)
0435         return 1;
0436 
0437     return 0;
0438 }
0439 
0440 static const struct esp_driver_ops sbus_esp_ops = {
0441     .esp_write8 =   sbus_esp_write8,
0442     .esp_read8  =   sbus_esp_read8,
0443     .irq_pending    =   sbus_esp_irq_pending,
0444     .reset_dma  =   sbus_esp_reset_dma,
0445     .dma_drain  =   sbus_esp_dma_drain,
0446     .dma_invalidate =   sbus_esp_dma_invalidate,
0447     .send_dma_cmd   =   sbus_esp_send_dma_cmd,
0448     .dma_error  =   sbus_esp_dma_error,
0449 };
0450 
0451 static int esp_sbus_probe_one(struct platform_device *op,
0452                   struct platform_device *espdma, int hme)
0453 {
0454     struct scsi_host_template *tpnt = &scsi_esp_template;
0455     struct Scsi_Host *host;
0456     struct esp *esp;
0457     int err;
0458 
0459     host = scsi_host_alloc(tpnt, sizeof(struct esp));
0460 
0461     err = -ENOMEM;
0462     if (!host)
0463         goto fail;
0464 
0465     host->max_id = (hme ? 16 : 8);
0466     esp = shost_priv(host);
0467 
0468     esp->host = host;
0469     esp->dev = &op->dev;
0470     esp->ops = &sbus_esp_ops;
0471 
0472     if (hme)
0473         esp->flags |= ESP_FLAG_WIDE_CAPABLE;
0474 
0475     err = esp_sbus_setup_dma(esp, espdma);
0476     if (err < 0)
0477         goto fail_unlink;
0478 
0479     err = esp_sbus_map_regs(esp, hme);
0480     if (err < 0)
0481         goto fail_unlink;
0482 
0483     err = esp_sbus_map_command_block(esp);
0484     if (err < 0)
0485         goto fail_unmap_regs;
0486 
0487     err = esp_sbus_register_irq(esp);
0488     if (err < 0)
0489         goto fail_unmap_command_block;
0490 
0491     esp_sbus_get_props(esp, espdma);
0492 
0493     /* Before we try to touch the ESP chip, ESC1 dma can
0494      * come up with the reset bit set, so make sure that
0495      * is clear first.
0496      */
0497     if (esp->dmarev == dvmaesc1) {
0498         u32 val = dma_read32(DMA_CSR);
0499 
0500         dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
0501     }
0502 
0503     dev_set_drvdata(&op->dev, esp);
0504 
0505     err = scsi_esp_register(esp);
0506     if (err)
0507         goto fail_free_irq;
0508 
0509     return 0;
0510 
0511 fail_free_irq:
0512     free_irq(host->irq, esp);
0513 fail_unmap_command_block:
0514     dma_free_coherent(&op->dev, 16,
0515               esp->command_block,
0516               esp->command_block_dma);
0517 fail_unmap_regs:
0518     of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
0519 fail_unlink:
0520     scsi_host_put(host);
0521 fail:
0522     return err;
0523 }
0524 
0525 static int esp_sbus_probe(struct platform_device *op)
0526 {
0527     struct device_node *dma_node = NULL;
0528     struct device_node *dp = op->dev.of_node;
0529     struct platform_device *dma_of = NULL;
0530     int hme = 0;
0531     int ret;
0532 
0533     if (of_node_name_eq(dp->parent, "espdma") ||
0534         of_node_name_eq(dp->parent, "dma"))
0535         dma_node = dp->parent;
0536     else if (of_node_name_eq(dp, "SUNW,fas")) {
0537         dma_node = op->dev.of_node;
0538         hme = 1;
0539     }
0540     if (dma_node)
0541         dma_of = of_find_device_by_node(dma_node);
0542     if (!dma_of)
0543         return -ENODEV;
0544 
0545     ret = esp_sbus_probe_one(op, dma_of, hme);
0546     if (ret)
0547         put_device(&dma_of->dev);
0548 
0549     return ret;
0550 }
0551 
0552 static int esp_sbus_remove(struct platform_device *op)
0553 {
0554     struct esp *esp = dev_get_drvdata(&op->dev);
0555     struct platform_device *dma_of = esp->dma;
0556     unsigned int irq = esp->host->irq;
0557     bool is_hme;
0558     u32 val;
0559 
0560     scsi_esp_unregister(esp);
0561 
0562     /* Disable interrupts.  */
0563     val = dma_read32(DMA_CSR);
0564     dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
0565 
0566     free_irq(irq, esp);
0567 
0568     is_hme = (esp->dmarev == dvmahme);
0569 
0570     dma_free_coherent(&op->dev, 16,
0571               esp->command_block,
0572               esp->command_block_dma);
0573     of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
0574            SBUS_ESP_REG_SIZE);
0575     of_iounmap(&dma_of->resource[0], esp->dma_regs,
0576            resource_size(&dma_of->resource[0]));
0577 
0578     scsi_host_put(esp->host);
0579 
0580     dev_set_drvdata(&op->dev, NULL);
0581 
0582     put_device(&dma_of->dev);
0583 
0584     return 0;
0585 }
0586 
0587 static const struct of_device_id esp_match[] = {
0588     {
0589         .name = "SUNW,esp",
0590     },
0591     {
0592         .name = "SUNW,fas",
0593     },
0594     {
0595         .name = "esp",
0596     },
0597     {},
0598 };
0599 MODULE_DEVICE_TABLE(of, esp_match);
0600 
0601 static struct platform_driver esp_sbus_driver = {
0602     .driver = {
0603         .name = "esp",
0604         .of_match_table = esp_match,
0605     },
0606     .probe      = esp_sbus_probe,
0607     .remove     = esp_sbus_remove,
0608 };
0609 module_platform_driver(esp_sbus_driver);
0610 
0611 MODULE_DESCRIPTION("Sun ESP SCSI driver");
0612 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
0613 MODULE_LICENSE("GPL");
0614 MODULE_VERSION(DRV_VERSION);
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