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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Sun3 SCSI stuff by Erik Verbruggen (erik@bigmama.xtdnet.nl)
0004  *
0005  * Sun3 DMA routines added by Sam Creasey (sammy@sammy.net)
0006  *
0007  * VME support added by Sam Creasey
0008  *
0009  * TODO: modify this driver to support multiple Sun3 SCSI VME boards
0010  *
0011  * Adapted from mac_scsinew.c:
0012  */
0013 /*
0014  * Generic Macintosh NCR5380 driver
0015  *
0016  * Copyright 1998, Michael Schmitz <mschmitz@lbl.gov>
0017  *
0018  * derived in part from:
0019  */
0020 /*
0021  * Generic Generic NCR5380 driver
0022  *
0023  * Copyright 1995, Russell King
0024  */
0025 
0026 #include <linux/types.h>
0027 #include <linux/delay.h>
0028 #include <linux/module.h>
0029 #include <linux/ioport.h>
0030 #include <linux/init.h>
0031 #include <linux/blkdev.h>
0032 #include <linux/platform_device.h>
0033 
0034 #include <asm/io.h>
0035 #include <asm/dvma.h>
0036 
0037 #include <scsi/scsi_host.h>
0038 
0039 /* minimum number of bytes to do dma on */
0040 #define DMA_MIN_SIZE                    129
0041 
0042 /* Definitions for the core NCR5380 driver. */
0043 
0044 #define NCR5380_implementation_fields   /* none */
0045 
0046 #define NCR5380_read(reg)               in_8(hostdata->io + (reg))
0047 #define NCR5380_write(reg, value)       out_8(hostdata->io + (reg), value)
0048 
0049 #define NCR5380_queue_command           sun3scsi_queue_command
0050 #define NCR5380_host_reset              sun3scsi_host_reset
0051 #define NCR5380_abort                   sun3scsi_abort
0052 #define NCR5380_info                    sun3scsi_info
0053 
0054 #define NCR5380_dma_xfer_len            sun3scsi_dma_xfer_len
0055 #define NCR5380_dma_recv_setup          sun3scsi_dma_count
0056 #define NCR5380_dma_send_setup          sun3scsi_dma_count
0057 #define NCR5380_dma_residual            sun3scsi_dma_residual
0058 
0059 #include "NCR5380.h"
0060 
0061 /* dma regs start at regbase + 8, directly after the NCR regs */
0062 struct sun3_dma_regs {
0063     unsigned short dma_addr_hi; /* vme only */
0064     unsigned short dma_addr_lo; /* vme only */
0065     unsigned short dma_count_hi; /* vme only */
0066     unsigned short dma_count_lo; /* vme only */
0067     unsigned short udc_data; /* udc dma data reg (obio only) */
0068     unsigned short udc_addr; /* uda dma addr reg (obio only) */
0069     unsigned short fifo_data; /* fifo data reg,
0070                                * holds extra byte on odd dma reads
0071                                */
0072     unsigned short fifo_count;
0073     unsigned short csr; /* control/status reg */
0074     unsigned short bpack_hi; /* vme only */
0075     unsigned short bpack_lo; /* vme only */
0076     unsigned short ivect; /* vme only */
0077     unsigned short fifo_count_hi; /* vme only */
0078 };
0079 
0080 /* ucd chip specific regs - live in dvma space */
0081 struct sun3_udc_regs {
0082     unsigned short rsel; /* select regs to load */
0083     unsigned short addr_hi; /* high word of addr */
0084     unsigned short addr_lo; /* low word */
0085     unsigned short count; /* words to be xfer'd */
0086     unsigned short mode_hi; /* high word of channel mode */
0087     unsigned short mode_lo; /* low word of channel mode */
0088 };
0089 
0090 /* addresses of the udc registers */
0091 #define UDC_MODE 0x38
0092 #define UDC_CSR 0x2e /* command/status */
0093 #define UDC_CHN_HI 0x26 /* chain high word */
0094 #define UDC_CHN_LO 0x22 /* chain lo word */
0095 #define UDC_CURA_HI 0x1a /* cur reg A high */
0096 #define UDC_CURA_LO 0x0a /* cur reg A low */
0097 #define UDC_CURB_HI 0x12 /* cur reg B high */
0098 #define UDC_CURB_LO 0x02 /* cur reg B low */
0099 #define UDC_MODE_HI 0x56 /* mode reg high */
0100 #define UDC_MODE_LO 0x52 /* mode reg low */
0101 #define UDC_COUNT 0x32 /* words to xfer */
0102 
0103 /* some udc commands */
0104 #define UDC_RESET 0
0105 #define UDC_CHN_START 0xa0 /* start chain */
0106 #define UDC_INT_ENABLE 0x32 /* channel 1 int on */
0107 
0108 /* udc mode words */
0109 #define UDC_MODE_HIWORD 0x40
0110 #define UDC_MODE_LSEND 0xc2
0111 #define UDC_MODE_LRECV 0xd2
0112 
0113 /* udc reg selections */
0114 #define UDC_RSEL_SEND 0x282
0115 #define UDC_RSEL_RECV 0x182
0116 
0117 /* bits in csr reg */
0118 #define CSR_DMA_ACTIVE 0x8000
0119 #define CSR_DMA_CONFLICT 0x4000
0120 #define CSR_DMA_BUSERR 0x2000
0121 
0122 #define CSR_FIFO_EMPTY 0x400 /* fifo flushed? */
0123 #define CSR_SDB_INT 0x200 /* sbc interrupt pending */
0124 #define CSR_DMA_INT 0x100 /* dma interrupt pending */
0125 
0126 #define CSR_LEFT 0xc0
0127 #define CSR_LEFT_3 0xc0
0128 #define CSR_LEFT_2 0x80
0129 #define CSR_LEFT_1 0x40
0130 #define CSR_PACK_ENABLE 0x20
0131 
0132 #define CSR_DMA_ENABLE 0x10
0133 
0134 #define CSR_SEND 0x8 /* 1 = send  0 = recv */
0135 #define CSR_FIFO 0x2 /* reset fifo */
0136 #define CSR_INTR 0x4 /* interrupt enable */
0137 #define CSR_SCSI 0x1
0138 
0139 #define VME_DATA24 0x3d00
0140 
0141 extern int sun3_map_test(unsigned long, char *);
0142 
0143 static int setup_can_queue = -1;
0144 module_param(setup_can_queue, int, 0);
0145 static int setup_cmd_per_lun = -1;
0146 module_param(setup_cmd_per_lun, int, 0);
0147 static int setup_sg_tablesize = -1;
0148 module_param(setup_sg_tablesize, int, 0);
0149 static int setup_hostid = -1;
0150 module_param(setup_hostid, int, 0);
0151 
0152 /* ms to wait after hitting dma regs */
0153 #define SUN3_DMA_DELAY 10
0154 
0155 /* dvma buffer to allocate -- 32k should hopefully be more than sufficient */
0156 #define SUN3_DVMA_BUFSIZE 0xe000
0157 
0158 static struct scsi_cmnd *sun3_dma_setup_done;
0159 static volatile struct sun3_dma_regs *dregs;
0160 static struct sun3_udc_regs *udc_regs;
0161 static unsigned char *sun3_dma_orig_addr;
0162 static unsigned long sun3_dma_orig_count;
0163 static int sun3_dma_active;
0164 static unsigned long last_residual;
0165 
0166 #ifndef SUN3_SCSI_VME
0167 /* dma controller register access functions */
0168 
0169 static inline unsigned short sun3_udc_read(unsigned char reg)
0170 {
0171     unsigned short ret;
0172 
0173     dregs->udc_addr = UDC_CSR;
0174     udelay(SUN3_DMA_DELAY);
0175     ret = dregs->udc_data;
0176     udelay(SUN3_DMA_DELAY);
0177     
0178     return ret;
0179 }
0180 
0181 static inline void sun3_udc_write(unsigned short val, unsigned char reg)
0182 {
0183     dregs->udc_addr = reg;
0184     udelay(SUN3_DMA_DELAY);
0185     dregs->udc_data = val;
0186     udelay(SUN3_DMA_DELAY);
0187 }
0188 #endif
0189 
0190 // safe bits for the CSR
0191 #define CSR_GOOD 0x060f
0192 
0193 static irqreturn_t scsi_sun3_intr(int irq, void *dev)
0194 {
0195     struct Scsi_Host *instance = dev;
0196     unsigned short csr = dregs->csr;
0197     int handled = 0;
0198 
0199 #ifdef SUN3_SCSI_VME
0200     dregs->csr &= ~CSR_DMA_ENABLE;
0201 #endif
0202 
0203     if(csr & ~CSR_GOOD) {
0204         if (csr & CSR_DMA_BUSERR)
0205             shost_printk(KERN_ERR, instance, "bus error in DMA\n");
0206         if (csr & CSR_DMA_CONFLICT)
0207             shost_printk(KERN_ERR, instance, "DMA conflict\n");
0208         handled = 1;
0209     }
0210 
0211     if(csr & (CSR_SDB_INT | CSR_DMA_INT)) {
0212         NCR5380_intr(irq, dev);
0213         handled = 1;
0214     }
0215 
0216     return IRQ_RETVAL(handled);
0217 }
0218 
0219 /* sun3scsi_dma_setup() -- initialize the dma controller for a read/write */
0220 static int sun3scsi_dma_setup(struct NCR5380_hostdata *hostdata,
0221                               unsigned char *data, int count, int write_flag)
0222 {
0223     void *addr;
0224 
0225     if(sun3_dma_orig_addr != NULL)
0226         dvma_unmap(sun3_dma_orig_addr);
0227 
0228 #ifdef SUN3_SCSI_VME
0229     addr = (void *)dvma_map_vme((unsigned long) data, count);
0230 #else
0231     addr = (void *)dvma_map((unsigned long) data, count);
0232 #endif
0233         
0234     sun3_dma_orig_addr = addr;
0235     sun3_dma_orig_count = count;
0236 
0237 #ifndef SUN3_SCSI_VME
0238     dregs->fifo_count = 0;
0239     sun3_udc_write(UDC_RESET, UDC_CSR);
0240     
0241     /* reset fifo */
0242     dregs->csr &= ~CSR_FIFO;
0243     dregs->csr |= CSR_FIFO;
0244 #endif
0245     
0246     /* set direction */
0247     if(write_flag)
0248         dregs->csr |= CSR_SEND;
0249     else
0250         dregs->csr &= ~CSR_SEND;
0251     
0252 #ifdef SUN3_SCSI_VME
0253     dregs->csr |= CSR_PACK_ENABLE;
0254 
0255     dregs->dma_addr_hi = ((unsigned long)addr >> 16);
0256     dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
0257 
0258     dregs->dma_count_hi = 0;
0259     dregs->dma_count_lo = 0;
0260     dregs->fifo_count_hi = 0;
0261     dregs->fifo_count = 0;
0262 #else
0263     /* byte count for fifo */
0264     dregs->fifo_count = count;
0265 
0266     sun3_udc_write(UDC_RESET, UDC_CSR);
0267     
0268     /* reset fifo */
0269     dregs->csr &= ~CSR_FIFO;
0270     dregs->csr |= CSR_FIFO;
0271     
0272     if(dregs->fifo_count != count) { 
0273         shost_printk(KERN_ERR, hostdata->host,
0274                      "FIFO mismatch %04x not %04x\n",
0275                      dregs->fifo_count, (unsigned int) count);
0276         NCR5380_dprint(NDEBUG_DMA, hostdata->host);
0277     }
0278 
0279     /* setup udc */
0280     udc_regs->addr_hi = (((unsigned long)(addr) & 0xff0000) >> 8);
0281     udc_regs->addr_lo = ((unsigned long)(addr) & 0xffff);
0282     udc_regs->count = count/2; /* count in words */
0283     udc_regs->mode_hi = UDC_MODE_HIWORD;
0284     if(write_flag) {
0285         if(count & 1)
0286             udc_regs->count++;
0287         udc_regs->mode_lo = UDC_MODE_LSEND;
0288         udc_regs->rsel = UDC_RSEL_SEND;
0289     } else {
0290         udc_regs->mode_lo = UDC_MODE_LRECV;
0291         udc_regs->rsel = UDC_RSEL_RECV;
0292     }
0293     
0294     /* announce location of regs block */
0295     sun3_udc_write(((dvma_vtob(udc_regs) & 0xff0000) >> 8),
0296                UDC_CHN_HI); 
0297 
0298     sun3_udc_write((dvma_vtob(udc_regs) & 0xffff), UDC_CHN_LO);
0299 
0300     /* set dma master on */
0301     sun3_udc_write(0xd, UDC_MODE);
0302 
0303     /* interrupt enable */
0304     sun3_udc_write(UDC_INT_ENABLE, UDC_CSR);
0305 #endif
0306     
0307         return count;
0308 
0309 }
0310 
0311 static int sun3scsi_dma_count(struct NCR5380_hostdata *hostdata,
0312                               unsigned char *data, int count)
0313 {
0314     return count;
0315 }
0316 
0317 static inline int sun3scsi_dma_recv_setup(struct NCR5380_hostdata *hostdata,
0318                                           unsigned char *data, int count)
0319 {
0320     return sun3scsi_dma_setup(hostdata, data, count, 0);
0321 }
0322 
0323 static inline int sun3scsi_dma_send_setup(struct NCR5380_hostdata *hostdata,
0324                                           unsigned char *data, int count)
0325 {
0326     return sun3scsi_dma_setup(hostdata, data, count, 1);
0327 }
0328 
0329 static int sun3scsi_dma_residual(struct NCR5380_hostdata *hostdata)
0330 {
0331     return last_residual;
0332 }
0333 
0334 static int sun3scsi_dma_xfer_len(struct NCR5380_hostdata *hostdata,
0335                                  struct scsi_cmnd *cmd)
0336 {
0337     int wanted_len = NCR5380_to_ncmd(cmd)->this_residual;
0338 
0339     if (wanted_len < DMA_MIN_SIZE || blk_rq_is_passthrough(scsi_cmd_to_rq(cmd)))
0340         return 0;
0341 
0342     return wanted_len;
0343 }
0344 
0345 static inline int sun3scsi_dma_start(unsigned long count, unsigned char *data)
0346 {
0347 #ifdef SUN3_SCSI_VME
0348     unsigned short csr;
0349 
0350     csr = dregs->csr;
0351 
0352     dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
0353     dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
0354 
0355     dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
0356     dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
0357 
0358 /*  if(!(csr & CSR_DMA_ENABLE))
0359  *      dregs->csr |= CSR_DMA_ENABLE;
0360  */
0361 #else
0362     sun3_udc_write(UDC_CHN_START, UDC_CSR);
0363 #endif
0364     
0365     return 0;
0366 }
0367 
0368 /* clean up after our dma is done */
0369 static int sun3scsi_dma_finish(enum dma_data_direction data_dir)
0370 {
0371     const bool write_flag = data_dir == DMA_TO_DEVICE;
0372     unsigned short __maybe_unused count;
0373     unsigned short fifo;
0374     int ret = 0;
0375     
0376     sun3_dma_active = 0;
0377 
0378 #ifdef SUN3_SCSI_VME
0379     dregs->csr &= ~CSR_DMA_ENABLE;
0380 
0381     fifo = dregs->fifo_count;
0382     if (write_flag) {
0383         if ((fifo > 0) && (fifo < sun3_dma_orig_count))
0384             fifo++;
0385     }
0386 
0387     last_residual = fifo;
0388     /* empty bytes from the fifo which didn't make it */
0389     if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
0390         unsigned char *vaddr;
0391 
0392         vaddr = (unsigned char *)dvma_vmetov(sun3_dma_orig_addr);
0393 
0394         vaddr += (sun3_dma_orig_count - fifo);
0395         vaddr--;
0396 
0397         switch (dregs->csr & CSR_LEFT) {
0398         case CSR_LEFT_3:
0399             *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
0400             vaddr--;
0401             fallthrough;
0402 
0403         case CSR_LEFT_2:
0404             *vaddr = (dregs->bpack_hi & 0x00ff);
0405             vaddr--;
0406             fallthrough;
0407 
0408         case CSR_LEFT_1:
0409             *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
0410             break;
0411         }
0412     }
0413 #else
0414     // check to empty the fifo on a read
0415     if(!write_flag) {
0416         int tmo = 20000; /* .2 sec */
0417         
0418         while(1) {
0419             if(dregs->csr & CSR_FIFO_EMPTY)
0420                 break;
0421 
0422             if(--tmo <= 0) {
0423                 printk("sun3scsi: fifo failed to empty!\n");
0424                 return 1;
0425             }
0426             udelay(10);
0427         }
0428     }
0429 
0430     dregs->udc_addr = 0x32;
0431     udelay(SUN3_DMA_DELAY);
0432     count = 2 * dregs->udc_data;
0433     udelay(SUN3_DMA_DELAY);
0434 
0435     fifo = dregs->fifo_count;
0436     last_residual = fifo;
0437 
0438     /* empty bytes from the fifo which didn't make it */
0439     if((!write_flag) && (count - fifo) == 2) {
0440         unsigned short data;
0441         unsigned char *vaddr;
0442 
0443         data = dregs->fifo_data;
0444         vaddr = (unsigned char *)dvma_btov(sun3_dma_orig_addr);
0445         
0446         vaddr += (sun3_dma_orig_count - fifo);
0447 
0448         vaddr[-2] = (data & 0xff00) >> 8;
0449         vaddr[-1] = (data & 0xff);
0450     }
0451 #endif
0452 
0453     dvma_unmap(sun3_dma_orig_addr);
0454     sun3_dma_orig_addr = NULL;
0455 
0456 #ifdef SUN3_SCSI_VME
0457     dregs->dma_addr_hi = 0;
0458     dregs->dma_addr_lo = 0;
0459     dregs->dma_count_hi = 0;
0460     dregs->dma_count_lo = 0;
0461 
0462     dregs->fifo_count = 0;
0463     dregs->fifo_count_hi = 0;
0464 
0465     dregs->csr &= ~CSR_SEND;
0466 /*  dregs->csr |= CSR_DMA_ENABLE; */
0467 #else
0468     sun3_udc_write(UDC_RESET, UDC_CSR);
0469     dregs->fifo_count = 0;
0470     dregs->csr &= ~CSR_SEND;
0471 
0472     /* reset fifo */
0473     dregs->csr &= ~CSR_FIFO;
0474     dregs->csr |= CSR_FIFO;
0475 #endif
0476     
0477     sun3_dma_setup_done = NULL;
0478 
0479     return ret;
0480 
0481 }
0482     
0483 #include "NCR5380.c"
0484 
0485 #ifdef SUN3_SCSI_VME
0486 #define SUN3_SCSI_NAME          "Sun3 NCR5380 VME SCSI"
0487 #define DRV_MODULE_NAME         "sun3_scsi_vme"
0488 #else
0489 #define SUN3_SCSI_NAME          "Sun3 NCR5380 SCSI"
0490 #define DRV_MODULE_NAME         "sun3_scsi"
0491 #endif
0492 
0493 #define PFX                     DRV_MODULE_NAME ": "
0494 
0495 static struct scsi_host_template sun3_scsi_template = {
0496     .module         = THIS_MODULE,
0497     .proc_name      = DRV_MODULE_NAME,
0498     .name           = SUN3_SCSI_NAME,
0499     .info           = sun3scsi_info,
0500     .queuecommand       = sun3scsi_queue_command,
0501     .eh_abort_handler   = sun3scsi_abort,
0502     .eh_host_reset_handler  = sun3scsi_host_reset,
0503     .can_queue      = 16,
0504     .this_id        = 7,
0505     .sg_tablesize       = 1,
0506     .cmd_per_lun        = 2,
0507     .dma_boundary       = PAGE_SIZE - 1,
0508     .cmd_size       = sizeof(struct NCR5380_cmd),
0509 };
0510 
0511 static int __init sun3_scsi_probe(struct platform_device *pdev)
0512 {
0513     struct Scsi_Host *instance;
0514     struct NCR5380_hostdata *hostdata;
0515     int error;
0516     struct resource *irq, *mem;
0517     void __iomem *ioaddr;
0518     int host_flags = 0;
0519 #ifdef SUN3_SCSI_VME
0520     int i;
0521 #endif
0522 
0523     if (setup_can_queue > 0)
0524         sun3_scsi_template.can_queue = setup_can_queue;
0525     if (setup_cmd_per_lun > 0)
0526         sun3_scsi_template.cmd_per_lun = setup_cmd_per_lun;
0527     if (setup_sg_tablesize > 0)
0528         sun3_scsi_template.sg_tablesize = setup_sg_tablesize;
0529     if (setup_hostid >= 0)
0530         sun3_scsi_template.this_id = setup_hostid & 7;
0531 
0532 #ifdef SUN3_SCSI_VME
0533     ioaddr = NULL;
0534     for (i = 0; i < 2; i++) {
0535         unsigned char x;
0536 
0537         irq = platform_get_resource(pdev, IORESOURCE_IRQ, i);
0538         mem = platform_get_resource(pdev, IORESOURCE_MEM, i);
0539         if (!irq || !mem)
0540             break;
0541 
0542         ioaddr = sun3_ioremap(mem->start, resource_size(mem),
0543                               SUN3_PAGE_TYPE_VME16);
0544         dregs = (struct sun3_dma_regs *)(ioaddr + 8);
0545 
0546         if (sun3_map_test((unsigned long)dregs, &x)) {
0547             unsigned short oldcsr;
0548 
0549             oldcsr = dregs->csr;
0550             dregs->csr = 0;
0551             udelay(SUN3_DMA_DELAY);
0552             if (dregs->csr == 0x1400)
0553                 break;
0554 
0555             dregs->csr = oldcsr;
0556         }
0557 
0558         iounmap(ioaddr);
0559         ioaddr = NULL;
0560     }
0561     if (!ioaddr)
0562         return -ENODEV;
0563 #else
0564     irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
0565     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0566     if (!irq || !mem)
0567         return -ENODEV;
0568 
0569     ioaddr = ioremap(mem->start, resource_size(mem));
0570     dregs = (struct sun3_dma_regs *)(ioaddr + 8);
0571 
0572     udc_regs = dvma_malloc(sizeof(struct sun3_udc_regs));
0573     if (!udc_regs) {
0574         pr_err(PFX "couldn't allocate DVMA memory!\n");
0575         iounmap(ioaddr);
0576         return -ENOMEM;
0577     }
0578 #endif
0579 
0580     instance = scsi_host_alloc(&sun3_scsi_template,
0581                                sizeof(struct NCR5380_hostdata));
0582     if (!instance) {
0583         error = -ENOMEM;
0584         goto fail_alloc;
0585     }
0586 
0587     instance->irq = irq->start;
0588 
0589     hostdata = shost_priv(instance);
0590     hostdata->base = mem->start;
0591     hostdata->io = ioaddr;
0592 
0593     error = NCR5380_init(instance, host_flags);
0594     if (error)
0595         goto fail_init;
0596 
0597     error = request_irq(instance->irq, scsi_sun3_intr, 0,
0598                         "NCR5380", instance);
0599     if (error) {
0600         pr_err(PFX "scsi%d: IRQ %d not free, bailing out\n",
0601                instance->host_no, instance->irq);
0602         goto fail_irq;
0603     }
0604 
0605     dregs->csr = 0;
0606     udelay(SUN3_DMA_DELAY);
0607     dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
0608     udelay(SUN3_DMA_DELAY);
0609     dregs->fifo_count = 0;
0610 #ifdef SUN3_SCSI_VME
0611     dregs->fifo_count_hi = 0;
0612     dregs->dma_addr_hi = 0;
0613     dregs->dma_addr_lo = 0;
0614     dregs->dma_count_hi = 0;
0615     dregs->dma_count_lo = 0;
0616 
0617     dregs->ivect = VME_DATA24 | (instance->irq & 0xff);
0618 #endif
0619 
0620     NCR5380_maybe_reset_bus(instance);
0621 
0622     error = scsi_add_host(instance, NULL);
0623     if (error)
0624         goto fail_host;
0625 
0626     platform_set_drvdata(pdev, instance);
0627 
0628     scsi_scan_host(instance);
0629     return 0;
0630 
0631 fail_host:
0632     free_irq(instance->irq, instance);
0633 fail_irq:
0634     NCR5380_exit(instance);
0635 fail_init:
0636     scsi_host_put(instance);
0637 fail_alloc:
0638     if (udc_regs)
0639         dvma_free(udc_regs);
0640     iounmap(ioaddr);
0641     return error;
0642 }
0643 
0644 static int __exit sun3_scsi_remove(struct platform_device *pdev)
0645 {
0646     struct Scsi_Host *instance = platform_get_drvdata(pdev);
0647     struct NCR5380_hostdata *hostdata = shost_priv(instance);
0648     void __iomem *ioaddr = hostdata->io;
0649 
0650     scsi_remove_host(instance);
0651     free_irq(instance->irq, instance);
0652     NCR5380_exit(instance);
0653     scsi_host_put(instance);
0654     if (udc_regs)
0655         dvma_free(udc_regs);
0656     iounmap(ioaddr);
0657     return 0;
0658 }
0659 
0660 static struct platform_driver sun3_scsi_driver = {
0661     .remove = __exit_p(sun3_scsi_remove),
0662     .driver = {
0663         .name   = DRV_MODULE_NAME,
0664     },
0665 };
0666 
0667 module_platform_driver_probe(sun3_scsi_driver, sun3_scsi_probe);
0668 
0669 MODULE_ALIAS("platform:" DRV_MODULE_NAME);
0670 MODULE_LICENSE("GPL");
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