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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * SuperTrak EX Series Storage Controller driver for Linux
0004  *
0005  *  Copyright (C) 2005-2015 Promise Technology Inc.
0006  *
0007  *  Written By:
0008  *      Ed Lin <promise_linux@promise.com>
0009  */
0010 
0011 #include <linux/init.h>
0012 #include <linux/errno.h>
0013 #include <linux/kernel.h>
0014 #include <linux/delay.h>
0015 #include <linux/slab.h>
0016 #include <linux/time.h>
0017 #include <linux/pci.h>
0018 #include <linux/blkdev.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/types.h>
0021 #include <linux/module.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/ktime.h>
0024 #include <linux/reboot.h>
0025 #include <asm/io.h>
0026 #include <asm/irq.h>
0027 #include <asm/byteorder.h>
0028 #include <scsi/scsi.h>
0029 #include <scsi/scsi_device.h>
0030 #include <scsi/scsi_cmnd.h>
0031 #include <scsi/scsi_host.h>
0032 #include <scsi/scsi_tcq.h>
0033 #include <scsi/scsi_dbg.h>
0034 #include <scsi/scsi_eh.h>
0035 
0036 #define DRV_NAME "stex"
0037 #define ST_DRIVER_VERSION   "6.02.0000.01"
0038 #define ST_VER_MAJOR        6
0039 #define ST_VER_MINOR        02
0040 #define ST_OEM              0000
0041 #define ST_BUILD_VER        01
0042 
0043 enum {
0044     /* MU register offset */
0045     IMR0    = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
0046     IMR1    = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
0047     OMR0    = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
0048     OMR1    = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
0049     IDBL    = 0x20, /* MU_INBOUND_DOORBELL */
0050     IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
0051     IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
0052     ODBL    = 0x2c, /* MU_OUTBOUND_DOORBELL */
0053     OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
0054     OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
0055 
0056     YIOA_STATUS             = 0x00,
0057     YH2I_INT                = 0x20,
0058     YINT_EN                 = 0x34,
0059     YI2H_INT                = 0x9c,
0060     YI2H_INT_C              = 0xa0,
0061     YH2I_REQ                = 0xc0,
0062     YH2I_REQ_HI             = 0xc4,
0063     PSCRATCH0               = 0xb0,
0064     PSCRATCH1               = 0xb4,
0065     PSCRATCH2               = 0xb8,
0066     PSCRATCH3               = 0xbc,
0067     PSCRATCH4               = 0xc8,
0068     MAILBOX_BASE            = 0x1000,
0069     MAILBOX_HNDSHK_STS      = 0x0,
0070 
0071     /* MU register value */
0072     MU_INBOUND_DOORBELL_HANDSHAKE       = (1 << 0),
0073     MU_INBOUND_DOORBELL_REQHEADCHANGED  = (1 << 1),
0074     MU_INBOUND_DOORBELL_STATUSTAILCHANGED   = (1 << 2),
0075     MU_INBOUND_DOORBELL_HMUSTOPPED      = (1 << 3),
0076     MU_INBOUND_DOORBELL_RESET       = (1 << 4),
0077 
0078     MU_OUTBOUND_DOORBELL_HANDSHAKE      = (1 << 0),
0079     MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = (1 << 1),
0080     MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED  = (1 << 2),
0081     MU_OUTBOUND_DOORBELL_BUSCHANGE      = (1 << 3),
0082     MU_OUTBOUND_DOORBELL_HASEVENT       = (1 << 4),
0083     MU_OUTBOUND_DOORBELL_REQUEST_RESET  = (1 << 27),
0084 
0085     /* MU status code */
0086     MU_STATE_STARTING           = 1,
0087     MU_STATE_STARTED            = 2,
0088     MU_STATE_RESETTING          = 3,
0089     MU_STATE_FAILED             = 4,
0090     MU_STATE_STOP               = 5,
0091     MU_STATE_NOCONNECT          = 6,
0092 
0093     MU_MAX_DELAY                = 50,
0094     MU_HANDSHAKE_SIGNATURE          = 0x55aaaa55,
0095     MU_HANDSHAKE_SIGNATURE_HALF     = 0x5a5a0000,
0096     MU_HARD_RESET_WAIT          = 30000,
0097     HMU_PARTNER_TYPE            = 2,
0098 
0099     /* firmware returned values */
0100     SRB_STATUS_SUCCESS          = 0x01,
0101     SRB_STATUS_ERROR            = 0x04,
0102     SRB_STATUS_BUSY             = 0x05,
0103     SRB_STATUS_INVALID_REQUEST      = 0x06,
0104     SRB_STATUS_SELECTION_TIMEOUT        = 0x0A,
0105     SRB_SEE_SENSE               = 0x80,
0106 
0107     /* task attribute */
0108     TASK_ATTRIBUTE_SIMPLE           = 0x0,
0109     TASK_ATTRIBUTE_HEADOFQUEUE      = 0x1,
0110     TASK_ATTRIBUTE_ORDERED          = 0x2,
0111     TASK_ATTRIBUTE_ACA          = 0x4,
0112 
0113     SS_STS_NORMAL               = 0x80000000,
0114     SS_STS_DONE             = 0x40000000,
0115     SS_STS_HANDSHAKE            = 0x20000000,
0116 
0117     SS_HEAD_HANDSHAKE           = 0x80,
0118 
0119     SS_H2I_INT_RESET            = 0x100,
0120 
0121     SS_I2H_REQUEST_RESET            = 0x2000,
0122 
0123     SS_MU_OPERATIONAL           = 0x80000000,
0124 
0125     STEX_CDB_LENGTH             = 16,
0126     STATUS_VAR_LEN              = 128,
0127 
0128     /* sg flags */
0129     SG_CF_EOT               = 0x80, /* end of table */
0130     SG_CF_64B               = 0x40, /* 64 bit item */
0131     SG_CF_HOST              = 0x20, /* sg in host memory */
0132     MSG_DATA_DIR_ND             = 0,
0133     MSG_DATA_DIR_IN             = 1,
0134     MSG_DATA_DIR_OUT            = 2,
0135 
0136     st_shasta               = 0,
0137     st_vsc                  = 1,
0138     st_yosemite             = 2,
0139     st_seq                  = 3,
0140     st_yel                  = 4,
0141     st_P3                   = 5,
0142 
0143     PASSTHRU_REQ_TYPE           = 0x00000001,
0144     PASSTHRU_REQ_NO_WAKEUP          = 0x00000100,
0145     ST_INTERNAL_TIMEOUT         = 180,
0146 
0147     ST_TO_CMD               = 0,
0148     ST_FROM_CMD             = 1,
0149 
0150     /* vendor specific commands of Promise */
0151     MGT_CMD                 = 0xd8,
0152     SINBAND_MGT_CMD             = 0xd9,
0153     ARRAY_CMD               = 0xe0,
0154     CONTROLLER_CMD              = 0xe1,
0155     DEBUGGING_CMD               = 0xe2,
0156     PASSTHRU_CMD                = 0xe3,
0157 
0158     PASSTHRU_GET_ADAPTER            = 0x05,
0159     PASSTHRU_GET_DRVVER         = 0x10,
0160 
0161     CTLR_CONFIG_CMD             = 0x03,
0162     CTLR_SHUTDOWN               = 0x0d,
0163 
0164     CTLR_POWER_STATE_CHANGE         = 0x0e,
0165     CTLR_POWER_SAVING           = 0x01,
0166 
0167     PASSTHRU_SIGNATURE          = 0x4e415041,
0168     MGT_CMD_SIGNATURE           = 0xba,
0169 
0170     INQUIRY_EVPD                = 0x01,
0171 
0172     ST_ADDITIONAL_MEM           = 0x200000,
0173     ST_ADDITIONAL_MEM_MIN           = 0x80000,
0174     PMIC_SHUTDOWN               = 0x0D,
0175     PMIC_REUMSE                 = 0x10,
0176     ST_IGNORED                  = -1,
0177     ST_NOTHANDLED               = 7,
0178     ST_S3                       = 3,
0179     ST_S4                       = 4,
0180     ST_S5                       = 5,
0181     ST_S6                       = 6,
0182 };
0183 
0184 struct st_sgitem {
0185     u8 ctrl;    /* SG_CF_xxx */
0186     u8 reserved[3];
0187     __le32 count;
0188     __le64 addr;
0189 };
0190 
0191 struct st_ss_sgitem {
0192     __le32 addr;
0193     __le32 addr_hi;
0194     __le32 count;
0195 };
0196 
0197 struct st_sgtable {
0198     __le16 sg_count;
0199     __le16 max_sg_count;
0200     __le32 sz_in_byte;
0201 };
0202 
0203 struct st_msg_header {
0204     __le64 handle;
0205     u8 flag;
0206     u8 channel;
0207     __le16 timeout;
0208     u32 reserved;
0209 };
0210 
0211 struct handshake_frame {
0212     __le64 rb_phy;      /* request payload queue physical address */
0213     __le16 req_sz;      /* size of each request payload */
0214     __le16 req_cnt;     /* count of reqs the buffer can hold */
0215     __le16 status_sz;   /* size of each status payload */
0216     __le16 status_cnt;  /* count of status the buffer can hold */
0217     __le64 hosttime;    /* seconds from Jan 1, 1970 (GMT) */
0218     u8 partner_type;    /* who sends this frame */
0219     u8 reserved0[7];
0220     __le32 partner_ver_major;
0221     __le32 partner_ver_minor;
0222     __le32 partner_ver_oem;
0223     __le32 partner_ver_build;
0224     __le32 extra_offset;    /* NEW */
0225     __le32 extra_size;  /* NEW */
0226     __le32 scratch_size;
0227     u32 reserved1;
0228 };
0229 
0230 struct req_msg {
0231     __le16 tag;
0232     u8 lun;
0233     u8 target;
0234     u8 task_attr;
0235     u8 task_manage;
0236     u8 data_dir;
0237     u8 payload_sz;      /* payload size in 4-byte, not used */
0238     u8 cdb[STEX_CDB_LENGTH];
0239     u32 variable[];
0240 };
0241 
0242 struct status_msg {
0243     __le16 tag;
0244     u8 lun;
0245     u8 target;
0246     u8 srb_status;
0247     u8 scsi_status;
0248     u8 reserved;
0249     u8 payload_sz;      /* payload size in 4-byte */
0250     u8 variable[STATUS_VAR_LEN];
0251 };
0252 
0253 struct ver_info {
0254     u32 major;
0255     u32 minor;
0256     u32 oem;
0257     u32 build;
0258     u32 reserved[2];
0259 };
0260 
0261 struct st_frame {
0262     u32 base[6];
0263     u32 rom_addr;
0264 
0265     struct ver_info drv_ver;
0266     struct ver_info bios_ver;
0267 
0268     u32 bus;
0269     u32 slot;
0270     u32 irq_level;
0271     u32 irq_vec;
0272     u32 id;
0273     u32 subid;
0274 
0275     u32 dimm_size;
0276     u8 dimm_type;
0277     u8 reserved[3];
0278 
0279     u32 channel;
0280     u32 reserved1;
0281 };
0282 
0283 struct st_drvver {
0284     u32 major;
0285     u32 minor;
0286     u32 oem;
0287     u32 build;
0288     u32 signature[2];
0289     u8 console_id;
0290     u8 host_no;
0291     u8 reserved0[2];
0292     u32 reserved[3];
0293 };
0294 
0295 struct st_ccb {
0296     struct req_msg *req;
0297     struct scsi_cmnd *cmd;
0298 
0299     void *sense_buffer;
0300     unsigned int sense_bufflen;
0301     int sg_count;
0302 
0303     u32 req_type;
0304     u8 srb_status;
0305     u8 scsi_status;
0306     u8 reserved[2];
0307 };
0308 
0309 struct st_hba {
0310     void __iomem *mmio_base;    /* iomapped PCI memory space */
0311     void *dma_mem;
0312     dma_addr_t dma_handle;
0313     size_t dma_size;
0314 
0315     struct Scsi_Host *host;
0316     struct pci_dev *pdev;
0317 
0318     struct req_msg * (*alloc_rq) (struct st_hba *);
0319     int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
0320     void (*send) (struct st_hba *, struct req_msg *, u16);
0321 
0322     u32 req_head;
0323     u32 req_tail;
0324     u32 status_head;
0325     u32 status_tail;
0326 
0327     struct status_msg *status_buffer;
0328     void *copy_buffer; /* temp buffer for driver-handled commands */
0329     struct st_ccb *ccb;
0330     struct st_ccb *wait_ccb;
0331     __le32 *scratch;
0332 
0333     char work_q_name[20];
0334     struct workqueue_struct *work_q;
0335     struct work_struct reset_work;
0336     wait_queue_head_t reset_waitq;
0337     unsigned int mu_status;
0338     unsigned int cardtype;
0339     int msi_enabled;
0340     int out_req_cnt;
0341     u32 extra_offset;
0342     u16 rq_count;
0343     u16 rq_size;
0344     u16 sts_count;
0345     u8  supports_pm;
0346     int msi_lock;
0347 };
0348 
0349 struct st_card_info {
0350     struct req_msg * (*alloc_rq) (struct st_hba *);
0351     int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
0352     void (*send) (struct st_hba *, struct req_msg *, u16);
0353     unsigned int max_id;
0354     unsigned int max_lun;
0355     unsigned int max_channel;
0356     u16 rq_count;
0357     u16 rq_size;
0358     u16 sts_count;
0359 };
0360 
0361 static int S6flag;
0362 static int stex_halt(struct notifier_block *nb, ulong event, void *buf);
0363 static struct notifier_block stex_notifier = {
0364     stex_halt, NULL, 0
0365 };
0366 
0367 static int msi;
0368 module_param(msi, int, 0);
0369 MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
0370 
0371 static const char console_inq_page[] =
0372 {
0373     0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
0374     0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20,    /* "Promise " */
0375     0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E,    /* "RAID Con" */
0376     0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20,    /* "sole    " */
0377     0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20,    /* "1.00    " */
0378     0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D,    /* "SX/RSAF-" */
0379     0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20,    /* "TE1.00  " */
0380     0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
0381 };
0382 
0383 MODULE_AUTHOR("Ed Lin");
0384 MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
0385 MODULE_LICENSE("GPL");
0386 MODULE_VERSION(ST_DRIVER_VERSION);
0387 
0388 static struct status_msg *stex_get_status(struct st_hba *hba)
0389 {
0390     struct status_msg *status = hba->status_buffer + hba->status_tail;
0391 
0392     ++hba->status_tail;
0393     hba->status_tail %= hba->sts_count+1;
0394 
0395     return status;
0396 }
0397 
0398 static void stex_invalid_field(struct scsi_cmnd *cmd,
0399                    void (*done)(struct scsi_cmnd *))
0400 {
0401     /* "Invalid field in cdb" */
0402     scsi_build_sense(cmd, 0, ILLEGAL_REQUEST, 0x24, 0x0);
0403     done(cmd);
0404 }
0405 
0406 static struct req_msg *stex_alloc_req(struct st_hba *hba)
0407 {
0408     struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
0409 
0410     ++hba->req_head;
0411     hba->req_head %= hba->rq_count+1;
0412 
0413     return req;
0414 }
0415 
0416 static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
0417 {
0418     return (struct req_msg *)(hba->dma_mem +
0419         hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
0420 }
0421 
0422 static int stex_map_sg(struct st_hba *hba,
0423     struct req_msg *req, struct st_ccb *ccb)
0424 {
0425     struct scsi_cmnd *cmd;
0426     struct scatterlist *sg;
0427     struct st_sgtable *dst;
0428     struct st_sgitem *table;
0429     int i, nseg;
0430 
0431     cmd = ccb->cmd;
0432     nseg = scsi_dma_map(cmd);
0433     BUG_ON(nseg < 0);
0434     if (nseg) {
0435         dst = (struct st_sgtable *)req->variable;
0436 
0437         ccb->sg_count = nseg;
0438         dst->sg_count = cpu_to_le16((u16)nseg);
0439         dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
0440         dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
0441 
0442         table = (struct st_sgitem *)(dst + 1);
0443         scsi_for_each_sg(cmd, sg, nseg, i) {
0444             table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
0445             table[i].addr = cpu_to_le64(sg_dma_address(sg));
0446             table[i].ctrl = SG_CF_64B | SG_CF_HOST;
0447         }
0448         table[--i].ctrl |= SG_CF_EOT;
0449     }
0450 
0451     return nseg;
0452 }
0453 
0454 static int stex_ss_map_sg(struct st_hba *hba,
0455     struct req_msg *req, struct st_ccb *ccb)
0456 {
0457     struct scsi_cmnd *cmd;
0458     struct scatterlist *sg;
0459     struct st_sgtable *dst;
0460     struct st_ss_sgitem *table;
0461     int i, nseg;
0462 
0463     cmd = ccb->cmd;
0464     nseg = scsi_dma_map(cmd);
0465     BUG_ON(nseg < 0);
0466     if (nseg) {
0467         dst = (struct st_sgtable *)req->variable;
0468 
0469         ccb->sg_count = nseg;
0470         dst->sg_count = cpu_to_le16((u16)nseg);
0471         dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
0472         dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
0473 
0474         table = (struct st_ss_sgitem *)(dst + 1);
0475         scsi_for_each_sg(cmd, sg, nseg, i) {
0476             table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
0477             table[i].addr =
0478                 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
0479             table[i].addr_hi =
0480                 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
0481         }
0482     }
0483 
0484     return nseg;
0485 }
0486 
0487 static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
0488 {
0489     struct st_frame *p;
0490     size_t count = sizeof(struct st_frame);
0491 
0492     p = hba->copy_buffer;
0493     scsi_sg_copy_to_buffer(ccb->cmd, p, count);
0494     memset(p->base, 0, sizeof(u32)*6);
0495     *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
0496     p->rom_addr = 0;
0497 
0498     p->drv_ver.major = ST_VER_MAJOR;
0499     p->drv_ver.minor = ST_VER_MINOR;
0500     p->drv_ver.oem = ST_OEM;
0501     p->drv_ver.build = ST_BUILD_VER;
0502 
0503     p->bus = hba->pdev->bus->number;
0504     p->slot = hba->pdev->devfn;
0505     p->irq_level = 0;
0506     p->irq_vec = hba->pdev->irq;
0507     p->id = hba->pdev->vendor << 16 | hba->pdev->device;
0508     p->subid =
0509         hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
0510 
0511     scsi_sg_copy_from_buffer(ccb->cmd, p, count);
0512 }
0513 
0514 static void
0515 stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
0516 {
0517     req->tag = cpu_to_le16(tag);
0518 
0519     hba->ccb[tag].req = req;
0520     hba->out_req_cnt++;
0521 
0522     writel(hba->req_head, hba->mmio_base + IMR0);
0523     writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
0524     readl(hba->mmio_base + IDBL); /* flush */
0525 }
0526 
0527 static void
0528 stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
0529 {
0530     struct scsi_cmnd *cmd;
0531     struct st_msg_header *msg_h;
0532     dma_addr_t addr;
0533 
0534     req->tag = cpu_to_le16(tag);
0535 
0536     hba->ccb[tag].req = req;
0537     hba->out_req_cnt++;
0538 
0539     cmd = hba->ccb[tag].cmd;
0540     msg_h = (struct st_msg_header *)req - 1;
0541     if (likely(cmd)) {
0542         msg_h->channel = (u8)cmd->device->channel;
0543         msg_h->timeout = cpu_to_le16(scsi_cmd_to_rq(cmd)->timeout / HZ);
0544     }
0545     addr = hba->dma_handle + hba->req_head * hba->rq_size;
0546     addr += (hba->ccb[tag].sg_count+4)/11;
0547     msg_h->handle = cpu_to_le64(addr);
0548 
0549     ++hba->req_head;
0550     hba->req_head %= hba->rq_count+1;
0551     if (hba->cardtype == st_P3) {
0552         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
0553         writel(addr, hba->mmio_base + YH2I_REQ);
0554     } else {
0555         writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
0556         readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
0557         writel(addr, hba->mmio_base + YH2I_REQ);
0558         readl(hba->mmio_base + YH2I_REQ); /* flush */
0559     }
0560 }
0561 
0562 static void return_abnormal_state(struct st_hba *hba, int status)
0563 {
0564     struct st_ccb *ccb;
0565     unsigned long flags;
0566     u16 tag;
0567 
0568     spin_lock_irqsave(hba->host->host_lock, flags);
0569     for (tag = 0; tag < hba->host->can_queue; tag++) {
0570         ccb = &hba->ccb[tag];
0571         if (ccb->req == NULL)
0572             continue;
0573         ccb->req = NULL;
0574         if (ccb->cmd) {
0575             scsi_dma_unmap(ccb->cmd);
0576             ccb->cmd->result = status << 16;
0577             scsi_done(ccb->cmd);
0578             ccb->cmd = NULL;
0579         }
0580     }
0581     spin_unlock_irqrestore(hba->host->host_lock, flags);
0582 }
0583 static int
0584 stex_slave_config(struct scsi_device *sdev)
0585 {
0586     sdev->use_10_for_rw = 1;
0587     sdev->use_10_for_ms = 1;
0588     blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
0589 
0590     return 0;
0591 }
0592 
0593 static int stex_queuecommand_lck(struct scsi_cmnd *cmd)
0594 {
0595     void (*done)(struct scsi_cmnd *) = scsi_done;
0596     struct st_hba *hba;
0597     struct Scsi_Host *host;
0598     unsigned int id, lun;
0599     struct req_msg *req;
0600     u16 tag;
0601 
0602     host = cmd->device->host;
0603     id = cmd->device->id;
0604     lun = cmd->device->lun;
0605     hba = (struct st_hba *) &host->hostdata[0];
0606     if (hba->mu_status == MU_STATE_NOCONNECT) {
0607         cmd->result = DID_NO_CONNECT;
0608         done(cmd);
0609         return 0;
0610     }
0611     if (unlikely(hba->mu_status != MU_STATE_STARTED))
0612         return SCSI_MLQUEUE_HOST_BUSY;
0613 
0614     switch (cmd->cmnd[0]) {
0615     case MODE_SENSE_10:
0616     {
0617         static char ms10_caching_page[12] =
0618             { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
0619         unsigned char page;
0620 
0621         page = cmd->cmnd[2] & 0x3f;
0622         if (page == 0x8 || page == 0x3f) {
0623             scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
0624                          sizeof(ms10_caching_page));
0625             cmd->result = DID_OK << 16;
0626             done(cmd);
0627         } else
0628             stex_invalid_field(cmd, done);
0629         return 0;
0630     }
0631     case REPORT_LUNS:
0632         /*
0633          * The shasta firmware does not report actual luns in the
0634          * target, so fail the command to force sequential lun scan.
0635          * Also, the console device does not support this command.
0636          */
0637         if (hba->cardtype == st_shasta || id == host->max_id - 1) {
0638             stex_invalid_field(cmd, done);
0639             return 0;
0640         }
0641         break;
0642     case TEST_UNIT_READY:
0643         if (id == host->max_id - 1) {
0644             cmd->result = DID_OK << 16;
0645             done(cmd);
0646             return 0;
0647         }
0648         break;
0649     case INQUIRY:
0650         if (lun >= host->max_lun) {
0651             cmd->result = DID_NO_CONNECT << 16;
0652             done(cmd);
0653             return 0;
0654         }
0655         if (id != host->max_id - 1)
0656             break;
0657         if (!lun && !cmd->device->channel &&
0658             (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
0659             scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
0660                          sizeof(console_inq_page));
0661             cmd->result = DID_OK << 16;
0662             done(cmd);
0663         } else
0664             stex_invalid_field(cmd, done);
0665         return 0;
0666     case PASSTHRU_CMD:
0667         if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
0668             struct st_drvver ver;
0669             size_t cp_len = sizeof(ver);
0670 
0671             ver.major = ST_VER_MAJOR;
0672             ver.minor = ST_VER_MINOR;
0673             ver.oem = ST_OEM;
0674             ver.build = ST_BUILD_VER;
0675             ver.signature[0] = PASSTHRU_SIGNATURE;
0676             ver.console_id = host->max_id - 1;
0677             ver.host_no = hba->host->host_no;
0678             cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
0679             if (sizeof(ver) == cp_len)
0680                 cmd->result = DID_OK << 16;
0681             else
0682                 cmd->result = DID_ERROR << 16;
0683             done(cmd);
0684             return 0;
0685         }
0686         break;
0687     default:
0688         break;
0689     }
0690 
0691     tag = scsi_cmd_to_rq(cmd)->tag;
0692 
0693     if (unlikely(tag >= host->can_queue))
0694         return SCSI_MLQUEUE_HOST_BUSY;
0695 
0696     req = hba->alloc_rq(hba);
0697 
0698     req->lun = lun;
0699     req->target = id;
0700 
0701     /* cdb */
0702     memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
0703 
0704     if (cmd->sc_data_direction == DMA_FROM_DEVICE)
0705         req->data_dir = MSG_DATA_DIR_IN;
0706     else if (cmd->sc_data_direction == DMA_TO_DEVICE)
0707         req->data_dir = MSG_DATA_DIR_OUT;
0708     else
0709         req->data_dir = MSG_DATA_DIR_ND;
0710 
0711     hba->ccb[tag].cmd = cmd;
0712     hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
0713     hba->ccb[tag].sense_buffer = cmd->sense_buffer;
0714 
0715     if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
0716         hba->ccb[tag].sg_count = 0;
0717         memset(&req->variable[0], 0, 8);
0718     }
0719 
0720     hba->send(hba, req, tag);
0721     return 0;
0722 }
0723 
0724 static DEF_SCSI_QCMD(stex_queuecommand)
0725 
0726 static void stex_scsi_done(struct st_ccb *ccb)
0727 {
0728     struct scsi_cmnd *cmd = ccb->cmd;
0729     int result;
0730 
0731     if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
0732         result = ccb->scsi_status;
0733         switch (ccb->scsi_status) {
0734         case SAM_STAT_GOOD:
0735             result |= DID_OK << 16;
0736             break;
0737         case SAM_STAT_CHECK_CONDITION:
0738             result |= DID_OK << 16;
0739             break;
0740         case SAM_STAT_BUSY:
0741             result |= DID_BUS_BUSY << 16;
0742             break;
0743         default:
0744             result |= DID_ERROR << 16;
0745             break;
0746         }
0747     }
0748     else if (ccb->srb_status & SRB_SEE_SENSE)
0749         result = SAM_STAT_CHECK_CONDITION;
0750     else switch (ccb->srb_status) {
0751         case SRB_STATUS_SELECTION_TIMEOUT:
0752             result = DID_NO_CONNECT << 16;
0753             break;
0754         case SRB_STATUS_BUSY:
0755             result = DID_BUS_BUSY << 16;
0756             break;
0757         case SRB_STATUS_INVALID_REQUEST:
0758         case SRB_STATUS_ERROR:
0759         default:
0760             result = DID_ERROR << 16;
0761             break;
0762     }
0763 
0764     cmd->result = result;
0765     scsi_done(cmd);
0766 }
0767 
0768 static void stex_copy_data(struct st_ccb *ccb,
0769     struct status_msg *resp, unsigned int variable)
0770 {
0771     if (resp->scsi_status != SAM_STAT_GOOD) {
0772         if (ccb->sense_buffer != NULL)
0773             memcpy(ccb->sense_buffer, resp->variable,
0774                 min(variable, ccb->sense_bufflen));
0775         return;
0776     }
0777 
0778     if (ccb->cmd == NULL)
0779         return;
0780     scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
0781 }
0782 
0783 static void stex_check_cmd(struct st_hba *hba,
0784     struct st_ccb *ccb, struct status_msg *resp)
0785 {
0786     if (ccb->cmd->cmnd[0] == MGT_CMD &&
0787         resp->scsi_status != SAM_STAT_CHECK_CONDITION)
0788         scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
0789             le32_to_cpu(*(__le32 *)&resp->variable[0]));
0790 }
0791 
0792 static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
0793 {
0794     void __iomem *base = hba->mmio_base;
0795     struct status_msg *resp;
0796     struct st_ccb *ccb;
0797     unsigned int size;
0798     u16 tag;
0799 
0800     if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
0801         return;
0802 
0803     /* status payloads */
0804     hba->status_head = readl(base + OMR1);
0805     if (unlikely(hba->status_head > hba->sts_count)) {
0806         printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
0807             pci_name(hba->pdev));
0808         return;
0809     }
0810 
0811     /*
0812      * it's not a valid status payload if:
0813      * 1. there are no pending requests(e.g. during init stage)
0814      * 2. there are some pending requests, but the controller is in
0815      *     reset status, and its type is not st_yosemite
0816      * firmware of st_yosemite in reset status will return pending requests
0817      * to driver, so we allow it to pass
0818      */
0819     if (unlikely(hba->out_req_cnt <= 0 ||
0820             (hba->mu_status == MU_STATE_RESETTING &&
0821              hba->cardtype != st_yosemite))) {
0822         hba->status_tail = hba->status_head;
0823         goto update_status;
0824     }
0825 
0826     while (hba->status_tail != hba->status_head) {
0827         resp = stex_get_status(hba);
0828         tag = le16_to_cpu(resp->tag);
0829         if (unlikely(tag >= hba->host->can_queue)) {
0830             printk(KERN_WARNING DRV_NAME
0831                 "(%s): invalid tag\n", pci_name(hba->pdev));
0832             continue;
0833         }
0834 
0835         hba->out_req_cnt--;
0836         ccb = &hba->ccb[tag];
0837         if (unlikely(hba->wait_ccb == ccb))
0838             hba->wait_ccb = NULL;
0839         if (unlikely(ccb->req == NULL)) {
0840             printk(KERN_WARNING DRV_NAME
0841                 "(%s): lagging req\n", pci_name(hba->pdev));
0842             continue;
0843         }
0844 
0845         size = resp->payload_sz * sizeof(u32); /* payload size */
0846         if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
0847             size > sizeof(*resp))) {
0848             printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
0849                 pci_name(hba->pdev));
0850         } else {
0851             size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
0852             if (size)
0853                 stex_copy_data(ccb, resp, size);
0854         }
0855 
0856         ccb->req = NULL;
0857         ccb->srb_status = resp->srb_status;
0858         ccb->scsi_status = resp->scsi_status;
0859 
0860         if (likely(ccb->cmd != NULL)) {
0861             if (hba->cardtype == st_yosemite)
0862                 stex_check_cmd(hba, ccb, resp);
0863 
0864             if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
0865                 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
0866                 stex_controller_info(hba, ccb);
0867 
0868             scsi_dma_unmap(ccb->cmd);
0869             stex_scsi_done(ccb);
0870         } else
0871             ccb->req_type = 0;
0872     }
0873 
0874 update_status:
0875     writel(hba->status_head, base + IMR1);
0876     readl(base + IMR1); /* flush */
0877 }
0878 
0879 static irqreturn_t stex_intr(int irq, void *__hba)
0880 {
0881     struct st_hba *hba = __hba;
0882     void __iomem *base = hba->mmio_base;
0883     u32 data;
0884     unsigned long flags;
0885 
0886     spin_lock_irqsave(hba->host->host_lock, flags);
0887 
0888     data = readl(base + ODBL);
0889 
0890     if (data && data != 0xffffffff) {
0891         /* clear the interrupt */
0892         writel(data, base + ODBL);
0893         readl(base + ODBL); /* flush */
0894         stex_mu_intr(hba, data);
0895         spin_unlock_irqrestore(hba->host->host_lock, flags);
0896         if (unlikely(data & MU_OUTBOUND_DOORBELL_REQUEST_RESET &&
0897             hba->cardtype == st_shasta))
0898             queue_work(hba->work_q, &hba->reset_work);
0899         return IRQ_HANDLED;
0900     }
0901 
0902     spin_unlock_irqrestore(hba->host->host_lock, flags);
0903 
0904     return IRQ_NONE;
0905 }
0906 
0907 static void stex_ss_mu_intr(struct st_hba *hba)
0908 {
0909     struct status_msg *resp;
0910     struct st_ccb *ccb;
0911     __le32 *scratch;
0912     unsigned int size;
0913     int count = 0;
0914     u32 value;
0915     u16 tag;
0916 
0917     if (unlikely(hba->out_req_cnt <= 0 ||
0918             hba->mu_status == MU_STATE_RESETTING))
0919         return;
0920 
0921     while (count < hba->sts_count) {
0922         scratch = hba->scratch + hba->status_tail;
0923         value = le32_to_cpu(*scratch);
0924         if (unlikely(!(value & SS_STS_NORMAL)))
0925             return;
0926 
0927         resp = hba->status_buffer + hba->status_tail;
0928         *scratch = 0;
0929         ++count;
0930         ++hba->status_tail;
0931         hba->status_tail %= hba->sts_count+1;
0932 
0933         tag = (u16)value;
0934         if (unlikely(tag >= hba->host->can_queue)) {
0935             printk(KERN_WARNING DRV_NAME
0936                 "(%s): invalid tag\n", pci_name(hba->pdev));
0937             continue;
0938         }
0939 
0940         hba->out_req_cnt--;
0941         ccb = &hba->ccb[tag];
0942         if (unlikely(hba->wait_ccb == ccb))
0943             hba->wait_ccb = NULL;
0944         if (unlikely(ccb->req == NULL)) {
0945             printk(KERN_WARNING DRV_NAME
0946                 "(%s): lagging req\n", pci_name(hba->pdev));
0947             continue;
0948         }
0949 
0950         ccb->req = NULL;
0951         if (likely(value & SS_STS_DONE)) { /* normal case */
0952             ccb->srb_status = SRB_STATUS_SUCCESS;
0953             ccb->scsi_status = SAM_STAT_GOOD;
0954         } else {
0955             ccb->srb_status = resp->srb_status;
0956             ccb->scsi_status = resp->scsi_status;
0957             size = resp->payload_sz * sizeof(u32);
0958             if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
0959                 size > sizeof(*resp))) {
0960                 printk(KERN_WARNING DRV_NAME
0961                     "(%s): bad status size\n",
0962                     pci_name(hba->pdev));
0963             } else {
0964                 size -= sizeof(*resp) - STATUS_VAR_LEN;
0965                 if (size)
0966                     stex_copy_data(ccb, resp, size);
0967             }
0968             if (likely(ccb->cmd != NULL))
0969                 stex_check_cmd(hba, ccb, resp);
0970         }
0971 
0972         if (likely(ccb->cmd != NULL)) {
0973             scsi_dma_unmap(ccb->cmd);
0974             stex_scsi_done(ccb);
0975         } else
0976             ccb->req_type = 0;
0977     }
0978 }
0979 
0980 static irqreturn_t stex_ss_intr(int irq, void *__hba)
0981 {
0982     struct st_hba *hba = __hba;
0983     void __iomem *base = hba->mmio_base;
0984     u32 data;
0985     unsigned long flags;
0986 
0987     spin_lock_irqsave(hba->host->host_lock, flags);
0988 
0989     if (hba->cardtype == st_yel) {
0990         data = readl(base + YI2H_INT);
0991         if (data && data != 0xffffffff) {
0992             /* clear the interrupt */
0993             writel(data, base + YI2H_INT_C);
0994             stex_ss_mu_intr(hba);
0995             spin_unlock_irqrestore(hba->host->host_lock, flags);
0996             if (unlikely(data & SS_I2H_REQUEST_RESET))
0997                 queue_work(hba->work_q, &hba->reset_work);
0998             return IRQ_HANDLED;
0999         }
1000     } else {
1001         data = readl(base + PSCRATCH4);
1002         if (data != 0xffffffff) {
1003             if (data != 0) {
1004                 /* clear the interrupt */
1005                 writel(data, base + PSCRATCH1);
1006                 writel((1 << 22), base + YH2I_INT);
1007             }
1008             stex_ss_mu_intr(hba);
1009             spin_unlock_irqrestore(hba->host->host_lock, flags);
1010             if (unlikely(data & SS_I2H_REQUEST_RESET))
1011                 queue_work(hba->work_q, &hba->reset_work);
1012             return IRQ_HANDLED;
1013         }
1014     }
1015 
1016     spin_unlock_irqrestore(hba->host->host_lock, flags);
1017 
1018     return IRQ_NONE;
1019 }
1020 
1021 static int stex_common_handshake(struct st_hba *hba)
1022 {
1023     void __iomem *base = hba->mmio_base;
1024     struct handshake_frame *h;
1025     dma_addr_t status_phys;
1026     u32 data;
1027     unsigned long before;
1028 
1029     if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1030         writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1031         readl(base + IDBL);
1032         before = jiffies;
1033         while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1034             if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1035                 printk(KERN_ERR DRV_NAME
1036                     "(%s): no handshake signature\n",
1037                     pci_name(hba->pdev));
1038                 return -1;
1039             }
1040             rmb();
1041             msleep(1);
1042         }
1043     }
1044 
1045     udelay(10);
1046 
1047     data = readl(base + OMR1);
1048     if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
1049         data &= 0x0000ffff;
1050         if (hba->host->can_queue > data) {
1051             hba->host->can_queue = data;
1052             hba->host->cmd_per_lun = data;
1053         }
1054     }
1055 
1056     h = (struct handshake_frame *)hba->status_buffer;
1057     h->rb_phy = cpu_to_le64(hba->dma_handle);
1058     h->req_sz = cpu_to_le16(hba->rq_size);
1059     h->req_cnt = cpu_to_le16(hba->rq_count+1);
1060     h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1061     h->status_cnt = cpu_to_le16(hba->sts_count+1);
1062     h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1063     h->partner_type = HMU_PARTNER_TYPE;
1064     if (hba->extra_offset) {
1065         h->extra_offset = cpu_to_le32(hba->extra_offset);
1066         h->extra_size = cpu_to_le32(hba->dma_size - hba->extra_offset);
1067     } else
1068         h->extra_offset = h->extra_size = 0;
1069 
1070     status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
1071     writel(status_phys, base + IMR0);
1072     readl(base + IMR0);
1073     writel((status_phys >> 16) >> 16, base + IMR1);
1074     readl(base + IMR1);
1075 
1076     writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1077     readl(base + OMR0);
1078     writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1079     readl(base + IDBL); /* flush */
1080 
1081     udelay(10);
1082     before = jiffies;
1083     while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1084         if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1085             printk(KERN_ERR DRV_NAME
1086                 "(%s): no signature after handshake frame\n",
1087                 pci_name(hba->pdev));
1088             return -1;
1089         }
1090         rmb();
1091         msleep(1);
1092     }
1093 
1094     writel(0, base + IMR0);
1095     readl(base + IMR0);
1096     writel(0, base + OMR0);
1097     readl(base + OMR0);
1098     writel(0, base + IMR1);
1099     readl(base + IMR1);
1100     writel(0, base + OMR1);
1101     readl(base + OMR1); /* flush */
1102     return 0;
1103 }
1104 
1105 static int stex_ss_handshake(struct st_hba *hba)
1106 {
1107     void __iomem *base = hba->mmio_base;
1108     struct st_msg_header *msg_h;
1109     struct handshake_frame *h;
1110     __le32 *scratch;
1111     u32 data, scratch_size, mailboxdata, operationaldata;
1112     unsigned long before;
1113     int ret = 0;
1114 
1115     before = jiffies;
1116 
1117     if (hba->cardtype == st_yel) {
1118         operationaldata = readl(base + YIOA_STATUS);
1119         while (operationaldata != SS_MU_OPERATIONAL) {
1120             if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1121                 printk(KERN_ERR DRV_NAME
1122                     "(%s): firmware not operational\n",
1123                     pci_name(hba->pdev));
1124                 return -1;
1125             }
1126             msleep(1);
1127             operationaldata = readl(base + YIOA_STATUS);
1128         }
1129     } else {
1130         operationaldata = readl(base + PSCRATCH3);
1131         while (operationaldata != SS_MU_OPERATIONAL) {
1132             if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1133                 printk(KERN_ERR DRV_NAME
1134                     "(%s): firmware not operational\n",
1135                     pci_name(hba->pdev));
1136                 return -1;
1137             }
1138             msleep(1);
1139             operationaldata = readl(base + PSCRATCH3);
1140         }
1141     }
1142 
1143     msg_h = (struct st_msg_header *)hba->dma_mem;
1144     msg_h->handle = cpu_to_le64(hba->dma_handle);
1145     msg_h->flag = SS_HEAD_HANDSHAKE;
1146 
1147     h = (struct handshake_frame *)(msg_h + 1);
1148     h->rb_phy = cpu_to_le64(hba->dma_handle);
1149     h->req_sz = cpu_to_le16(hba->rq_size);
1150     h->req_cnt = cpu_to_le16(hba->rq_count+1);
1151     h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1152     h->status_cnt = cpu_to_le16(hba->sts_count+1);
1153     h->hosttime = cpu_to_le64(ktime_get_real_seconds());
1154     h->partner_type = HMU_PARTNER_TYPE;
1155     h->extra_offset = h->extra_size = 0;
1156     scratch_size = (hba->sts_count+1)*sizeof(u32);
1157     h->scratch_size = cpu_to_le32(scratch_size);
1158 
1159     if (hba->cardtype == st_yel) {
1160         data = readl(base + YINT_EN);
1161         data &= ~4;
1162         writel(data, base + YINT_EN);
1163         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1164         readl(base + YH2I_REQ_HI);
1165         writel(hba->dma_handle, base + YH2I_REQ);
1166         readl(base + YH2I_REQ); /* flush */
1167     } else {
1168         data = readl(base + YINT_EN);
1169         data &= ~(1 << 0);
1170         data &= ~(1 << 2);
1171         writel(data, base + YINT_EN);
1172         if (hba->msi_lock == 0) {
1173             /* P3 MSI Register cannot access twice */
1174             writel((1 << 6), base + YH2I_INT);
1175             hba->msi_lock  = 1;
1176         }
1177         writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1178         writel(hba->dma_handle, base + YH2I_REQ);
1179     }
1180 
1181     before = jiffies;
1182     scratch = hba->scratch;
1183     if (hba->cardtype == st_yel) {
1184         while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1185             if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1186                 printk(KERN_ERR DRV_NAME
1187                     "(%s): no signature after handshake frame\n",
1188                     pci_name(hba->pdev));
1189                 ret = -1;
1190                 break;
1191             }
1192             rmb();
1193             msleep(1);
1194         }
1195     } else {
1196         mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1197         while (mailboxdata != SS_STS_HANDSHAKE) {
1198             if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1199                 printk(KERN_ERR DRV_NAME
1200                     "(%s): no signature after handshake frame\n",
1201                     pci_name(hba->pdev));
1202                 ret = -1;
1203                 break;
1204             }
1205             rmb();
1206             msleep(1);
1207             mailboxdata = readl(base + MAILBOX_BASE + MAILBOX_HNDSHK_STS);
1208         }
1209     }
1210     memset(scratch, 0, scratch_size);
1211     msg_h->flag = 0;
1212 
1213     return ret;
1214 }
1215 
1216 static int stex_handshake(struct st_hba *hba)
1217 {
1218     int err;
1219     unsigned long flags;
1220     unsigned int mu_status;
1221 
1222     if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1223         err = stex_ss_handshake(hba);
1224     else
1225         err = stex_common_handshake(hba);
1226     spin_lock_irqsave(hba->host->host_lock, flags);
1227     mu_status = hba->mu_status;
1228     if (err == 0) {
1229         hba->req_head = 0;
1230         hba->req_tail = 0;
1231         hba->status_head = 0;
1232         hba->status_tail = 0;
1233         hba->out_req_cnt = 0;
1234         hba->mu_status = MU_STATE_STARTED;
1235     } else
1236         hba->mu_status = MU_STATE_FAILED;
1237     if (mu_status == MU_STATE_RESETTING)
1238         wake_up_all(&hba->reset_waitq);
1239     spin_unlock_irqrestore(hba->host->host_lock, flags);
1240     return err;
1241 }
1242 
1243 static int stex_abort(struct scsi_cmnd *cmd)
1244 {
1245     struct Scsi_Host *host = cmd->device->host;
1246     struct st_hba *hba = (struct st_hba *)host->hostdata;
1247     u16 tag = scsi_cmd_to_rq(cmd)->tag;
1248     void __iomem *base;
1249     u32 data;
1250     int result = SUCCESS;
1251     unsigned long flags;
1252 
1253     scmd_printk(KERN_INFO, cmd, "aborting command\n");
1254 
1255     base = hba->mmio_base;
1256     spin_lock_irqsave(host->host_lock, flags);
1257     if (tag < host->can_queue &&
1258         hba->ccb[tag].req && hba->ccb[tag].cmd == cmd)
1259         hba->wait_ccb = &hba->ccb[tag];
1260     else
1261         goto out;
1262 
1263     if (hba->cardtype == st_yel) {
1264         data = readl(base + YI2H_INT);
1265         if (data == 0 || data == 0xffffffff)
1266             goto fail_out;
1267 
1268         writel(data, base + YI2H_INT_C);
1269         stex_ss_mu_intr(hba);
1270     } else if (hba->cardtype == st_P3) {
1271         data = readl(base + PSCRATCH4);
1272         if (data == 0xffffffff)
1273             goto fail_out;
1274         if (data != 0) {
1275             writel(data, base + PSCRATCH1);
1276             writel((1 << 22), base + YH2I_INT);
1277         }
1278         stex_ss_mu_intr(hba);
1279     } else {
1280         data = readl(base + ODBL);
1281         if (data == 0 || data == 0xffffffff)
1282             goto fail_out;
1283 
1284         writel(data, base + ODBL);
1285         readl(base + ODBL); /* flush */
1286         stex_mu_intr(hba, data);
1287     }
1288     if (hba->wait_ccb == NULL) {
1289         printk(KERN_WARNING DRV_NAME
1290             "(%s): lost interrupt\n", pci_name(hba->pdev));
1291         goto out;
1292     }
1293 
1294 fail_out:
1295     scsi_dma_unmap(cmd);
1296     hba->wait_ccb->req = NULL; /* nullify the req's future return */
1297     hba->wait_ccb = NULL;
1298     result = FAILED;
1299 out:
1300     spin_unlock_irqrestore(host->host_lock, flags);
1301     return result;
1302 }
1303 
1304 static void stex_hard_reset(struct st_hba *hba)
1305 {
1306     struct pci_bus *bus;
1307     int i;
1308     u16 pci_cmd;
1309     u8 pci_bctl;
1310 
1311     for (i = 0; i < 16; i++)
1312         pci_read_config_dword(hba->pdev, i * 4,
1313             &hba->pdev->saved_config_space[i]);
1314 
1315     /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1316        secondary bus. Consult Intel 80331/3 developer's manual for detail */
1317     bus = hba->pdev->bus;
1318     pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1319     pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1320     pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1321 
1322     /*
1323      * 1 ms may be enough for 8-port controllers. But 16-port controllers
1324      * require more time to finish bus reset. Use 100 ms here for safety
1325      */
1326     msleep(100);
1327     pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1328     pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1329 
1330     for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
1331         pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
1332         if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
1333             break;
1334         msleep(1);
1335     }
1336 
1337     ssleep(5);
1338     for (i = 0; i < 16; i++)
1339         pci_write_config_dword(hba->pdev, i * 4,
1340             hba->pdev->saved_config_space[i]);
1341 }
1342 
1343 static int stex_yos_reset(struct st_hba *hba)
1344 {
1345     void __iomem *base;
1346     unsigned long flags, before;
1347     int ret = 0;
1348 
1349     base = hba->mmio_base;
1350     writel(MU_INBOUND_DOORBELL_RESET, base + IDBL);
1351     readl(base + IDBL); /* flush */
1352     before = jiffies;
1353     while (hba->out_req_cnt > 0) {
1354         if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1355             printk(KERN_WARNING DRV_NAME
1356                 "(%s): reset timeout\n", pci_name(hba->pdev));
1357             ret = -1;
1358             break;
1359         }
1360         msleep(1);
1361     }
1362 
1363     spin_lock_irqsave(hba->host->host_lock, flags);
1364     if (ret == -1)
1365         hba->mu_status = MU_STATE_FAILED;
1366     else
1367         hba->mu_status = MU_STATE_STARTED;
1368     wake_up_all(&hba->reset_waitq);
1369     spin_unlock_irqrestore(hba->host->host_lock, flags);
1370 
1371     return ret;
1372 }
1373 
1374 static void stex_ss_reset(struct st_hba *hba)
1375 {
1376     writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1377     readl(hba->mmio_base + YH2I_INT);
1378     ssleep(5);
1379 }
1380 
1381 static void stex_p3_reset(struct st_hba *hba)
1382 {
1383     writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1384     ssleep(5);
1385 }
1386 
1387 static int stex_do_reset(struct st_hba *hba)
1388 {
1389     unsigned long flags;
1390     unsigned int mu_status = MU_STATE_RESETTING;
1391 
1392     spin_lock_irqsave(hba->host->host_lock, flags);
1393     if (hba->mu_status == MU_STATE_STARTING) {
1394         spin_unlock_irqrestore(hba->host->host_lock, flags);
1395         printk(KERN_INFO DRV_NAME "(%s): request reset during init\n",
1396             pci_name(hba->pdev));
1397         return 0;
1398     }
1399     while (hba->mu_status == MU_STATE_RESETTING) {
1400         spin_unlock_irqrestore(hba->host->host_lock, flags);
1401         wait_event_timeout(hba->reset_waitq,
1402                    hba->mu_status != MU_STATE_RESETTING,
1403                    MU_MAX_DELAY * HZ);
1404         spin_lock_irqsave(hba->host->host_lock, flags);
1405         mu_status = hba->mu_status;
1406     }
1407 
1408     if (mu_status != MU_STATE_RESETTING) {
1409         spin_unlock_irqrestore(hba->host->host_lock, flags);
1410         return (mu_status == MU_STATE_STARTED) ? 0 : -1;
1411     }
1412 
1413     hba->mu_status = MU_STATE_RESETTING;
1414     spin_unlock_irqrestore(hba->host->host_lock, flags);
1415 
1416     if (hba->cardtype == st_yosemite)
1417         return stex_yos_reset(hba);
1418 
1419     if (hba->cardtype == st_shasta)
1420         stex_hard_reset(hba);
1421     else if (hba->cardtype == st_yel)
1422         stex_ss_reset(hba);
1423     else if (hba->cardtype == st_P3)
1424         stex_p3_reset(hba);
1425 
1426     return_abnormal_state(hba, DID_RESET);
1427 
1428     if (stex_handshake(hba) == 0)
1429         return 0;
1430 
1431     printk(KERN_WARNING DRV_NAME "(%s): resetting: handshake failed\n",
1432         pci_name(hba->pdev));
1433     return -1;
1434 }
1435 
1436 static int stex_reset(struct scsi_cmnd *cmd)
1437 {
1438     struct st_hba *hba;
1439 
1440     hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1441 
1442     shost_printk(KERN_INFO, cmd->device->host,
1443              "resetting host\n");
1444 
1445     return stex_do_reset(hba) ? FAILED : SUCCESS;
1446 }
1447 
1448 static void stex_reset_work(struct work_struct *work)
1449 {
1450     struct st_hba *hba = container_of(work, struct st_hba, reset_work);
1451 
1452     stex_do_reset(hba);
1453 }
1454 
1455 static int stex_biosparam(struct scsi_device *sdev,
1456     struct block_device *bdev, sector_t capacity, int geom[])
1457 {
1458     int heads = 255, sectors = 63;
1459 
1460     if (capacity < 0x200000) {
1461         heads = 64;
1462         sectors = 32;
1463     }
1464 
1465     sector_div(capacity, heads * sectors);
1466 
1467     geom[0] = heads;
1468     geom[1] = sectors;
1469     geom[2] = capacity;
1470 
1471     return 0;
1472 }
1473 
1474 static struct scsi_host_template driver_template = {
1475     .module             = THIS_MODULE,
1476     .name               = DRV_NAME,
1477     .proc_name          = DRV_NAME,
1478     .bios_param         = stex_biosparam,
1479     .queuecommand           = stex_queuecommand,
1480     .slave_configure        = stex_slave_config,
1481     .eh_abort_handler       = stex_abort,
1482     .eh_host_reset_handler      = stex_reset,
1483     .this_id            = -1,
1484     .dma_boundary           = PAGE_SIZE - 1,
1485 };
1486 
1487 static struct pci_device_id stex_pci_tbl[] = {
1488     /* st_shasta */
1489     { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1490         st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1491     { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1492         st_shasta }, /* SuperTrak EX12350 */
1493     { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1494         st_shasta }, /* SuperTrak EX4350 */
1495     { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1496         st_shasta }, /* SuperTrak EX24350 */
1497 
1498     /* st_vsc */
1499     { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1500 
1501     /* st_yosemite */
1502     { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
1503 
1504     /* st_seq */
1505     { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
1506 
1507     /* st_yel */
1508     { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1509     { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
1510 
1511     /* st_P3, pluto */
1512     { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1513         0x8870, 0, 0, st_P3 },
1514     /* st_P3, p3 */
1515     { PCI_VENDOR_ID_PROMISE, 0x8870, PCI_VENDOR_ID_PROMISE,
1516         0x4300, 0, 0, st_P3 },
1517 
1518     /* st_P3, SymplyStor4E */
1519     { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1520         0x4311, 0, 0, st_P3 },
1521     /* st_P3, SymplyStor8E */
1522     { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1523         0x4312, 0, 0, st_P3 },
1524     /* st_P3, SymplyStor4 */
1525     { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1526         0x4321, 0, 0, st_P3 },
1527     /* st_P3, SymplyStor8 */
1528     { PCI_VENDOR_ID_PROMISE, 0x8871, PCI_VENDOR_ID_PROMISE,
1529         0x4322, 0, 0, st_P3 },
1530     { } /* terminate list */
1531 };
1532 
1533 static struct st_card_info stex_card_info[] = {
1534     /* st_shasta */
1535     {
1536         .max_id     = 17,
1537         .max_lun    = 8,
1538         .max_channel    = 0,
1539         .rq_count   = 32,
1540         .rq_size    = 1048,
1541         .sts_count  = 32,
1542         .alloc_rq   = stex_alloc_req,
1543         .map_sg     = stex_map_sg,
1544         .send       = stex_send_cmd,
1545     },
1546 
1547     /* st_vsc */
1548     {
1549         .max_id     = 129,
1550         .max_lun    = 1,
1551         .max_channel    = 0,
1552         .rq_count   = 32,
1553         .rq_size    = 1048,
1554         .sts_count  = 32,
1555         .alloc_rq   = stex_alloc_req,
1556         .map_sg     = stex_map_sg,
1557         .send       = stex_send_cmd,
1558     },
1559 
1560     /* st_yosemite */
1561     {
1562         .max_id     = 2,
1563         .max_lun    = 256,
1564         .max_channel    = 0,
1565         .rq_count   = 256,
1566         .rq_size    = 1048,
1567         .sts_count  = 256,
1568         .alloc_rq   = stex_alloc_req,
1569         .map_sg     = stex_map_sg,
1570         .send       = stex_send_cmd,
1571     },
1572 
1573     /* st_seq */
1574     {
1575         .max_id     = 129,
1576         .max_lun    = 1,
1577         .max_channel    = 0,
1578         .rq_count   = 32,
1579         .rq_size    = 1048,
1580         .sts_count  = 32,
1581         .alloc_rq   = stex_alloc_req,
1582         .map_sg     = stex_map_sg,
1583         .send       = stex_send_cmd,
1584     },
1585 
1586     /* st_yel */
1587     {
1588         .max_id     = 129,
1589         .max_lun    = 256,
1590         .max_channel    = 3,
1591         .rq_count   = 801,
1592         .rq_size    = 512,
1593         .sts_count  = 801,
1594         .alloc_rq   = stex_ss_alloc_req,
1595         .map_sg     = stex_ss_map_sg,
1596         .send       = stex_ss_send_cmd,
1597     },
1598 
1599     /* st_P3 */
1600     {
1601         .max_id     = 129,
1602         .max_lun    = 256,
1603         .max_channel    = 0,
1604         .rq_count   = 801,
1605         .rq_size    = 512,
1606         .sts_count  = 801,
1607         .alloc_rq   = stex_ss_alloc_req,
1608         .map_sg     = stex_ss_map_sg,
1609         .send       = stex_ss_send_cmd,
1610     },
1611 };
1612 
1613 static int stex_request_irq(struct st_hba *hba)
1614 {
1615     struct pci_dev *pdev = hba->pdev;
1616     int status;
1617 
1618     if (msi || hba->cardtype == st_P3) {
1619         status = pci_enable_msi(pdev);
1620         if (status != 0)
1621             printk(KERN_ERR DRV_NAME
1622                 "(%s): error %d setting up MSI\n",
1623                 pci_name(pdev), status);
1624         else
1625             hba->msi_enabled = 1;
1626     } else
1627         hba->msi_enabled = 0;
1628 
1629     status = request_irq(pdev->irq,
1630         (hba->cardtype == st_yel || hba->cardtype == st_P3) ?
1631         stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
1632 
1633     if (status != 0) {
1634         if (hba->msi_enabled)
1635             pci_disable_msi(pdev);
1636     }
1637     return status;
1638 }
1639 
1640 static void stex_free_irq(struct st_hba *hba)
1641 {
1642     struct pci_dev *pdev = hba->pdev;
1643 
1644     free_irq(pdev->irq, hba);
1645     if (hba->msi_enabled)
1646         pci_disable_msi(pdev);
1647 }
1648 
1649 static int stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1650 {
1651     struct st_hba *hba;
1652     struct Scsi_Host *host;
1653     const struct st_card_info *ci = NULL;
1654     u32 sts_offset, cp_offset, scratch_offset;
1655     int err;
1656 
1657     err = pci_enable_device(pdev);
1658     if (err)
1659         return err;
1660 
1661     pci_set_master(pdev);
1662 
1663     S6flag = 0;
1664     register_reboot_notifier(&stex_notifier);
1665 
1666     host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1667 
1668     if (!host) {
1669         printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1670             pci_name(pdev));
1671         err = -ENOMEM;
1672         goto out_disable;
1673     }
1674 
1675     hba = (struct st_hba *)host->hostdata;
1676     memset(hba, 0, sizeof(struct st_hba));
1677 
1678     err = pci_request_regions(pdev, DRV_NAME);
1679     if (err < 0) {
1680         printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1681             pci_name(pdev));
1682         goto out_scsi_host_put;
1683     }
1684 
1685     hba->mmio_base = pci_ioremap_bar(pdev, 0);
1686     if ( !hba->mmio_base) {
1687         printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1688             pci_name(pdev));
1689         err = -ENOMEM;
1690         goto out_release_regions;
1691     }
1692 
1693     err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1694     if (err)
1695         err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1696     if (err) {
1697         printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1698             pci_name(pdev));
1699         goto out_iounmap;
1700     }
1701 
1702     hba->cardtype = (unsigned int) id->driver_data;
1703     ci = &stex_card_info[hba->cardtype];
1704     switch (id->subdevice) {
1705     case 0x4221:
1706     case 0x4222:
1707     case 0x4223:
1708     case 0x4224:
1709     case 0x4225:
1710     case 0x4226:
1711     case 0x4227:
1712     case 0x4261:
1713     case 0x4262:
1714     case 0x4263:
1715     case 0x4264:
1716     case 0x4265:
1717         break;
1718     default:
1719         if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1720             hba->supports_pm = 1;
1721     }
1722 
1723     sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1724     if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1725         sts_offset += (ci->sts_count+1) * sizeof(u32);
1726     cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1727     hba->dma_size = cp_offset + sizeof(struct st_frame);
1728     if (hba->cardtype == st_seq ||
1729         (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1730         hba->extra_offset = hba->dma_size;
1731         hba->dma_size += ST_ADDITIONAL_MEM;
1732     }
1733     hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1734         hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1735     if (!hba->dma_mem) {
1736         /* Retry minimum coherent mapping for st_seq and st_vsc */
1737         if (hba->cardtype == st_seq ||
1738             (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1739             printk(KERN_WARNING DRV_NAME
1740                 "(%s): allocating min buffer for controller\n",
1741                 pci_name(pdev));
1742             hba->dma_size = hba->extra_offset
1743                 + ST_ADDITIONAL_MEM_MIN;
1744             hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1745                 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
1746         }
1747 
1748         if (!hba->dma_mem) {
1749             err = -ENOMEM;
1750             printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1751                 pci_name(pdev));
1752             goto out_iounmap;
1753         }
1754     }
1755 
1756     hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1757     if (!hba->ccb) {
1758         err = -ENOMEM;
1759         printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1760             pci_name(pdev));
1761         goto out_pci_free;
1762     }
1763 
1764     if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1765         hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
1766     hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1767     hba->copy_buffer = hba->dma_mem + cp_offset;
1768     hba->rq_count = ci->rq_count;
1769     hba->rq_size = ci->rq_size;
1770     hba->sts_count = ci->sts_count;
1771     hba->alloc_rq = ci->alloc_rq;
1772     hba->map_sg = ci->map_sg;
1773     hba->send = ci->send;
1774     hba->mu_status = MU_STATE_STARTING;
1775     hba->msi_lock = 0;
1776 
1777     if (hba->cardtype == st_yel || hba->cardtype == st_P3)
1778         host->sg_tablesize = 38;
1779     else
1780         host->sg_tablesize = 32;
1781     host->can_queue = ci->rq_count;
1782     host->cmd_per_lun = ci->rq_count;
1783     host->max_id = ci->max_id;
1784     host->max_lun = ci->max_lun;
1785     host->max_channel = ci->max_channel;
1786     host->unique_id = host->host_no;
1787     host->max_cmd_len = STEX_CDB_LENGTH;
1788 
1789     hba->host = host;
1790     hba->pdev = pdev;
1791     init_waitqueue_head(&hba->reset_waitq);
1792 
1793     snprintf(hba->work_q_name, sizeof(hba->work_q_name),
1794          "stex_wq_%d", host->host_no);
1795     hba->work_q = create_singlethread_workqueue(hba->work_q_name);
1796     if (!hba->work_q) {
1797         printk(KERN_ERR DRV_NAME "(%s): create workqueue failed\n",
1798             pci_name(pdev));
1799         err = -ENOMEM;
1800         goto out_ccb_free;
1801     }
1802     INIT_WORK(&hba->reset_work, stex_reset_work);
1803 
1804     err = stex_request_irq(hba);
1805     if (err) {
1806         printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1807             pci_name(pdev));
1808         goto out_free_wq;
1809     }
1810 
1811     err = stex_handshake(hba);
1812     if (err)
1813         goto out_free_irq;
1814 
1815     pci_set_drvdata(pdev, hba);
1816 
1817     err = scsi_add_host(host, &pdev->dev);
1818     if (err) {
1819         printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1820             pci_name(pdev));
1821         goto out_free_irq;
1822     }
1823 
1824     scsi_scan_host(host);
1825 
1826     return 0;
1827 
1828 out_free_irq:
1829     stex_free_irq(hba);
1830 out_free_wq:
1831     destroy_workqueue(hba->work_q);
1832 out_ccb_free:
1833     kfree(hba->ccb);
1834 out_pci_free:
1835     dma_free_coherent(&pdev->dev, hba->dma_size,
1836               hba->dma_mem, hba->dma_handle);
1837 out_iounmap:
1838     iounmap(hba->mmio_base);
1839 out_release_regions:
1840     pci_release_regions(pdev);
1841 out_scsi_host_put:
1842     scsi_host_put(host);
1843 out_disable:
1844     pci_disable_device(pdev);
1845 
1846     return err;
1847 }
1848 
1849 static void stex_hba_stop(struct st_hba *hba, int st_sleep_mic)
1850 {
1851     struct req_msg *req;
1852     struct st_msg_header *msg_h;
1853     unsigned long flags;
1854     unsigned long before;
1855     u16 tag = 0;
1856 
1857     spin_lock_irqsave(hba->host->host_lock, flags);
1858 
1859     if ((hba->cardtype == st_yel || hba->cardtype == st_P3) &&
1860         hba->supports_pm == 1) {
1861         if (st_sleep_mic == ST_NOTHANDLED) {
1862             spin_unlock_irqrestore(hba->host->host_lock, flags);
1863             return;
1864         }
1865     }
1866     req = hba->alloc_rq(hba);
1867     if (hba->cardtype == st_yel || hba->cardtype == st_P3) {
1868         msg_h = (struct st_msg_header *)req - 1;
1869         memset(msg_h, 0, hba->rq_size);
1870     } else
1871         memset(req, 0, hba->rq_size);
1872 
1873     if ((hba->cardtype == st_yosemite || hba->cardtype == st_yel
1874         || hba->cardtype == st_P3)
1875         && st_sleep_mic == ST_IGNORED) {
1876         req->cdb[0] = MGT_CMD;
1877         req->cdb[1] = MGT_CMD_SIGNATURE;
1878         req->cdb[2] = CTLR_CONFIG_CMD;
1879         req->cdb[3] = CTLR_SHUTDOWN;
1880     } else if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1881         && st_sleep_mic != ST_IGNORED) {
1882         req->cdb[0] = MGT_CMD;
1883         req->cdb[1] = MGT_CMD_SIGNATURE;
1884         req->cdb[2] = CTLR_CONFIG_CMD;
1885         req->cdb[3] = PMIC_SHUTDOWN;
1886         req->cdb[4] = st_sleep_mic;
1887     } else {
1888         req->cdb[0] = CONTROLLER_CMD;
1889         req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1890         req->cdb[2] = CTLR_POWER_SAVING;
1891     }
1892     hba->ccb[tag].cmd = NULL;
1893     hba->ccb[tag].sg_count = 0;
1894     hba->ccb[tag].sense_bufflen = 0;
1895     hba->ccb[tag].sense_buffer = NULL;
1896     hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
1897     hba->send(hba, req, tag);
1898     spin_unlock_irqrestore(hba->host->host_lock, flags);
1899     before = jiffies;
1900     while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1901         if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1902             hba->ccb[tag].req_type = 0;
1903             hba->mu_status = MU_STATE_STOP;
1904             return;
1905         }
1906         msleep(1);
1907     }
1908     hba->mu_status = MU_STATE_STOP;
1909 }
1910 
1911 static void stex_hba_free(struct st_hba *hba)
1912 {
1913     stex_free_irq(hba);
1914 
1915     destroy_workqueue(hba->work_q);
1916 
1917     iounmap(hba->mmio_base);
1918 
1919     pci_release_regions(hba->pdev);
1920 
1921     kfree(hba->ccb);
1922 
1923     dma_free_coherent(&hba->pdev->dev, hba->dma_size,
1924               hba->dma_mem, hba->dma_handle);
1925 }
1926 
1927 static void stex_remove(struct pci_dev *pdev)
1928 {
1929     struct st_hba *hba = pci_get_drvdata(pdev);
1930 
1931     hba->mu_status = MU_STATE_NOCONNECT;
1932     return_abnormal_state(hba, DID_NO_CONNECT);
1933     scsi_remove_host(hba->host);
1934 
1935     scsi_block_requests(hba->host);
1936 
1937     stex_hba_free(hba);
1938 
1939     scsi_host_put(hba->host);
1940 
1941     pci_disable_device(pdev);
1942 
1943     unregister_reboot_notifier(&stex_notifier);
1944 }
1945 
1946 static void stex_shutdown(struct pci_dev *pdev)
1947 {
1948     struct st_hba *hba = pci_get_drvdata(pdev);
1949 
1950     if (hba->supports_pm == 0) {
1951         stex_hba_stop(hba, ST_IGNORED);
1952     } else if (hba->supports_pm == 1 && S6flag) {
1953         unregister_reboot_notifier(&stex_notifier);
1954         stex_hba_stop(hba, ST_S6);
1955     } else
1956         stex_hba_stop(hba, ST_S5);
1957 }
1958 
1959 static int stex_choice_sleep_mic(struct st_hba *hba, pm_message_t state)
1960 {
1961     switch (state.event) {
1962     case PM_EVENT_SUSPEND:
1963         return ST_S3;
1964     case PM_EVENT_HIBERNATE:
1965         hba->msi_lock = 0;
1966         return ST_S4;
1967     default:
1968         return ST_NOTHANDLED;
1969     }
1970 }
1971 
1972 static int stex_suspend(struct pci_dev *pdev, pm_message_t state)
1973 {
1974     struct st_hba *hba = pci_get_drvdata(pdev);
1975 
1976     if ((hba->cardtype == st_yel || hba->cardtype == st_P3)
1977         && hba->supports_pm == 1)
1978         stex_hba_stop(hba, stex_choice_sleep_mic(hba, state));
1979     else
1980         stex_hba_stop(hba, ST_IGNORED);
1981     return 0;
1982 }
1983 
1984 static int stex_resume(struct pci_dev *pdev)
1985 {
1986     struct st_hba *hba = pci_get_drvdata(pdev);
1987 
1988     hba->mu_status = MU_STATE_STARTING;
1989     stex_handshake(hba);
1990     return 0;
1991 }
1992 
1993 static int stex_halt(struct notifier_block *nb, unsigned long event, void *buf)
1994 {
1995     S6flag = 1;
1996     return NOTIFY_OK;
1997 }
1998 MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1999 
2000 static struct pci_driver stex_pci_driver = {
2001     .name       = DRV_NAME,
2002     .id_table   = stex_pci_tbl,
2003     .probe      = stex_probe,
2004     .remove     = stex_remove,
2005     .shutdown   = stex_shutdown,
2006     .suspend    = stex_suspend,
2007     .resume     = stex_resume,
2008 };
2009 
2010 static int __init stex_init(void)
2011 {
2012     printk(KERN_INFO DRV_NAME
2013         ": Promise SuperTrak EX Driver version: %s\n",
2014          ST_DRIVER_VERSION);
2015 
2016     return pci_register_driver(&stex_pci_driver);
2017 }
2018 
2019 static void __exit stex_exit(void)
2020 {
2021     pci_unregister_driver(&stex_pci_driver);
2022 }
2023 
2024 module_init(stex_init);
2025 module_exit(stex_exit);
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