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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  *    driver for Microchip PQI-based storage controllers
0004  *    Copyright (c) 2019-2022 Microchip Technology Inc. and its subsidiaries
0005  *    Copyright (c) 2016-2018 Microsemi Corporation
0006  *    Copyright (c) 2016 PMC-Sierra, Inc.
0007  *
0008  *    Questions/Comments/Bugfixes to storagedev@microchip.com
0009  *
0010  */
0011 
0012 #include <linux/io-64-nonatomic-lo-hi.h>
0013 
0014 #if !defined(_SMARTPQI_H)
0015 #define _SMARTPQI_H
0016 
0017 #include <scsi/scsi_host.h>
0018 #include <linux/bsg-lib.h>
0019 
0020 #pragma pack(1)
0021 
0022 #define PQI_DEVICE_SIGNATURE    "PQI DREG"
0023 
0024 /* This structure is defined by the PQI specification. */
0025 struct pqi_device_registers {
0026     __le64  signature;
0027     u8  function_and_status_code;
0028     u8  reserved[7];
0029     u8  max_admin_iq_elements;
0030     u8  max_admin_oq_elements;
0031     u8  admin_iq_element_length;    /* in 16-byte units */
0032     u8  admin_oq_element_length;    /* in 16-byte units */
0033     __le16  max_reset_timeout;      /* in 100-millisecond units */
0034     u8  reserved1[2];
0035     __le32  legacy_intx_status;
0036     __le32  legacy_intx_mask_set;
0037     __le32  legacy_intx_mask_clear;
0038     u8  reserved2[28];
0039     __le32  device_status;
0040     u8  reserved3[4];
0041     __le64  admin_iq_pi_offset;
0042     __le64  admin_oq_ci_offset;
0043     __le64  admin_iq_element_array_addr;
0044     __le64  admin_oq_element_array_addr;
0045     __le64  admin_iq_ci_addr;
0046     __le64  admin_oq_pi_addr;
0047     u8  admin_iq_num_elements;
0048     u8  admin_oq_num_elements;
0049     __le16  admin_queue_int_msg_num;
0050     u8  reserved4[4];
0051     __le32  device_error;
0052     u8  reserved5[4];
0053     __le64  error_details;
0054     __le32  device_reset;
0055     __le32  power_action;
0056     u8  reserved6[104];
0057 };
0058 
0059 /*
0060  * controller registers
0061  *
0062  * These are defined by the Microchip implementation.
0063  *
0064  * Some registers (those named sis_*) are only used when in
0065  * legacy SIS mode before we transition the controller into
0066  * PQI mode.  There are a number of other SIS mode registers,
0067  * but we don't use them, so only the SIS registers that we
0068  * care about are defined here.  The offsets mentioned in the
0069  * comments are the offsets from the PCIe BAR 0.
0070  */
0071 struct pqi_ctrl_registers {
0072     u8  reserved[0x20];
0073     __le32  sis_host_to_ctrl_doorbell;      /* 20h */
0074     u8  reserved1[0x34 - (0x20 + sizeof(__le32))];
0075     __le32  sis_interrupt_mask;         /* 34h */
0076     u8  reserved2[0x9c - (0x34 + sizeof(__le32))];
0077     __le32  sis_ctrl_to_host_doorbell;      /* 9Ch */
0078     u8  reserved3[0xa0 - (0x9c + sizeof(__le32))];
0079     __le32  sis_ctrl_to_host_doorbell_clear;    /* A0h */
0080     u8  reserved4[0xb0 - (0xa0 + sizeof(__le32))];
0081     __le32  sis_driver_scratch;         /* B0h */
0082     __le32  sis_product_identifier;         /* B4h */
0083     u8  reserved5[0xbc - (0xb4 + sizeof(__le32))];
0084     __le32  sis_firmware_status;            /* BCh */
0085     u8  reserved6[0xcc - (0xbc + sizeof(__le32))];
0086     __le32  sis_ctrl_shutdown_reason_code;      /* CCh */
0087     u8  reserved7[0x1000 - (0xcc + sizeof(__le32))];
0088     __le32  sis_mailbox[8];             /* 1000h */
0089     u8  reserved8[0x4000 - (0x1000 + (sizeof(__le32) * 8))];
0090     /*
0091      * The PQI spec states that the PQI registers should be at
0092      * offset 0 from the PCIe BAR 0.  However, we can't map
0093      * them at offset 0 because that would break compatibility
0094      * with the SIS registers.  So we map them at offset 4000h.
0095      */
0096     struct pqi_device_registers pqi_registers;  /* 4000h */
0097 };
0098 
0099 #define PQI_DEVICE_REGISTERS_OFFSET 0x4000
0100 
0101 /* shutdown reasons for taking the controller offline */
0102 enum pqi_ctrl_shutdown_reason {
0103     PQI_IQ_NOT_DRAINED_TIMEOUT = 1,
0104     PQI_LUN_RESET_TIMEOUT = 2,
0105     PQI_IO_PENDING_POST_LUN_RESET_TIMEOUT = 3,
0106     PQI_NO_HEARTBEAT = 4,
0107     PQI_FIRMWARE_KERNEL_NOT_UP = 5,
0108     PQI_OFA_RESPONSE_TIMEOUT = 6,
0109     PQI_INVALID_REQ_ID = 7,
0110     PQI_UNMATCHED_REQ_ID = 8,
0111     PQI_IO_PI_OUT_OF_RANGE = 9,
0112     PQI_EVENT_PI_OUT_OF_RANGE = 10,
0113     PQI_UNEXPECTED_IU_TYPE = 11
0114 };
0115 
0116 enum pqi_io_path {
0117     RAID_PATH = 0,
0118     AIO_PATH = 1
0119 };
0120 
0121 enum pqi_irq_mode {
0122     IRQ_MODE_NONE,
0123     IRQ_MODE_INTX,
0124     IRQ_MODE_MSIX
0125 };
0126 
0127 struct pqi_sg_descriptor {
0128     __le64  address;
0129     __le32  length;
0130     __le32  flags;
0131 };
0132 
0133 /* manifest constants for the flags field of pqi_sg_descriptor */
0134 #define CISS_SG_LAST    0x40000000
0135 #define CISS_SG_CHAIN   0x80000000
0136 
0137 struct pqi_iu_header {
0138     u8  iu_type;
0139     u8  reserved;
0140     __le16  iu_length;  /* in bytes - does not include the length */
0141                 /* of this header */
0142     __le16  response_queue_id;  /* specifies the OQ where the */
0143                     /* response IU is to be delivered */
0144     u16 driver_flags;   /* reserved for driver use */
0145 };
0146 
0147 /* manifest constants for pqi_iu_header.driver_flags */
0148 #define PQI_DRIVER_NONBLOCKABLE_REQUEST     0x1
0149 
0150 /*
0151  * According to the PQI spec, the IU header is only the first 4 bytes of our
0152  * pqi_iu_header structure.
0153  */
0154 #define PQI_REQUEST_HEADER_LENGTH   4
0155 
0156 struct pqi_general_admin_request {
0157     struct pqi_iu_header header;
0158     __le16  request_id;
0159     u8  function_code;
0160     union {
0161         struct {
0162             u8  reserved[33];
0163             __le32  buffer_length;
0164             struct pqi_sg_descriptor sg_descriptor;
0165         } report_device_capability;
0166 
0167         struct {
0168             u8  reserved;
0169             __le16  queue_id;
0170             u8  reserved1[2];
0171             __le64  element_array_addr;
0172             __le64  ci_addr;
0173             __le16  num_elements;
0174             __le16  element_length;
0175             u8  queue_protocol;
0176             u8  reserved2[23];
0177             __le32  vendor_specific;
0178         } create_operational_iq;
0179 
0180         struct {
0181             u8  reserved;
0182             __le16  queue_id;
0183             u8  reserved1[2];
0184             __le64  element_array_addr;
0185             __le64  pi_addr;
0186             __le16  num_elements;
0187             __le16  element_length;
0188             u8  queue_protocol;
0189             u8  reserved2[3];
0190             __le16  int_msg_num;
0191             __le16  coalescing_count;
0192             __le32  min_coalescing_time;
0193             __le32  max_coalescing_time;
0194             u8  reserved3[8];
0195             __le32  vendor_specific;
0196         } create_operational_oq;
0197 
0198         struct {
0199             u8  reserved;
0200             __le16  queue_id;
0201             u8  reserved1[50];
0202         } delete_operational_queue;
0203 
0204         struct {
0205             u8  reserved;
0206             __le16  queue_id;
0207             u8  reserved1[46];
0208             __le32  vendor_specific;
0209         } change_operational_iq_properties;
0210 
0211     } data;
0212 };
0213 
0214 struct pqi_general_admin_response {
0215     struct pqi_iu_header header;
0216     __le16  request_id;
0217     u8  function_code;
0218     u8  status;
0219     union {
0220         struct {
0221             u8  status_descriptor[4];
0222             __le64  iq_pi_offset;
0223             u8  reserved[40];
0224         } create_operational_iq;
0225 
0226         struct {
0227             u8  status_descriptor[4];
0228             __le64  oq_ci_offset;
0229             u8  reserved[40];
0230         } create_operational_oq;
0231     } data;
0232 };
0233 
0234 struct pqi_iu_layer_descriptor {
0235     u8  inbound_spanning_supported : 1;
0236     u8  reserved : 7;
0237     u8  reserved1[5];
0238     __le16  max_inbound_iu_length;
0239     u8  outbound_spanning_supported : 1;
0240     u8  reserved2 : 7;
0241     u8  reserved3[5];
0242     __le16  max_outbound_iu_length;
0243 };
0244 
0245 struct pqi_device_capability {
0246     __le16  data_length;
0247     u8  reserved[6];
0248     u8  iq_arbitration_priority_support_bitmask;
0249     u8  maximum_aw_a;
0250     u8  maximum_aw_b;
0251     u8  maximum_aw_c;
0252     u8  max_arbitration_burst : 3;
0253     u8  reserved1 : 4;
0254     u8  iqa : 1;
0255     u8  reserved2[2];
0256     u8  iq_freeze : 1;
0257     u8  reserved3 : 7;
0258     __le16  max_inbound_queues;
0259     __le16  max_elements_per_iq;
0260     u8  reserved4[4];
0261     __le16  max_iq_element_length;
0262     __le16  min_iq_element_length;
0263     u8  reserved5[2];
0264     __le16  max_outbound_queues;
0265     __le16  max_elements_per_oq;
0266     __le16  intr_coalescing_time_granularity;
0267     __le16  max_oq_element_length;
0268     __le16  min_oq_element_length;
0269     u8  reserved6[24];
0270     struct pqi_iu_layer_descriptor iu_layer_descriptors[32];
0271 };
0272 
0273 #define PQI_MAX_EMBEDDED_SG_DESCRIPTORS     4
0274 #define PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS 3
0275 
0276 struct pqi_raid_path_request {
0277     struct pqi_iu_header header;
0278     __le16  request_id;
0279     __le16  nexus_id;
0280     __le32  buffer_length;
0281     u8  lun_number[8];
0282     __le16  protocol_specific;
0283     u8  data_direction : 2;
0284     u8  partial : 1;
0285     u8  reserved1 : 4;
0286     u8  fence : 1;
0287     __le16  error_index;
0288     u8  reserved2;
0289     u8  task_attribute : 3;
0290     u8  command_priority : 4;
0291     u8  reserved3 : 1;
0292     u8  reserved4 : 2;
0293     u8  additional_cdb_bytes_usage : 3;
0294     u8  reserved5 : 3;
0295     u8  cdb[16];
0296     u8  reserved6[11];
0297     u8  ml_device_lun_number;
0298     __le32  timeout;
0299     struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
0300 };
0301 
0302 struct pqi_aio_path_request {
0303     struct pqi_iu_header header;
0304     __le16  request_id;
0305     u8  reserved1[2];
0306     __le32  nexus_id;
0307     __le32  buffer_length;
0308     u8  data_direction : 2;
0309     u8  partial : 1;
0310     u8  memory_type : 1;
0311     u8  fence : 1;
0312     u8  encryption_enable : 1;
0313     u8  reserved2 : 2;
0314     u8  task_attribute : 3;
0315     u8  command_priority : 4;
0316     u8  reserved3 : 1;
0317     __le16  data_encryption_key_index;
0318     __le32  encrypt_tweak_lower;
0319     __le32  encrypt_tweak_upper;
0320     u8  cdb[16];
0321     __le16  error_index;
0322     u8  num_sg_descriptors;
0323     u8  cdb_length;
0324     u8  lun_number[8];
0325     u8  reserved4[4];
0326     struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
0327 };
0328 
0329 #define PQI_RAID1_NVME_XFER_LIMIT   (32 * 1024) /* 32 KiB */
0330 
0331 struct pqi_aio_r1_path_request {
0332     struct pqi_iu_header header;
0333     __le16  request_id;
0334     __le16  volume_id;  /* ID of the RAID volume */
0335     __le32  it_nexus_1; /* IT nexus of the 1st drive in the RAID volume */
0336     __le32  it_nexus_2; /* IT nexus of the 2nd drive in the RAID volume */
0337     __le32  it_nexus_3; /* IT nexus of the 3rd drive in the RAID volume */
0338     __le32  data_length;    /* total bytes to read/write */
0339     u8  data_direction : 2;
0340     u8  partial : 1;
0341     u8  memory_type : 1;
0342     u8  fence : 1;
0343     u8  encryption_enable : 1;
0344     u8  reserved : 2;
0345     u8  task_attribute : 3;
0346     u8  command_priority : 4;
0347     u8  reserved2 : 1;
0348     __le16  data_encryption_key_index;
0349     u8  cdb[16];
0350     __le16  error_index;
0351     u8  num_sg_descriptors;
0352     u8  cdb_length;
0353     u8  num_drives; /* number of drives in the RAID volume (2 or 3) */
0354     u8  reserved3[3];
0355     __le32  encrypt_tweak_lower;
0356     __le32  encrypt_tweak_upper;
0357     struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_SG_DESCRIPTORS];
0358 };
0359 
0360 #define PQI_DEFAULT_MAX_WRITE_RAID_5_6          (8 * 1024U)
0361 #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_SAS_SATA (~0U)
0362 #define PQI_DEFAULT_MAX_TRANSFER_ENCRYPTED_NVME     (32 * 1024U)
0363 
0364 struct pqi_aio_r56_path_request {
0365     struct pqi_iu_header header;
0366     __le16  request_id;
0367     __le16  volume_id;      /* ID of the RAID volume */
0368     __le32  data_it_nexus;      /* IT nexus for the data drive */
0369     __le32  p_parity_it_nexus;  /* IT nexus for the P parity drive */
0370     __le32  q_parity_it_nexus;  /* IT nexus for the Q parity drive */
0371     __le32  data_length;        /* total bytes to read/write */
0372     u8  data_direction : 2;
0373     u8  partial : 1;
0374     u8  mem_type : 1;       /* 0 = PCIe, 1 = DDR */
0375     u8  fence : 1;
0376     u8  encryption_enable : 1;
0377     u8  reserved : 2;
0378     u8  task_attribute : 3;
0379     u8  command_priority : 4;
0380     u8  reserved1 : 1;
0381     __le16  data_encryption_key_index;
0382     u8  cdb[16];
0383     __le16  error_index;
0384     u8  num_sg_descriptors;
0385     u8  cdb_length;
0386     u8  xor_multiplier;
0387     u8  reserved2[3];
0388     __le32  encrypt_tweak_lower;
0389     __le32  encrypt_tweak_upper;
0390     __le64  row;            /* row = logical LBA/blocks per row */
0391     u8  reserved3[8];
0392     struct pqi_sg_descriptor sg_descriptors[PQI_MAX_EMBEDDED_R56_SG_DESCRIPTORS];
0393 };
0394 
0395 struct pqi_io_response {
0396     struct pqi_iu_header header;
0397     __le16  request_id;
0398     __le16  error_index;
0399     u8  reserved2[4];
0400 };
0401 
0402 struct pqi_general_management_request {
0403     struct pqi_iu_header header;
0404     __le16  request_id;
0405     union {
0406         struct {
0407             u8  reserved[2];
0408             __le32  buffer_length;
0409             struct pqi_sg_descriptor sg_descriptors[3];
0410         } report_event_configuration;
0411 
0412         struct {
0413             __le16  global_event_oq_id;
0414             __le32  buffer_length;
0415             struct pqi_sg_descriptor sg_descriptors[3];
0416         } set_event_configuration;
0417     } data;
0418 };
0419 
0420 struct pqi_event_descriptor {
0421     u8  event_type;
0422     u8  reserved;
0423     __le16  oq_id;
0424 };
0425 
0426 struct pqi_event_config {
0427     u8  reserved[2];
0428     u8  num_event_descriptors;
0429     u8  reserved1;
0430     struct pqi_event_descriptor descriptors[];
0431 };
0432 
0433 #define PQI_MAX_EVENT_DESCRIPTORS   255
0434 
0435 #define PQI_EVENT_OFA_MEMORY_ALLOCATION 0x0
0436 #define PQI_EVENT_OFA_QUIESCE       0x1
0437 #define PQI_EVENT_OFA_CANCELED      0x2
0438 
0439 struct pqi_event_response {
0440     struct pqi_iu_header header;
0441     u8  event_type;
0442     u8  reserved2 : 7;
0443     u8  request_acknowledge : 1;
0444     __le16  event_id;
0445     __le32  additional_event_id;
0446     union {
0447         struct {
0448             __le32  bytes_requested;
0449             u8  reserved[12];
0450         } ofa_memory_allocation;
0451 
0452         struct {
0453             __le16  reason;     /* reason for cancellation */
0454             u8  reserved[14];
0455         } ofa_cancelled;
0456     } data;
0457 };
0458 
0459 struct pqi_event_acknowledge_request {
0460     struct pqi_iu_header header;
0461     u8  event_type;
0462     u8  reserved2;
0463     __le16  event_id;
0464     __le32  additional_event_id;
0465 };
0466 
0467 struct pqi_task_management_request {
0468     struct pqi_iu_header header;
0469     __le16  request_id;
0470     __le16  nexus_id;
0471     u8  reserved;
0472     u8  ml_device_lun_number;
0473     __le16  timeout;
0474     u8  lun_number[8];
0475     __le16  protocol_specific;
0476     __le16  outbound_queue_id_to_manage;
0477     __le16  request_id_to_manage;
0478     u8  task_management_function;
0479     u8  reserved2 : 7;
0480     u8  fence : 1;
0481 };
0482 
0483 #define SOP_TASK_MANAGEMENT_LUN_RESET   0x8
0484 
0485 struct pqi_task_management_response {
0486     struct pqi_iu_header header;
0487     __le16  request_id;
0488     __le16  nexus_id;
0489     u8  additional_response_info[3];
0490     u8  response_code;
0491 };
0492 
0493 struct pqi_vendor_general_request {
0494     struct pqi_iu_header header;
0495     __le16  request_id;
0496     __le16  function_code;
0497     union {
0498         struct {
0499             __le16  first_section;
0500             __le16  last_section;
0501             u8  reserved[48];
0502         } config_table_update;
0503 
0504         struct {
0505             __le64  buffer_address;
0506             __le32  buffer_length;
0507             u8  reserved[40];
0508         } ofa_memory_allocation;
0509     } data;
0510 };
0511 
0512 struct pqi_vendor_general_response {
0513     struct pqi_iu_header header;
0514     __le16  request_id;
0515     __le16  function_code;
0516     __le16  status;
0517     u8  reserved[2];
0518 };
0519 
0520 #define PQI_VENDOR_GENERAL_CONFIG_TABLE_UPDATE  0
0521 #define PQI_VENDOR_GENERAL_HOST_MEMORY_UPDATE   1
0522 
0523 #define PQI_OFA_VERSION         1
0524 #define PQI_OFA_SIGNATURE       "OFA_QRM"
0525 #define PQI_OFA_MAX_SG_DESCRIPTORS  64
0526 
0527 struct pqi_ofa_memory {
0528     __le64  signature;  /* "OFA_QRM" */
0529     __le16  version;    /* version of this struct (1 = 1st version) */
0530     u8  reserved[62];
0531     __le32  bytes_allocated;    /* total allocated memory in bytes */
0532     __le16  num_memory_descriptors;
0533     u8  reserved1[2];
0534     struct pqi_sg_descriptor sg_descriptor[PQI_OFA_MAX_SG_DESCRIPTORS];
0535 };
0536 
0537 struct pqi_aio_error_info {
0538     u8  status;
0539     u8  service_response;
0540     u8  data_present;
0541     u8  reserved;
0542     __le32  residual_count;
0543     __le16  data_length;
0544     __le16  reserved1;
0545     u8  data[256];
0546 };
0547 
0548 struct pqi_raid_error_info {
0549     u8  data_in_result;
0550     u8  data_out_result;
0551     u8  reserved[3];
0552     u8  status;
0553     __le16  status_qualifier;
0554     __le16  sense_data_length;
0555     __le16  response_data_length;
0556     __le32  data_in_transferred;
0557     __le32  data_out_transferred;
0558     u8  data[256];
0559 };
0560 
0561 #define PQI_REQUEST_IU_TASK_MANAGEMENT          0x13
0562 #define PQI_REQUEST_IU_RAID_PATH_IO         0x14
0563 #define PQI_REQUEST_IU_AIO_PATH_IO          0x15
0564 #define PQI_REQUEST_IU_AIO_PATH_RAID5_IO        0x18
0565 #define PQI_REQUEST_IU_AIO_PATH_RAID6_IO        0x19
0566 #define PQI_REQUEST_IU_AIO_PATH_RAID1_IO        0x1A
0567 #define PQI_REQUEST_IU_GENERAL_ADMIN            0x60
0568 #define PQI_REQUEST_IU_REPORT_VENDOR_EVENT_CONFIG   0x72
0569 #define PQI_REQUEST_IU_SET_VENDOR_EVENT_CONFIG      0x73
0570 #define PQI_REQUEST_IU_VENDOR_GENERAL           0x75
0571 #define PQI_REQUEST_IU_ACKNOWLEDGE_VENDOR_EVENT     0xf6
0572 
0573 #define PQI_RESPONSE_IU_GENERAL_MANAGEMENT      0x81
0574 #define PQI_RESPONSE_IU_TASK_MANAGEMENT         0x93
0575 #define PQI_RESPONSE_IU_GENERAL_ADMIN           0xe0
0576 #define PQI_RESPONSE_IU_RAID_PATH_IO_SUCCESS        0xf0
0577 #define PQI_RESPONSE_IU_AIO_PATH_IO_SUCCESS     0xf1
0578 #define PQI_RESPONSE_IU_RAID_PATH_IO_ERROR      0xf2
0579 #define PQI_RESPONSE_IU_AIO_PATH_IO_ERROR       0xf3
0580 #define PQI_RESPONSE_IU_AIO_PATH_DISABLED       0xf4
0581 #define PQI_RESPONSE_IU_VENDOR_EVENT            0xf5
0582 #define PQI_RESPONSE_IU_VENDOR_GENERAL          0xf7
0583 
0584 #define PQI_GENERAL_ADMIN_FUNCTION_REPORT_DEVICE_CAPABILITY 0x0
0585 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_IQ            0x10
0586 #define PQI_GENERAL_ADMIN_FUNCTION_CREATE_OQ            0x11
0587 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_IQ            0x12
0588 #define PQI_GENERAL_ADMIN_FUNCTION_DELETE_OQ            0x13
0589 #define PQI_GENERAL_ADMIN_FUNCTION_CHANGE_IQ_PROPERTY       0x14
0590 
0591 #define PQI_GENERAL_ADMIN_STATUS_SUCCESS    0x0
0592 
0593 #define PQI_IQ_PROPERTY_IS_AIO_QUEUE    0x1
0594 
0595 #define PQI_GENERAL_ADMIN_IU_LENGTH     0x3c
0596 #define PQI_PROTOCOL_SOP            0x0
0597 
0598 #define PQI_DATA_IN_OUT_GOOD                    0x0
0599 #define PQI_DATA_IN_OUT_UNDERFLOW               0x1
0600 #define PQI_DATA_IN_OUT_BUFFER_ERROR                0x40
0601 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW             0x41
0602 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_DESCRIPTOR_AREA     0x42
0603 #define PQI_DATA_IN_OUT_BUFFER_OVERFLOW_BRIDGE          0x43
0604 #define PQI_DATA_IN_OUT_PCIE_FABRIC_ERROR           0x60
0605 #define PQI_DATA_IN_OUT_PCIE_COMPLETION_TIMEOUT         0x61
0606 #define PQI_DATA_IN_OUT_PCIE_COMPLETER_ABORT_RECEIVED       0x62
0607 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST_RECEIVED   0x63
0608 #define PQI_DATA_IN_OUT_PCIE_ECRC_CHECK_FAILED          0x64
0609 #define PQI_DATA_IN_OUT_PCIE_UNSUPPORTED_REQUEST        0x65
0610 #define PQI_DATA_IN_OUT_PCIE_ACS_VIOLATION          0x66
0611 #define PQI_DATA_IN_OUT_PCIE_TLP_PREFIX_BLOCKED         0x67
0612 #define PQI_DATA_IN_OUT_PCIE_POISONED_MEMORY_READ       0x6F
0613 #define PQI_DATA_IN_OUT_ERROR                   0xf0
0614 #define PQI_DATA_IN_OUT_PROTOCOL_ERROR              0xf1
0615 #define PQI_DATA_IN_OUT_HARDWARE_ERROR              0xf2
0616 #define PQI_DATA_IN_OUT_UNSOLICITED_ABORT           0xf3
0617 #define PQI_DATA_IN_OUT_ABORTED                 0xf4
0618 #define PQI_DATA_IN_OUT_TIMEOUT                 0xf5
0619 
0620 #define CISS_CMD_STATUS_SUCCESS         0x0
0621 #define CISS_CMD_STATUS_TARGET_STATUS       0x1
0622 #define CISS_CMD_STATUS_DATA_UNDERRUN       0x2
0623 #define CISS_CMD_STATUS_DATA_OVERRUN        0x3
0624 #define CISS_CMD_STATUS_INVALID         0x4
0625 #define CISS_CMD_STATUS_PROTOCOL_ERROR      0x5
0626 #define CISS_CMD_STATUS_HARDWARE_ERROR      0x6
0627 #define CISS_CMD_STATUS_CONNECTION_LOST     0x7
0628 #define CISS_CMD_STATUS_ABORTED         0x8
0629 #define CISS_CMD_STATUS_ABORT_FAILED        0x9
0630 #define CISS_CMD_STATUS_UNSOLICITED_ABORT   0xa
0631 #define CISS_CMD_STATUS_TIMEOUT         0xb
0632 #define CISS_CMD_STATUS_UNABORTABLE     0xc
0633 #define CISS_CMD_STATUS_TMF         0xd
0634 #define CISS_CMD_STATUS_AIO_DISABLED        0xe
0635 
0636 #define PQI_CMD_STATUS_ABORTED  CISS_CMD_STATUS_ABORTED
0637 
0638 #define PQI_NUM_EVENT_QUEUE_ELEMENTS    32
0639 #define PQI_EVENT_OQ_ELEMENT_LENGTH sizeof(struct pqi_event_response)
0640 
0641 #define PQI_EVENT_TYPE_HOTPLUG          0x1
0642 #define PQI_EVENT_TYPE_HARDWARE         0x2
0643 #define PQI_EVENT_TYPE_PHYSICAL_DEVICE      0x4
0644 #define PQI_EVENT_TYPE_LOGICAL_DEVICE       0x5
0645 #define PQI_EVENT_TYPE_OFA          0xfb
0646 #define PQI_EVENT_TYPE_AIO_STATE_CHANGE     0xfd
0647 #define PQI_EVENT_TYPE_AIO_CONFIG_CHANGE    0xfe
0648 
0649 #pragma pack()
0650 
0651 #define PQI_ERROR_BUFFER_ELEMENT_LENGTH     \
0652     sizeof(struct pqi_raid_error_info)
0653 
0654 /* these values are based on our implementation */
0655 #define PQI_ADMIN_IQ_NUM_ELEMENTS       8
0656 #define PQI_ADMIN_OQ_NUM_ELEMENTS       20
0657 #define PQI_ADMIN_IQ_ELEMENT_LENGTH     64
0658 #define PQI_ADMIN_OQ_ELEMENT_LENGTH     64
0659 
0660 #define PQI_OPERATIONAL_IQ_ELEMENT_LENGTH   128
0661 #define PQI_OPERATIONAL_OQ_ELEMENT_LENGTH   16
0662 
0663 #define PQI_MIN_MSIX_VECTORS        1
0664 #define PQI_MAX_MSIX_VECTORS        64
0665 
0666 /* these values are defined by the PQI spec */
0667 #define PQI_MAX_NUM_ELEMENTS_ADMIN_QUEUE    255
0668 #define PQI_MAX_NUM_ELEMENTS_OPERATIONAL_QUEUE  65535
0669 
0670 #define PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT   64
0671 #define PQI_QUEUE_ELEMENT_LENGTH_ALIGNMENT  16
0672 #define PQI_ADMIN_INDEX_ALIGNMENT       64
0673 #define PQI_OPERATIONAL_INDEX_ALIGNMENT     4
0674 
0675 #define PQI_MIN_OPERATIONAL_QUEUE_ID        1
0676 #define PQI_MAX_OPERATIONAL_QUEUE_ID        65535
0677 
0678 #define PQI_AIO_SERV_RESPONSE_COMPLETE      0
0679 #define PQI_AIO_SERV_RESPONSE_FAILURE       1
0680 #define PQI_AIO_SERV_RESPONSE_TMF_COMPLETE  2
0681 #define PQI_AIO_SERV_RESPONSE_TMF_SUCCEEDED 3
0682 #define PQI_AIO_SERV_RESPONSE_TMF_REJECTED  4
0683 #define PQI_AIO_SERV_RESPONSE_TMF_INCORRECT_LUN 5
0684 
0685 #define PQI_AIO_STATUS_IO_ERROR         0x1
0686 #define PQI_AIO_STATUS_IO_ABORTED       0x2
0687 #define PQI_AIO_STATUS_NO_PATH_TO_DEVICE    0x3
0688 #define PQI_AIO_STATUS_INVALID_DEVICE       0x4
0689 #define PQI_AIO_STATUS_AIO_PATH_DISABLED    0xe
0690 #define PQI_AIO_STATUS_UNDERRUN         0x51
0691 #define PQI_AIO_STATUS_OVERRUN          0x75
0692 
0693 typedef u32 pqi_index_t;
0694 
0695 /* SOP data direction flags */
0696 #define SOP_NO_DIRECTION_FLAG   0
0697 #define SOP_WRITE_FLAG      1   /* host writes data to Data-Out */
0698                     /* buffer */
0699 #define SOP_READ_FLAG       2   /* host receives data from Data-In */
0700                     /* buffer */
0701 #define SOP_BIDIRECTIONAL   3   /* data is transferred from the */
0702                     /* Data-Out buffer and data is */
0703                     /* transferred to the Data-In buffer */
0704 
0705 #define SOP_TASK_ATTRIBUTE_SIMPLE       0
0706 #define SOP_TASK_ATTRIBUTE_HEAD_OF_QUEUE    1
0707 #define SOP_TASK_ATTRIBUTE_ORDERED      2
0708 #define SOP_TASK_ATTRIBUTE_ACA          4
0709 
0710 #define SOP_TMF_COMPLETE        0x0
0711 #define SOP_TMF_REJECTED        0x4
0712 #define SOP_TMF_FUNCTION_SUCCEEDED  0x8
0713 #define SOP_RC_INCORRECT_LOGICAL_UNIT   0x9
0714 
0715 /* additional CDB bytes usage field codes */
0716 #define SOP_ADDITIONAL_CDB_BYTES_0  0   /* 16-byte CDB */
0717 #define SOP_ADDITIONAL_CDB_BYTES_4  1   /* 20-byte CDB */
0718 #define SOP_ADDITIONAL_CDB_BYTES_8  2   /* 24-byte CDB */
0719 #define SOP_ADDITIONAL_CDB_BYTES_12 3   /* 28-byte CDB */
0720 #define SOP_ADDITIONAL_CDB_BYTES_16 4   /* 32-byte CDB */
0721 
0722 /*
0723  * The purpose of this structure is to obtain proper alignment of objects in
0724  * an admin queue pair.
0725  */
0726 struct pqi_admin_queues_aligned {
0727     __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
0728         u8  iq_element_array[PQI_ADMIN_IQ_ELEMENT_LENGTH]
0729                     [PQI_ADMIN_IQ_NUM_ELEMENTS];
0730     __aligned(PQI_QUEUE_ELEMENT_ARRAY_ALIGNMENT)
0731         u8  oq_element_array[PQI_ADMIN_OQ_ELEMENT_LENGTH]
0732                     [PQI_ADMIN_OQ_NUM_ELEMENTS];
0733     __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t iq_ci;
0734     __aligned(PQI_ADMIN_INDEX_ALIGNMENT) pqi_index_t oq_pi;
0735 };
0736 
0737 struct pqi_admin_queues {
0738     void        *iq_element_array;
0739     void        *oq_element_array;
0740     pqi_index_t __iomem *iq_ci;
0741     pqi_index_t __iomem *oq_pi;
0742     dma_addr_t  iq_element_array_bus_addr;
0743     dma_addr_t  oq_element_array_bus_addr;
0744     dma_addr_t  iq_ci_bus_addr;
0745     dma_addr_t  oq_pi_bus_addr;
0746     __le32 __iomem  *iq_pi;
0747     pqi_index_t iq_pi_copy;
0748     __le32 __iomem  *oq_ci;
0749     pqi_index_t oq_ci_copy;
0750     struct task_struct *task;
0751     u16     int_msg_num;
0752 };
0753 
0754 struct pqi_queue_group {
0755     struct pqi_ctrl_info *ctrl_info;    /* backpointer */
0756     u16     iq_id[2];
0757     u16     oq_id;
0758     u16     int_msg_num;
0759     void        *iq_element_array[2];
0760     void        *oq_element_array;
0761     dma_addr_t  iq_element_array_bus_addr[2];
0762     dma_addr_t  oq_element_array_bus_addr;
0763     __le32 __iomem  *iq_pi[2];
0764     pqi_index_t iq_pi_copy[2];
0765     pqi_index_t __iomem *iq_ci[2];
0766     pqi_index_t __iomem *oq_pi;
0767     dma_addr_t  iq_ci_bus_addr[2];
0768     dma_addr_t  oq_pi_bus_addr;
0769     __le32 __iomem  *oq_ci;
0770     pqi_index_t oq_ci_copy;
0771     spinlock_t  submit_lock[2]; /* protect submission queue */
0772     struct list_head request_list[2];
0773 };
0774 
0775 struct pqi_event_queue {
0776     u16     oq_id;
0777     u16     int_msg_num;
0778     void        *oq_element_array;
0779     pqi_index_t __iomem *oq_pi;
0780     dma_addr_t  oq_element_array_bus_addr;
0781     dma_addr_t  oq_pi_bus_addr;
0782     __le32 __iomem  *oq_ci;
0783     pqi_index_t oq_ci_copy;
0784 };
0785 
0786 #define PQI_DEFAULT_QUEUE_GROUP     0
0787 #define PQI_MAX_QUEUE_GROUPS        PQI_MAX_MSIX_VECTORS
0788 
0789 struct pqi_encryption_info {
0790     u16 data_encryption_key_index;
0791     u32 encrypt_tweak_lower;
0792     u32 encrypt_tweak_upper;
0793 };
0794 
0795 #pragma pack(1)
0796 
0797 #define PQI_CONFIG_TABLE_SIGNATURE  "CFGTABLE"
0798 #define PQI_CONFIG_TABLE_MAX_LENGTH ((u16)~0)
0799 
0800 /* configuration table section IDs */
0801 #define PQI_CONFIG_TABLE_ALL_SECTIONS           (-1)
0802 #define PQI_CONFIG_TABLE_SECTION_GENERAL_INFO       0
0803 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_FEATURES  1
0804 #define PQI_CONFIG_TABLE_SECTION_FIRMWARE_ERRATA    2
0805 #define PQI_CONFIG_TABLE_SECTION_DEBUG          3
0806 #define PQI_CONFIG_TABLE_SECTION_HEARTBEAT      4
0807 #define PQI_CONFIG_TABLE_SECTION_SOFT_RESET     5
0808 
0809 struct pqi_config_table {
0810     u8  signature[8];       /* "CFGTABLE" */
0811     __le32  first_section_offset;   /* offset in bytes from the base */
0812                     /* address of this table to the */
0813                     /* first section */
0814 };
0815 
0816 struct pqi_config_table_section_header {
0817     __le16  section_id;     /* as defined by the */
0818                     /* PQI_CONFIG_TABLE_SECTION_* */
0819                     /* manifest constants above */
0820     __le16  next_section_offset;    /* offset in bytes from base */
0821                     /* address of the table of the */
0822                     /* next section or 0 if last entry */
0823 };
0824 
0825 struct pqi_config_table_general_info {
0826     struct pqi_config_table_section_header header;
0827     __le32  section_length;     /* size of this section in bytes */
0828                     /* including the section header */
0829     __le32  max_outstanding_requests;   /* max. outstanding */
0830                         /* commands supported by */
0831                         /* the controller */
0832     __le32  max_sg_size;        /* max. transfer size of a single */
0833                     /* command */
0834     __le32  max_sg_per_request; /* max. number of scatter-gather */
0835                     /* entries supported in a single */
0836                     /* command */
0837 };
0838 
0839 struct pqi_config_table_firmware_features {
0840     struct pqi_config_table_section_header header;
0841     __le16  num_elements;
0842     u8  features_supported[];
0843 /*  u8  features_requested_by_host[]; */
0844 /*  u8  features_enabled[]; */
0845 /* The 2 fields below are only valid if the MAX_KNOWN_FEATURE bit is set. */
0846 /*  __le16  firmware_max_known_feature; */
0847 /*  __le16  host_max_known_feature; */
0848 };
0849 
0850 #define PQI_FIRMWARE_FEATURE_OFA                0
0851 #define PQI_FIRMWARE_FEATURE_SMP                1
0852 #define PQI_FIRMWARE_FEATURE_MAX_KNOWN_FEATURE          2
0853 #define PQI_FIRMWARE_FEATURE_RAID_0_READ_BYPASS         3
0854 #define PQI_FIRMWARE_FEATURE_RAID_1_READ_BYPASS         4
0855 #define PQI_FIRMWARE_FEATURE_RAID_5_READ_BYPASS         5
0856 #define PQI_FIRMWARE_FEATURE_RAID_6_READ_BYPASS         6
0857 #define PQI_FIRMWARE_FEATURE_RAID_0_WRITE_BYPASS        7
0858 #define PQI_FIRMWARE_FEATURE_RAID_1_WRITE_BYPASS        8
0859 #define PQI_FIRMWARE_FEATURE_RAID_5_WRITE_BYPASS        9
0860 #define PQI_FIRMWARE_FEATURE_RAID_6_WRITE_BYPASS        10
0861 #define PQI_FIRMWARE_FEATURE_SOFT_RESET_HANDSHAKE       11
0862 #define PQI_FIRMWARE_FEATURE_UNIQUE_SATA_WWN            12
0863 #define PQI_FIRMWARE_FEATURE_RAID_IU_TIMEOUT            13
0864 #define PQI_FIRMWARE_FEATURE_TMF_IU_TIMEOUT         14
0865 #define PQI_FIRMWARE_FEATURE_RAID_BYPASS_ON_ENCRYPTED_NVME  15
0866 #define PQI_FIRMWARE_FEATURE_UNIQUE_WWID_IN_REPORT_PHYS_LUN 16
0867 #define PQI_FIRMWARE_FEATURE_FW_TRIAGE              17
0868 #define PQI_FIRMWARE_FEATURE_RPL_EXTENDED_FORMAT_4_5        18
0869 #define PQI_FIRMWARE_FEATURE_MULTI_LUN_DEVICE_SUPPORT           21
0870 #define PQI_FIRMWARE_FEATURE_MAXIMUM                            21
0871 
0872 struct pqi_config_table_debug {
0873     struct pqi_config_table_section_header header;
0874     __le32  scratchpad;
0875 };
0876 
0877 struct pqi_config_table_heartbeat {
0878     struct pqi_config_table_section_header header;
0879     __le32  heartbeat_counter;
0880 };
0881 
0882 struct pqi_config_table_soft_reset {
0883     struct pqi_config_table_section_header header;
0884     u8 soft_reset_status;
0885 };
0886 
0887 #define PQI_SOFT_RESET_INITIATE     0x1
0888 #define PQI_SOFT_RESET_ABORT        0x2
0889 
0890 enum pqi_soft_reset_status {
0891     RESET_INITIATE_FIRMWARE,
0892     RESET_INITIATE_DRIVER,
0893     RESET_ABORT,
0894     RESET_NORESPONSE,
0895     RESET_TIMEDOUT
0896 };
0897 
0898 union pqi_reset_register {
0899     struct {
0900         u32 reset_type : 3;
0901         u32 reserved : 2;
0902         u32 reset_action : 3;
0903         u32 hold_in_pd1 : 1;
0904         u32 reserved2 : 23;
0905     } bits;
0906     u32 all_bits;
0907 };
0908 
0909 #define PQI_RESET_ACTION_RESET      0x1
0910 
0911 #define PQI_RESET_TYPE_NO_RESET     0x0
0912 #define PQI_RESET_TYPE_SOFT_RESET   0x1
0913 #define PQI_RESET_TYPE_FIRM_RESET   0x2
0914 #define PQI_RESET_TYPE_HARD_RESET   0x3
0915 
0916 #define PQI_RESET_ACTION_COMPLETED  0x2
0917 
0918 #define PQI_RESET_POLL_INTERVAL_MSECS   100
0919 
0920 #define PQI_MAX_OUTSTANDING_REQUESTS        ((u32)~0)
0921 #define PQI_MAX_OUTSTANDING_REQUESTS_KDUMP  32
0922 #define PQI_MAX_TRANSFER_SIZE           (1024U * 1024U)
0923 #define PQI_MAX_TRANSFER_SIZE_KDUMP     (512 * 1024U)
0924 
0925 #define RAID_MAP_MAX_ENTRIES            1024
0926 #define RAID_MAP_MAX_DATA_DISKS_PER_ROW     128
0927 
0928 #define PQI_PHYSICAL_DEVICE_BUS     0
0929 #define PQI_RAID_VOLUME_BUS     1
0930 #define PQI_HBA_BUS         2
0931 #define PQI_EXTERNAL_RAID_VOLUME_BUS    3
0932 #define PQI_MAX_BUS         PQI_EXTERNAL_RAID_VOLUME_BUS
0933 #define PQI_VSEP_CISS_BTL       379
0934 
0935 struct report_lun_header {
0936     __be32  list_length;
0937     u8  flags;
0938     u8  reserved[3];
0939 };
0940 
0941 /* for flags field of struct report_lun_header */
0942 #define CISS_REPORT_LOG_FLAG_UNIQUE_LUN_ID  (1 << 0)
0943 #define CISS_REPORT_LOG_FLAG_QUEUE_DEPTH    (1 << 5)
0944 #define CISS_REPORT_LOG_FLAG_DRIVE_TYPE_MIX (1 << 6)
0945 
0946 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_2     0x2
0947 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_4     0x4
0948 #define CISS_REPORT_PHYS_FLAG_EXTENDED_FORMAT_MASK  0xf
0949 
0950 struct report_log_lun {
0951     u8  lunid[8];
0952     u8  volume_id[16];
0953 };
0954 
0955 struct report_log_lun_list {
0956     struct report_lun_header header;
0957     struct report_log_lun lun_entries[1];
0958 };
0959 
0960 struct report_phys_lun_8byte_wwid {
0961     u8  lunid[8];
0962     __be64  wwid;
0963     u8  device_type;
0964     u8  device_flags;
0965     u8  lun_count;  /* number of LUNs in a multi-LUN device */
0966     u8  redundant_paths;
0967     u32 aio_handle;
0968 };
0969 
0970 struct report_phys_lun_16byte_wwid {
0971     u8  lunid[8];
0972     u8  wwid[16];
0973     u8  device_type;
0974     u8  device_flags;
0975     u8  lun_count;  /* number of LUNs in a multi-LUN device */
0976     u8  redundant_paths;
0977     u32 aio_handle;
0978 };
0979 
0980 /* for device_flags field of struct report_phys_lun_extended_entry */
0981 #define CISS_REPORT_PHYS_DEV_FLAG_AIO_ENABLED   0x8
0982 
0983 struct report_phys_lun_8byte_wwid_list {
0984     struct report_lun_header header;
0985     struct report_phys_lun_8byte_wwid lun_entries[1];
0986 };
0987 
0988 struct report_phys_lun_16byte_wwid_list {
0989     struct report_lun_header header;
0990     struct report_phys_lun_16byte_wwid lun_entries[1];
0991 };
0992 
0993 struct raid_map_disk_data {
0994     u32 aio_handle;
0995     u8  xor_mult[2];
0996     u8  reserved[2];
0997 };
0998 
0999 /* for flags field of RAID map */
1000 #define RAID_MAP_ENCRYPTION_ENABLED 0x1
1001 
1002 struct raid_map {
1003     __le32  structure_size;     /* size of entire structure in bytes */
1004     __le32  volume_blk_size;    /* bytes / block in the volume */
1005     __le64  volume_blk_cnt;     /* logical blocks on the volume */
1006     u8  phys_blk_shift;     /* shift factor to convert between */
1007                     /* units of logical blocks and */
1008                     /* physical disk blocks */
1009     u8  parity_rotation_shift;  /* shift factor to convert between */
1010                     /* units of logical stripes and */
1011                     /* physical stripes */
1012     __le16  strip_size;     /* blocks used on each disk / stripe */
1013     __le64  disk_starting_blk;  /* first disk block used in volume */
1014     __le64  disk_blk_cnt;       /* disk blocks used by volume / disk */
1015     __le16  data_disks_per_row; /* data disk entries / row in the map */
1016     __le16  metadata_disks_per_row; /* mirror/parity disk entries / row */
1017                     /* in the map */
1018     __le16  row_cnt;        /* rows in each layout map */
1019     __le16  layout_map_count;   /* layout maps (1 map per */
1020                     /* mirror parity group) */
1021     __le16  flags;
1022     __le16  data_encryption_key_index;
1023     u8  reserved[16];
1024     struct raid_map_disk_data disk_data[RAID_MAP_MAX_ENTRIES];
1025 };
1026 
1027 #pragma pack()
1028 
1029 struct pqi_scsi_dev_raid_map_data {
1030     bool    is_write;
1031     u8  raid_level;
1032     u32 map_index;
1033     u64 first_block;
1034     u64 last_block;
1035     u32 data_length;
1036     u32 block_cnt;
1037     u32 blocks_per_row;
1038     u64 first_row;
1039     u64 last_row;
1040     u32 first_row_offset;
1041     u32 last_row_offset;
1042     u32 first_column;
1043     u32 last_column;
1044     u64 r5or6_first_row;
1045     u64 r5or6_last_row;
1046     u32 r5or6_first_row_offset;
1047     u32 r5or6_last_row_offset;
1048     u32 r5or6_first_column;
1049     u32 r5or6_last_column;
1050     u16 data_disks_per_row;
1051     u32 total_disks_per_row;
1052     u16 layout_map_count;
1053     u32 stripesize;
1054     u16 strip_size;
1055     u32 first_group;
1056     u32 last_group;
1057     u32 map_row;
1058     u32 aio_handle;
1059     u64 disk_block;
1060     u32 disk_block_cnt;
1061     u8  cdb[16];
1062     u8  cdb_length;
1063 
1064     /* RAID 1 specific */
1065 #define NUM_RAID1_MAP_ENTRIES   3
1066     u32 num_it_nexus_entries;
1067     u32 it_nexus[NUM_RAID1_MAP_ENTRIES];
1068 
1069     /* RAID 5 / RAID 6 specific */
1070     u32 p_parity_it_nexus;  /* aio_handle */
1071     u32 q_parity_it_nexus;  /* aio_handle */
1072     u8  xor_mult;
1073     u64 row;
1074     u64 stripe_lba;
1075     u32 p_index;
1076     u32 q_index;
1077 };
1078 
1079 #define RAID_CTLR_LUNID     "\0\0\0\0\0\0\0\0"
1080 
1081 #define NUM_STREAMS_PER_LUN 8
1082 
1083 struct pqi_stream_data {
1084     u64 next_lba;
1085     u32 last_accessed;
1086 };
1087 
1088 #define PQI_MAX_LUNS_PER_DEVICE         256
1089 
1090 struct pqi_scsi_dev {
1091     int devtype;        /* as reported by INQUIRY command */
1092     u8  device_type;        /* as reported by */
1093                     /* BMIC_IDENTIFY_PHYSICAL_DEVICE */
1094                     /* only valid for devtype = TYPE_DISK */
1095     int bus;
1096     int target;
1097     int lun;
1098     u8  scsi3addr[8];
1099     u8  wwid[16];
1100     u8  volume_id[16];
1101     u8  is_physical_device : 1;
1102     u8  is_external_raid_device : 1;
1103     u8  is_expander_smp_device : 1;
1104     u8  target_lun_valid : 1;
1105     u8  device_gone : 1;
1106     u8  new_device : 1;
1107     u8  keep_device : 1;
1108     u8  volume_offline : 1;
1109     u8  rescan : 1;
1110     u8  ignore_device : 1;
1111     bool    aio_enabled;        /* only valid for physical disks */
1112     bool    in_remove;
1113     bool    device_offline;
1114     u8  vendor[8];      /* bytes 8-15 of inquiry data */
1115     u8  model[16];      /* bytes 16-31 of inquiry data */
1116     u64 sas_address;
1117     u8  raid_level;
1118     u16 queue_depth;        /* max. queue_depth for this device */
1119     u16 advertised_queue_depth;
1120     u32 aio_handle;
1121     u8  volume_status;
1122     u8  active_path_index;
1123     u8  path_map;
1124     u8  bay;
1125     u8  box_index;
1126     u8  phys_box_on_bus;
1127     u8  phy_connected_dev_type;
1128     u8  box[8];
1129     u16 phys_connector[8];
1130     u8  phy_id;
1131     u8  ncq_prio_enable;
1132     u8  ncq_prio_support;
1133     u8  multi_lun_device_lun_count;
1134     bool    raid_bypass_configured; /* RAID bypass configured */
1135     bool    raid_bypass_enabled;    /* RAID bypass enabled */
1136     u32 next_bypass_group[RAID_MAP_MAX_DATA_DISKS_PER_ROW];
1137     struct raid_map *raid_map;  /* RAID bypass map */
1138     u32 max_transfer_encrypted;
1139 
1140     struct pqi_sas_port *sas_port;
1141     struct scsi_device *sdev;
1142 
1143     struct list_head scsi_device_list_entry;
1144     struct list_head new_device_list_entry;
1145     struct list_head add_list_entry;
1146     struct list_head delete_list_entry;
1147 
1148     struct pqi_stream_data stream_data[NUM_STREAMS_PER_LUN];
1149     atomic_t scsi_cmds_outstanding[PQI_MAX_LUNS_PER_DEVICE];
1150     atomic_t raid_bypass_cnt;
1151 };
1152 
1153 /* VPD inquiry pages */
1154 #define CISS_VPD_LV_DEVICE_GEOMETRY 0xc1    /* vendor-specific page */
1155 #define CISS_VPD_LV_BYPASS_STATUS   0xc2    /* vendor-specific page */
1156 #define CISS_VPD_LV_STATUS      0xc3    /* vendor-specific page */
1157 
1158 #define VPD_PAGE    (1 << 8)
1159 
1160 #pragma pack(1)
1161 
1162 /* structure for CISS_VPD_LV_STATUS */
1163 struct ciss_vpd_logical_volume_status {
1164     u8  peripheral_info;
1165     u8  page_code;
1166     u8  reserved;
1167     u8  page_length;
1168     u8  volume_status;
1169     u8  reserved2[3];
1170     __be32  flags;
1171 };
1172 
1173 #pragma pack()
1174 
1175 /* constants for volume_status field of ciss_vpd_logical_volume_status */
1176 #define CISS_LV_OK                  0
1177 #define CISS_LV_FAILED                  1
1178 #define CISS_LV_NOT_CONFIGURED              2
1179 #define CISS_LV_DEGRADED                3
1180 #define CISS_LV_READY_FOR_RECOVERY          4
1181 #define CISS_LV_UNDERGOING_RECOVERY         5
1182 #define CISS_LV_WRONG_PHYSICAL_DRIVE_REPLACED       6
1183 #define CISS_LV_PHYSICAL_DRIVE_CONNECTION_PROBLEM   7
1184 #define CISS_LV_HARDWARE_OVERHEATING            8
1185 #define CISS_LV_HARDWARE_HAS_OVERHEATED         9
1186 #define CISS_LV_UNDERGOING_EXPANSION            10
1187 #define CISS_LV_NOT_AVAILABLE               11
1188 #define CISS_LV_QUEUED_FOR_EXPANSION            12
1189 #define CISS_LV_DISABLED_SCSI_ID_CONFLICT       13
1190 #define CISS_LV_EJECTED                 14
1191 #define CISS_LV_UNDERGOING_ERASE            15
1192 /* state 16 not used */
1193 #define CISS_LV_READY_FOR_PREDICTIVE_SPARE_REBUILD  17
1194 #define CISS_LV_UNDERGOING_RPI              18
1195 #define CISS_LV_PENDING_RPI             19
1196 #define CISS_LV_ENCRYPTED_NO_KEY            20
1197 /* state 21 not used */
1198 #define CISS_LV_UNDERGOING_ENCRYPTION           22
1199 #define CISS_LV_UNDERGOING_ENCRYPTION_REKEYING      23
1200 #define CISS_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER   24
1201 #define CISS_LV_PENDING_ENCRYPTION          25
1202 #define CISS_LV_PENDING_ENCRYPTION_REKEYING     26
1203 #define CISS_LV_NOT_SUPPORTED               27
1204 #define CISS_LV_STATUS_UNAVAILABLE          255
1205 
1206 /* constants for flags field of ciss_vpd_logical_volume_status */
1207 #define CISS_LV_FLAGS_NO_HOST_IO    0x1 /* volume not available for */
1208                         /* host I/O */
1209 
1210 /* for SAS hosts and SAS expanders */
1211 struct pqi_sas_node {
1212     struct device *parent_dev;
1213     struct list_head port_list_head;
1214 };
1215 
1216 struct pqi_sas_port {
1217     struct list_head port_list_entry;
1218     u64 sas_address;
1219     struct pqi_scsi_dev *device;
1220     struct sas_port *port;
1221     int next_phy_index;
1222     struct list_head phy_list_head;
1223     struct pqi_sas_node *parent_node;
1224     struct sas_rphy *rphy;
1225 };
1226 
1227 struct pqi_sas_phy {
1228     struct list_head phy_list_entry;
1229     struct sas_phy *phy;
1230     struct pqi_sas_port *parent_port;
1231     bool    added_to_port;
1232 };
1233 
1234 struct pqi_io_request {
1235     atomic_t    refcount;
1236     u16     index;
1237     void (*io_complete_callback)(struct pqi_io_request *io_request,
1238         void *context);
1239     void        *context;
1240     u8      raid_bypass : 1;
1241     int     status;
1242     struct pqi_queue_group *queue_group;
1243     struct scsi_cmnd *scmd;
1244     void        *error_info;
1245     struct pqi_sg_descriptor *sg_chain_buffer;
1246     dma_addr_t  sg_chain_buffer_dma_handle;
1247     void        *iu;
1248     struct list_head request_list_entry;
1249 };
1250 
1251 #define PQI_NUM_SUPPORTED_EVENTS    7
1252 
1253 struct pqi_event {
1254     bool    pending;
1255     u8  event_type;
1256     u16 event_id;
1257     u32 additional_event_id;
1258 };
1259 
1260 #define PQI_RESERVED_IO_SLOTS_LUN_RESET         1
1261 #define PQI_RESERVED_IO_SLOTS_EVENT_ACK         PQI_NUM_SUPPORTED_EVENTS
1262 #define PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS  3
1263 #define PQI_RESERVED_IO_SLOTS               \
1264     (PQI_RESERVED_IO_SLOTS_LUN_RESET + PQI_RESERVED_IO_SLOTS_EVENT_ACK + \
1265     PQI_RESERVED_IO_SLOTS_SYNCHRONOUS_REQUESTS)
1266 
1267 #define PQI_CTRL_PRODUCT_ID_GEN1    0
1268 #define PQI_CTRL_PRODUCT_ID_GEN2    7
1269 #define PQI_CTRL_PRODUCT_REVISION_A 0
1270 #define PQI_CTRL_PRODUCT_REVISION_B 1
1271 
1272 enum pqi_ctrl_removal_state {
1273     PQI_CTRL_PRESENT = 0,
1274     PQI_CTRL_GRACEFUL_REMOVAL,
1275     PQI_CTRL_SURPRISE_REMOVAL
1276 };
1277 
1278 struct pqi_ctrl_info {
1279     unsigned int    ctrl_id;
1280     struct pci_dev  *pci_dev;
1281     char        firmware_version[32];
1282     char        serial_number[17];
1283     char        model[17];
1284     char        vendor[9];
1285     u8      product_id;
1286     u8      product_revision;
1287     void __iomem    *iomem_base;
1288     struct pqi_ctrl_registers __iomem *registers;
1289     struct pqi_device_registers __iomem *pqi_registers;
1290     u32     max_sg_entries;
1291     u32     config_table_offset;
1292     u32     config_table_length;
1293     u16     max_inbound_queues;
1294     u16     max_elements_per_iq;
1295     u16     max_iq_element_length;
1296     u16     max_outbound_queues;
1297     u16     max_elements_per_oq;
1298     u16     max_oq_element_length;
1299     u32     max_transfer_size;
1300     u32     max_outstanding_requests;
1301     u32     max_io_slots;
1302     unsigned int    scsi_ml_can_queue;
1303     unsigned short  sg_tablesize;
1304     unsigned int    max_sectors;
1305     u32     error_buffer_length;
1306     void        *error_buffer;
1307     dma_addr_t  error_buffer_dma_handle;
1308     size_t      sg_chain_buffer_length;
1309     unsigned int    num_queue_groups;
1310     u16     max_hw_queue_index;
1311     u16     num_elements_per_iq;
1312     u16     num_elements_per_oq;
1313     u16     max_inbound_iu_length_per_firmware;
1314     u16     max_inbound_iu_length;
1315     unsigned int    max_sg_per_iu;
1316     unsigned int    max_sg_per_r56_iu;
1317     void        *admin_queue_memory_base;
1318     u32     admin_queue_memory_length;
1319     dma_addr_t  admin_queue_memory_base_dma_handle;
1320     void        *queue_memory_base;
1321     u32     queue_memory_length;
1322     dma_addr_t  queue_memory_base_dma_handle;
1323     struct pqi_admin_queues admin_queues;
1324     struct pqi_queue_group queue_groups[PQI_MAX_QUEUE_GROUPS];
1325     struct pqi_event_queue event_queue;
1326     enum pqi_irq_mode irq_mode;
1327     int     max_msix_vectors;
1328     int     num_msix_vectors_enabled;
1329     int     num_msix_vectors_initialized;
1330     int     event_irq;
1331     struct Scsi_Host *scsi_host;
1332 
1333     struct mutex    scan_mutex;
1334     struct mutex    lun_reset_mutex;
1335     bool        controller_online;
1336     bool        block_requests;
1337     bool        scan_blocked;
1338     u8      logical_volume_rescan_needed : 1;
1339     u8      inbound_spanning_supported : 1;
1340     u8      outbound_spanning_supported : 1;
1341     u8      pqi_mode_enabled : 1;
1342     u8      pqi_reset_quiesce_supported : 1;
1343     u8      soft_reset_handshake_supported : 1;
1344     u8      raid_iu_timeout_supported : 1;
1345     u8      tmf_iu_timeout_supported : 1;
1346     u8      firmware_triage_supported : 1;
1347     u8      rpl_extended_format_4_5_supported : 1;
1348     u8      multi_lun_device_supported : 1;
1349     u8      enable_r1_writes : 1;
1350     u8      enable_r5_writes : 1;
1351     u8      enable_r6_writes : 1;
1352     u8      lv_drive_type_mix_valid : 1;
1353     u8      enable_stream_detection : 1;
1354     u8      disable_managed_interrupts : 1;
1355     u8      ciss_report_log_flags;
1356     u32     max_transfer_encrypted_sas_sata;
1357     u32     max_transfer_encrypted_nvme;
1358     u32     max_write_raid_5_6;
1359     u32     max_write_raid_1_10_2drive;
1360     u32     max_write_raid_1_10_3drive;
1361 
1362     struct list_head scsi_device_list;
1363     spinlock_t  scsi_device_list_lock;
1364 
1365     struct delayed_work rescan_work;
1366     struct delayed_work update_time_work;
1367 
1368     struct pqi_sas_node *sas_host;
1369     u64     sas_address;
1370 
1371     struct pqi_io_request *io_request_pool;
1372     u16     next_io_request_slot;
1373 
1374     struct pqi_event events[PQI_NUM_SUPPORTED_EVENTS];
1375     struct work_struct event_work;
1376 
1377     atomic_t    num_interrupts;
1378     int     previous_num_interrupts;
1379     u32     previous_heartbeat_count;
1380     __le32 __iomem  *heartbeat_counter;
1381     u8 __iomem  *soft_reset_status;
1382     struct timer_list heartbeat_timer;
1383     struct work_struct ctrl_offline_work;
1384 
1385     struct semaphore sync_request_sem;
1386     atomic_t    num_busy_threads;
1387     atomic_t    num_blocked_threads;
1388     wait_queue_head_t block_requests_wait;
1389 
1390     struct mutex    ofa_mutex;
1391     struct pqi_ofa_memory *pqi_ofa_mem_virt_addr;
1392     dma_addr_t  pqi_ofa_mem_dma_handle;
1393     void        **pqi_ofa_chunk_virt_addr;
1394     struct work_struct ofa_memory_alloc_work;
1395     struct work_struct ofa_quiesce_work;
1396     u32     ofa_bytes_requested;
1397     u16     ofa_cancel_reason;
1398     enum pqi_ctrl_removal_state ctrl_removal_state;
1399 };
1400 
1401 enum pqi_ctrl_mode {
1402     SIS_MODE = 0,
1403     PQI_MODE
1404 };
1405 
1406 /*
1407  * assume worst case: SATA queue depth of 31 minus 4 internal firmware commands
1408  */
1409 #define PQI_PHYSICAL_DISK_DEFAULT_MAX_QUEUE_DEPTH   27
1410 
1411 /* CISS commands */
1412 #define CISS_READ       0xc0
1413 #define CISS_REPORT_LOG     0xc2    /* Report Logical LUNs */
1414 #define CISS_REPORT_PHYS    0xc3    /* Report Physical LUNs */
1415 #define CISS_GET_RAID_MAP   0xc8
1416 
1417 /* BMIC commands */
1418 #define BMIC_IDENTIFY_CONTROLLER        0x11
1419 #define BMIC_IDENTIFY_PHYSICAL_DEVICE       0x15
1420 #define BMIC_READ               0x26
1421 #define BMIC_WRITE              0x27
1422 #define BMIC_SENSE_FEATURE          0x61
1423 #define BMIC_SENSE_CONTROLLER_PARAMETERS    0x64
1424 #define BMIC_SENSE_SUBSYSTEM_INFORMATION    0x66
1425 #define BMIC_CSMI_PASSTHRU          0x68
1426 #define BMIC_WRITE_HOST_WELLNESS        0xa5
1427 #define BMIC_FLUSH_CACHE            0xc2
1428 #define BMIC_SET_DIAG_OPTIONS           0xf4
1429 #define BMIC_SENSE_DIAG_OPTIONS         0xf5
1430 
1431 #define CSMI_CC_SAS_SMP_PASSTHRU        0x17
1432 
1433 #define SA_FLUSH_CACHE              0x1
1434 
1435 #define MASKED_DEVICE(lunid)            ((lunid)[3] & 0xc0)
1436 #define CISS_GET_LEVEL_2_BUS(lunid)     ((lunid)[7] & 0x3f)
1437 #define CISS_GET_LEVEL_2_TARGET(lunid)      ((lunid)[6])
1438 #define CISS_GET_DRIVE_NUMBER(lunid)        \
1439     (((CISS_GET_LEVEL_2_BUS((lunid)) - 1) << 8) + \
1440     CISS_GET_LEVEL_2_TARGET((lunid)))
1441 
1442 #define LV_GET_DRIVE_TYPE_MIX(lunid)        ((lunid)[6])
1443 
1444 #define LV_DRIVE_TYPE_MIX_UNKNOWN       0
1445 #define LV_DRIVE_TYPE_MIX_NO_RESTRICTION    1
1446 #define LV_DRIVE_TYPE_MIX_SAS_HDD_ONLY      2
1447 #define LV_DRIVE_TYPE_MIX_SATA_HDD_ONLY     3
1448 #define LV_DRIVE_TYPE_MIX_SAS_OR_SATA_SSD_ONLY  4
1449 #define LV_DRIVE_TYPE_MIX_SAS_SSD_ONLY      5
1450 #define LV_DRIVE_TYPE_MIX_SATA_SSD_ONLY     6
1451 #define LV_DRIVE_TYPE_MIX_SAS_ONLY      7
1452 #define LV_DRIVE_TYPE_MIX_SATA_ONLY     8
1453 #define LV_DRIVE_TYPE_MIX_NVME_ONLY     9
1454 
1455 #define NO_TIMEOUT      ((unsigned long) -1)
1456 
1457 #pragma pack(1)
1458 
1459 struct bmic_identify_controller {
1460     u8  configured_logical_drive_count;
1461     __le32  configuration_signature;
1462     u8  firmware_version_short[4];
1463     u8  reserved[145];
1464     __le16  extended_logical_unit_count;
1465     u8  reserved1[34];
1466     __le16  firmware_build_number;
1467     u8  reserved2[8];
1468     u8  vendor_id[8];
1469     u8  product_id[16];
1470     u8  reserved3[62];
1471     __le32  extra_controller_flags;
1472     u8  reserved4[2];
1473     u8  controller_mode;
1474     u8  spare_part_number[32];
1475     u8  firmware_version_long[32];
1476 };
1477 
1478 /* constants for extra_controller_flags field of bmic_identify_controller */
1479 #define BMIC_IDENTIFY_EXTRA_FLAGS_LONG_FW_VERSION_SUPPORTED 0x20000000
1480 
1481 struct bmic_sense_subsystem_info {
1482     u8  reserved[44];
1483     u8  ctrl_serial_number[16];
1484 };
1485 
1486 /* constants for device_type field */
1487 #define SA_DEVICE_TYPE_SATA     0x1
1488 #define SA_DEVICE_TYPE_SAS      0x2
1489 #define SA_DEVICE_TYPE_EXPANDER_SMP 0x5
1490 #define SA_DEVICE_TYPE_SES      0x6
1491 #define SA_DEVICE_TYPE_CONTROLLER   0x7
1492 #define SA_DEVICE_TYPE_NVME     0x9
1493 
1494 struct bmic_identify_physical_device {
1495     u8  scsi_bus;       /* SCSI Bus number on controller */
1496     u8  scsi_id;        /* SCSI ID on this bus */
1497     __le16  block_size;     /* sector size in bytes */
1498     __le32  total_blocks;       /* number for sectors on drive */
1499     __le32  reserved_blocks;    /* controller reserved (RIS) */
1500     u8  model[40];      /* Physical Drive Model */
1501     u8  serial_number[40];  /* Drive Serial Number */
1502     u8  firmware_revision[8];   /* drive firmware revision */
1503     u8  scsi_inquiry_bits;  /* inquiry byte 7 bits */
1504     u8  compaq_drive_stamp; /* 0 means drive not stamped */
1505     u8  last_failure_reason;
1506     u8  flags;
1507     u8  more_flags;
1508     u8  scsi_lun;       /* SCSI LUN for phys drive */
1509     u8  yet_more_flags;
1510     u8  even_more_flags;
1511     __le32  spi_speed_rules;
1512     u8  phys_connector[2];  /* connector number on controller */
1513     u8  phys_box_on_bus;    /* phys enclosure this drive resides */
1514     u8  phys_bay_in_box;    /* phys drv bay this drive resides */
1515     __le32  rpm;            /* drive rotational speed in RPM */
1516     u8  device_type;        /* type of drive */
1517     u8  sata_version;       /* only valid when device_type = */
1518                     /* SA_DEVICE_TYPE_SATA */
1519     __le64  big_total_block_count;
1520     __le64  ris_starting_lba;
1521     __le32  ris_size;
1522     u8  wwid[20];
1523     u8  controller_phy_map[32];
1524     __le16  phy_count;
1525     u8  phy_connected_dev_type[256];
1526     u8  phy_to_drive_bay_num[256];
1527     __le16  phy_to_attached_dev_index[256];
1528     u8  box_index;
1529     u8  reserved;
1530     __le16  extra_physical_drive_flags;
1531     u8  negotiated_link_rate[256];
1532     u8  phy_to_phy_map[256];
1533     u8  redundant_path_present_map;
1534     u8  redundant_path_failure_map;
1535     u8  active_path_number;
1536     __le16  alternate_paths_phys_connector[8];
1537     u8  alternate_paths_phys_box_on_port[8];
1538     u8  multi_lun_device_lun_count;
1539     u8  minimum_good_fw_revision[8];
1540     u8  unique_inquiry_bytes[20];
1541     u8  current_temperature_degrees;
1542     u8  temperature_threshold_degrees;
1543     u8  max_temperature_degrees;
1544     u8  logical_blocks_per_phys_block_exp;
1545     __le16  current_queue_depth_limit;
1546     u8  switch_name[10];
1547     __le16  switch_port;
1548     u8  alternate_paths_switch_name[40];
1549     u8  alternate_paths_switch_port[8];
1550     __le16  power_on_hours;
1551     __le16  percent_endurance_used;
1552     u8  drive_authentication;
1553     u8  smart_carrier_authentication;
1554     u8  smart_carrier_app_fw_version;
1555     u8  smart_carrier_bootloader_fw_version;
1556     u8  sanitize_flags;
1557     u8  encryption_key_flags;
1558     u8  encryption_key_name[64];
1559     __le32  misc_drive_flags;
1560     __le16  dek_index;
1561     __le16  hba_drive_encryption_flags;
1562     __le16  max_overwrite_time;
1563     __le16  max_block_erase_time;
1564     __le16  max_crypto_erase_time;
1565     u8  connector_info[5];
1566     u8  connector_name[8][8];
1567     u8  page_83_identifier[16];
1568     u8  maximum_link_rate[256];
1569     u8  negotiated_physical_link_rate[256];
1570     u8  box_connector_name[8];
1571     u8  padding_to_multiple_of_512[9];
1572 };
1573 
1574 #define BMIC_SENSE_FEATURE_IO_PAGE      0x8
1575 #define BMIC_SENSE_FEATURE_IO_PAGE_AIO_SUBPAGE  0x2
1576 
1577 struct bmic_sense_feature_buffer_header {
1578     u8  page_code;
1579     u8  subpage_code;
1580     __le16  buffer_length;
1581 };
1582 
1583 struct bmic_sense_feature_page_header {
1584     u8  page_code;
1585     u8  subpage_code;
1586     __le16  page_length;
1587 };
1588 
1589 struct bmic_sense_feature_io_page_aio_subpage {
1590     struct bmic_sense_feature_page_header header;
1591     u8  firmware_read_support;
1592     u8  driver_read_support;
1593     u8  firmware_write_support;
1594     u8  driver_write_support;
1595     __le16  max_transfer_encrypted_sas_sata;
1596     __le16  max_transfer_encrypted_nvme;
1597     __le16  max_write_raid_5_6;
1598     __le16  max_write_raid_1_10_2drive;
1599     __le16  max_write_raid_1_10_3drive;
1600 };
1601 
1602 struct bmic_smp_request {
1603     u8  frame_type;
1604     u8  function;
1605     u8  allocated_response_length;
1606     u8  request_length;
1607     u8  additional_request_bytes[1016];
1608 };
1609 
1610 struct  bmic_smp_response {
1611     u8  frame_type;
1612     u8  function;
1613     u8  function_result;
1614     u8  response_length;
1615     u8  additional_response_bytes[1016];
1616 };
1617 
1618 struct bmic_csmi_ioctl_header {
1619     __le32  header_length;
1620     u8  signature[8];
1621     __le32  timeout;
1622     __le32  control_code;
1623     __le32  return_code;
1624     __le32  length;
1625 };
1626 
1627 struct bmic_csmi_smp_passthru {
1628     u8  phy_identifier;
1629     u8  port_identifier;
1630     u8  connection_rate;
1631     u8  reserved;
1632     __be64  destination_sas_address;
1633     __le32  request_length;
1634     struct bmic_smp_request request;
1635     u8  connection_status;
1636     u8  reserved1[3];
1637     __le32  response_length;
1638     struct bmic_smp_response response;
1639 };
1640 
1641 struct bmic_csmi_smp_passthru_buffer {
1642     struct bmic_csmi_ioctl_header ioctl_header;
1643     struct bmic_csmi_smp_passthru parameters;
1644 };
1645 
1646 struct bmic_flush_cache {
1647     u8  disable_flag;
1648     u8  system_power_action;
1649     u8  ndu_flush;
1650     u8  shutdown_event;
1651     u8  reserved[28];
1652 };
1653 
1654 /* for shutdown_event member of struct bmic_flush_cache */
1655 enum bmic_flush_cache_shutdown_event {
1656     NONE_CACHE_FLUSH_ONLY = 0,
1657     SHUTDOWN = 1,
1658     HIBERNATE = 2,
1659     SUSPEND = 3,
1660     RESTART = 4
1661 };
1662 
1663 struct bmic_diag_options {
1664     __le32 options;
1665 };
1666 
1667 #pragma pack()
1668 
1669 static inline struct pqi_ctrl_info *shost_to_hba(struct Scsi_Host *shost)
1670 {
1671     void *hostdata = shost_priv(shost);
1672 
1673     return *((struct pqi_ctrl_info **)hostdata);
1674 }
1675 
1676 void pqi_sas_smp_handler(struct bsg_job *job, struct Scsi_Host *shost,
1677     struct sas_rphy *rphy);
1678 
1679 int pqi_add_sas_host(struct Scsi_Host *shost, struct pqi_ctrl_info *ctrl_info);
1680 void pqi_delete_sas_host(struct pqi_ctrl_info *ctrl_info);
1681 int pqi_add_sas_device(struct pqi_sas_node *pqi_sas_node,
1682     struct pqi_scsi_dev *device);
1683 void pqi_remove_sas_device(struct pqi_scsi_dev *device);
1684 struct pqi_scsi_dev *pqi_find_device_by_sas_rphy(
1685     struct pqi_ctrl_info *ctrl_info, struct sas_rphy *rphy);
1686 void pqi_prep_for_scsi_done(struct scsi_cmnd *scmd);
1687 int pqi_csmi_smp_passthru(struct pqi_ctrl_info *ctrl_info,
1688     struct bmic_csmi_smp_passthru_buffer *buffer, size_t buffer_length,
1689     struct pqi_raid_error_info *error_info);
1690 
1691 extern struct sas_function_template pqi_sas_transport_functions;
1692 
1693 #endif /* _SMARTPQI_H */
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