Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* qlogicpti.h: Performance Technologies QlogicISP sbus card defines.
0003  *
0004  * Copyright (C) 1996 David S. Miller (davem@caipfs.rutgers.edu)
0005  */
0006 
0007 #ifndef _QLOGICPTI_H
0008 #define _QLOGICPTI_H
0009 
0010 /* Qlogic/SBUS controller registers. */
0011 #define SBUS_CFG1   0x006UL
0012 #define SBUS_CTRL   0x008UL
0013 #define SBUS_STAT   0x00aUL
0014 #define SBUS_SEMAPHORE  0x00cUL
0015 #define CMD_DMA_CTRL    0x022UL
0016 #define DATA_DMA_CTRL   0x042UL
0017 #define MBOX0       0x080UL
0018 #define MBOX1       0x082UL
0019 #define MBOX2       0x084UL
0020 #define MBOX3       0x086UL
0021 #define MBOX4       0x088UL
0022 #define MBOX5       0x08aUL
0023 #define CPU_CMD     0x214UL
0024 #define CPU_ORIDE   0x224UL
0025 #define CPU_PCTRL   0x272UL
0026 #define CPU_PDIFF   0x276UL
0027 #define RISC_PSR    0x420UL
0028 #define RISC_MTREG  0x42EUL
0029 #define HCCTRL      0x440UL
0030 
0031 /* SCSI parameters for this driver. */
0032 #define MAX_TARGETS 16
0033 #define MAX_LUNS    8
0034 
0035 /* With the qlogic interface, every queue slot can hold a SCSI
0036  * command with up to 4 scatter/gather entries.  If we need more
0037  * than 4 entries, continuation entries can be used that hold
0038  * another 7 entries each.  Unlike for other drivers, this means
0039  * that the maximum number of scatter/gather entries we can
0040  * support at any given time is a function of the number of queue
0041  * slots available.  That is, host->can_queue and host->sg_tablesize
0042  * are dynamic and _not_ independent.  This all works fine because
0043  * requests are queued serially and the scatter/gather limit is
0044  * determined for each queue request anew.
0045  */
0046 #define QLOGICPTI_REQ_QUEUE_LEN 255 /* must be power of two - 1 */
0047 #define QLOGICPTI_MAX_SG(ql)    (4 + (((ql) > 0) ? 7*((ql) - 1) : 0))
0048 
0049 /* mailbox command complete status codes */
0050 #define MBOX_COMMAND_COMPLETE       0x4000
0051 #define INVALID_COMMAND         0x4001
0052 #define HOST_INTERFACE_ERROR        0x4002
0053 #define TEST_FAILED         0x4003
0054 #define COMMAND_ERROR           0x4005
0055 #define COMMAND_PARAM_ERROR     0x4006
0056 
0057 /* async event status codes */
0058 #define ASYNC_SCSI_BUS_RESET        0x8001
0059 #define SYSTEM_ERROR            0x8002
0060 #define REQUEST_TRANSFER_ERROR      0x8003
0061 #define RESPONSE_TRANSFER_ERROR     0x8004
0062 #define REQUEST_QUEUE_WAKEUP        0x8005
0063 #define EXECUTION_TIMEOUT_RESET     0x8006
0064 
0065 /* Am I fucking pedantic or what? */
0066 struct Entry_header {
0067 #ifdef __BIG_ENDIAN
0068     u8  entry_cnt;
0069     u8  entry_type;
0070     u8  flags;
0071     u8  sys_def_1;
0072 #else /* __LITTLE_ENDIAN */
0073     u8  entry_type;
0074     u8  entry_cnt;
0075     u8  sys_def_1;
0076     u8  flags;
0077 #endif
0078 };
0079 
0080 /* entry header type commands */
0081 #define ENTRY_COMMAND       1
0082 #define ENTRY_CONTINUATION  2
0083 #define ENTRY_STATUS        3
0084 #define ENTRY_MARKER        4
0085 #define ENTRY_EXTENDED_COMMAND  5
0086 
0087 /* entry header flag definitions */
0088 #define EFLAG_CONTINUATION  1
0089 #define EFLAG_BUSY      2
0090 #define EFLAG_BAD_HEADER    4
0091 #define EFLAG_BAD_PAYLOAD   8
0092 
0093 struct dataseg {
0094     u32 d_base;
0095     u32 d_count;
0096 };
0097 
0098 struct Command_Entry {
0099     struct Entry_header hdr;
0100     u32         handle;
0101 #ifdef __BIG_ENDIAN
0102     u8          target_id;
0103     u8          target_lun;
0104 #else /* __LITTLE_ENDIAN */
0105     u8          target_lun;
0106     u8          target_id;
0107 #endif
0108     u16         cdb_length;
0109     u16         control_flags;
0110     u16         rsvd;
0111     u16         time_out;
0112     u16         segment_cnt;
0113     u8          cdb[12];
0114     struct dataseg      dataseg[4];
0115 };
0116 
0117 /* command entry control flag definitions */
0118 #define CFLAG_NODISC        0x01
0119 #define CFLAG_HEAD_TAG      0x02
0120 #define CFLAG_ORDERED_TAG   0x04
0121 #define CFLAG_SIMPLE_TAG    0x08
0122 #define CFLAG_TAR_RTN       0x10
0123 #define CFLAG_READ      0x20
0124 #define CFLAG_WRITE     0x40
0125 
0126 struct Ext_Command_Entry {
0127     struct Entry_header hdr;
0128     u32         handle;
0129 #ifdef __BIG_ENDIAN
0130     u8          target_id;
0131     u8          target_lun;
0132 #else /* __LITTLE_ENDIAN */
0133     u8          target_lun;
0134     u8          target_id;
0135 #endif
0136     u16         cdb_length;
0137     u16         control_flags;
0138     u16         rsvd;
0139     u16         time_out;
0140     u16         segment_cnt;
0141     u8          cdb[44];
0142 };
0143 
0144 struct Continuation_Entry {
0145     struct Entry_header hdr;
0146     u32         reserved;
0147     struct dataseg      dataseg[7];
0148 };
0149 
0150 struct Marker_Entry {
0151     struct Entry_header hdr;
0152     u32         reserved;
0153 #ifdef __BIG_ENDIAN
0154     u8          target_id;
0155     u8          target_lun;
0156 #else /* __LITTLE_ENDIAN */
0157     u8          target_lun;
0158     u8          target_id;
0159 #endif
0160 #ifdef __BIG_ENDIAN
0161     u8          rsvd;
0162     u8          modifier;
0163 #else /* __LITTLE_ENDIAN */
0164     u8          modifier;
0165     u8          rsvd;
0166 #endif
0167     u8          rsvds[52];
0168 };
0169 
0170 /* marker entry modifier definitions */
0171 #define SYNC_DEVICE 0
0172 #define SYNC_TARGET 1
0173 #define SYNC_ALL    2
0174 
0175 struct Status_Entry {
0176     struct Entry_header hdr;
0177     u32         handle;
0178     u16         scsi_status;
0179     u16         completion_status;
0180     u16         state_flags;
0181     u16         status_flags;
0182     u16         time;
0183     u16         req_sense_len;
0184     u32         residual;
0185     u8          rsvd[8];
0186     u8          req_sense_data[32];
0187 };
0188 
0189 /* status entry completion status definitions */
0190 #define CS_COMPLETE         0x0000
0191 #define CS_INCOMPLETE           0x0001
0192 #define CS_DMA_ERROR            0x0002
0193 #define CS_TRANSPORT_ERROR      0x0003
0194 #define CS_RESET_OCCURRED       0x0004
0195 #define CS_ABORTED          0x0005
0196 #define CS_TIMEOUT          0x0006
0197 #define CS_DATA_OVERRUN         0x0007
0198 #define CS_COMMAND_OVERRUN      0x0008
0199 #define CS_STATUS_OVERRUN       0x0009
0200 #define CS_BAD_MESSAGE          0x000a
0201 #define CS_NO_MESSAGE_OUT       0x000b
0202 #define CS_EXT_ID_FAILED        0x000c
0203 #define CS_IDE_MSG_FAILED       0x000d
0204 #define CS_ABORT_MSG_FAILED     0x000e
0205 #define CS_REJECT_MSG_FAILED        0x000f
0206 #define CS_NOP_MSG_FAILED       0x0010
0207 #define CS_PARITY_ERROR_MSG_FAILED  0x0011
0208 #define CS_DEVICE_RESET_MSG_FAILED  0x0012
0209 #define CS_ID_MSG_FAILED        0x0013
0210 #define CS_UNEXP_BUS_FREE       0x0014
0211 #define CS_DATA_UNDERRUN        0x0015
0212 #define CS_BUS_RESET            0x001c
0213 
0214 /* status entry state flag definitions */
0215 #define SF_GOT_BUS          0x0100
0216 #define SF_GOT_TARGET           0x0200
0217 #define SF_SENT_CDB         0x0400
0218 #define SF_TRANSFERRED_DATA     0x0800
0219 #define SF_GOT_STATUS           0x1000
0220 #define SF_GOT_SENSE            0x2000
0221 
0222 /* status entry status flag definitions */
0223 #define STF_DISCONNECT          0x0001
0224 #define STF_SYNCHRONOUS         0x0002
0225 #define STF_PARITY_ERROR        0x0004
0226 #define STF_BUS_RESET           0x0008
0227 #define STF_DEVICE_RESET        0x0010
0228 #define STF_ABORTED         0x0020
0229 #define STF_TIMEOUT         0x0040
0230 #define STF_NEGOTIATION         0x0080
0231 
0232 /* mailbox commands */
0233 #define MBOX_NO_OP          0x0000
0234 #define MBOX_LOAD_RAM           0x0001
0235 #define MBOX_EXEC_FIRMWARE      0x0002
0236 #define MBOX_DUMP_RAM           0x0003
0237 #define MBOX_WRITE_RAM_WORD     0x0004
0238 #define MBOX_READ_RAM_WORD      0x0005
0239 #define MBOX_MAILBOX_REG_TEST       0x0006
0240 #define MBOX_VERIFY_CHECKSUM        0x0007
0241 #define MBOX_ABOUT_FIRMWARE     0x0008
0242 #define MBOX_CHECK_FIRMWARE     0x000e
0243 #define MBOX_INIT_REQ_QUEUE     0x0010
0244 #define MBOX_INIT_RES_QUEUE     0x0011
0245 #define MBOX_EXECUTE_IOCB       0x0012
0246 #define MBOX_WAKE_UP            0x0013
0247 #define MBOX_STOP_FIRMWARE      0x0014
0248 #define MBOX_ABORT          0x0015
0249 #define MBOX_ABORT_DEVICE       0x0016
0250 #define MBOX_ABORT_TARGET       0x0017
0251 #define MBOX_BUS_RESET          0x0018
0252 #define MBOX_STOP_QUEUE         0x0019
0253 #define MBOX_START_QUEUE        0x001a
0254 #define MBOX_SINGLE_STEP_QUEUE      0x001b
0255 #define MBOX_ABORT_QUEUE        0x001c
0256 #define MBOX_GET_DEV_QUEUE_STATUS   0x001d
0257 #define MBOX_GET_FIRMWARE_STATUS    0x001f
0258 #define MBOX_GET_INIT_SCSI_ID       0x0020
0259 #define MBOX_GET_SELECT_TIMEOUT     0x0021
0260 #define MBOX_GET_RETRY_COUNT        0x0022
0261 #define MBOX_GET_TAG_AGE_LIMIT      0x0023
0262 #define MBOX_GET_CLOCK_RATE     0x0024
0263 #define MBOX_GET_ACT_NEG_STATE      0x0025
0264 #define MBOX_GET_ASYNC_DATA_SETUP_TIME  0x0026
0265 #define MBOX_GET_SBUS_PARAMS        0x0027
0266 #define MBOX_GET_TARGET_PARAMS      0x0028
0267 #define MBOX_GET_DEV_QUEUE_PARAMS   0x0029
0268 #define MBOX_SET_INIT_SCSI_ID       0x0030
0269 #define MBOX_SET_SELECT_TIMEOUT     0x0031
0270 #define MBOX_SET_RETRY_COUNT        0x0032
0271 #define MBOX_SET_TAG_AGE_LIMIT      0x0033
0272 #define MBOX_SET_CLOCK_RATE     0x0034
0273 #define MBOX_SET_ACTIVE_NEG_STATE   0x0035
0274 #define MBOX_SET_ASYNC_DATA_SETUP_TIME  0x0036
0275 #define MBOX_SET_SBUS_CONTROL_PARAMS    0x0037
0276 #define MBOX_SET_TARGET_PARAMS      0x0038
0277 #define MBOX_SET_DEV_QUEUE_PARAMS   0x0039
0278 
0279 struct host_param {
0280     u_short     initiator_scsi_id;
0281     u_short     bus_reset_delay;
0282     u_short     retry_count;
0283     u_short     retry_delay;
0284     u_short     async_data_setup_time;
0285     u_short     req_ack_active_negation;
0286     u_short     data_line_active_negation;
0287     u_short     data_dma_burst_enable;
0288     u_short     command_dma_burst_enable;
0289     u_short     tag_aging;
0290     u_short     selection_timeout;
0291     u_short     max_queue_depth;
0292 };
0293 
0294 /*
0295  * Device Flags:
0296  *
0297  * Bit  Name
0298  * ---------
0299  *  7   Disconnect Privilege
0300  *  6   Parity Checking
0301  *  5   Wide Data Transfers
0302  *  4   Synchronous Data Transfers
0303  *  3   Tagged Queuing
0304  *  2   Automatic Request Sense
0305  *  1   Stop Queue on Check Condition
0306  *  0   Renegotiate on Error
0307  */
0308 
0309 struct dev_param {
0310     u_short     device_flags;
0311     u_short     execution_throttle;
0312     u_short     synchronous_period;
0313     u_short     synchronous_offset;
0314     u_short     device_enable;
0315     u_short     reserved; /* pad */
0316 };
0317 
0318 /*
0319  * The result queue can be quite a bit smaller since continuation entries
0320  * do not show up there:
0321  */
0322 #define RES_QUEUE_LEN       255 /* Must be power of two - 1 */
0323 #define QUEUE_ENTRY_LEN     64
0324 
0325 #define NEXT_REQ_PTR(wheee)   (((wheee) + 1) & QLOGICPTI_REQ_QUEUE_LEN)
0326 #define NEXT_RES_PTR(wheee)   (((wheee) + 1) & RES_QUEUE_LEN)
0327 #define PREV_REQ_PTR(wheee)   (((wheee) - 1) & QLOGICPTI_REQ_QUEUE_LEN)
0328 #define PREV_RES_PTR(wheee)   (((wheee) - 1) & RES_QUEUE_LEN)
0329 
0330 struct pti_queue_entry {
0331     char __opaque[QUEUE_ENTRY_LEN];
0332 };
0333 
0334 struct scsi_cmnd;
0335 
0336 /* Software state for the driver. */
0337 struct qlogicpti {
0338     /* These are the hot elements in the cache, so they come first. */
0339     void __iomem             *qregs;                /* Adapter registers          */
0340     struct pti_queue_entry   *res_cpu;              /* Ptr to RESPONSE bufs (CPU) */
0341     struct pti_queue_entry   *req_cpu;              /* Ptr to REQUEST bufs (CPU)  */
0342 
0343     u_int                     req_in_ptr;       /* index of next request slot */
0344     u_int                     res_out_ptr;      /* index of next result slot  */
0345     long                      send_marker;      /* must we send a marker?     */
0346     struct platform_device   *op;
0347     unsigned long         __pad;
0348 
0349     int                       cmd_count[MAX_TARGETS];
0350     unsigned long             tag_ages[MAX_TARGETS];
0351 
0352     /* The cmd->handler is only 32-bits, so that things work even on monster
0353      * Ex000 sparc64 machines with >4GB of ram we just keep track of the
0354      * scsi command pointers here.  This is essentially what Matt Jacob does. -DaveM
0355      */
0356     struct scsi_cmnd         *cmd_slots[QLOGICPTI_REQ_QUEUE_LEN + 1];
0357 
0358     /* The rest of the elements are unimportant for performance. */
0359     struct qlogicpti         *next;
0360     dma_addr_t                res_dvma;             /* Ptr to RESPONSE bufs (DVMA)*/
0361     dma_addr_t                req_dvma;             /* Ptr to REQUEST bufs (DVMA) */
0362     u_char                    fware_majrev, fware_minrev, fware_micrev;
0363     struct Scsi_Host         *qhost;
0364     int                       qpti_id;
0365     int                       scsi_id;
0366     int                       prom_node;
0367     int                       irq;
0368     char                      differential, ultra, clock;
0369     unsigned char             bursts;
0370     struct  host_param        host_param;
0371     struct  dev_param         dev_param[MAX_TARGETS];
0372 
0373     void __iomem              *sreg;
0374 #define SREG_TPOWER               0x80   /* State of termpwr           */
0375 #define SREG_FUSE                 0x40   /* State of on board fuse     */
0376 #define SREG_PDISAB               0x20   /* Disable state for power on */
0377 #define SREG_DSENSE               0x10   /* Sense for differential     */
0378 #define SREG_IMASK                0x0c   /* Interrupt level            */
0379 #define SREG_SPMASK               0x03   /* Mask for switch pack       */
0380     unsigned char             swsreg;
0381     unsigned int
0382         gotirq  :   1,  /* this instance got an irq */
0383         is_pti  :   1;  /* Non-zero if this is a PTI board. */
0384 };
0385 
0386 /* How to twiddle them bits... */
0387 
0388 /* SBUS config register one. */
0389 #define SBUS_CFG1_EPAR          0x0100      /* Enable parity checking           */
0390 #define SBUS_CFG1_FMASK         0x00f0      /* Forth code cycle mask            */
0391 #define SBUS_CFG1_BENAB         0x0004      /* Burst dvma enable                */
0392 #define SBUS_CFG1_B64           0x0003      /* Enable 64byte bursts             */
0393 #define SBUS_CFG1_B32           0x0002      /* Enable 32byte bursts             */
0394 #define SBUS_CFG1_B16           0x0001      /* Enable 16byte bursts             */
0395 #define SBUS_CFG1_B8            0x0008      /* Enable 8byte bursts              */
0396 
0397 /* SBUS control register */
0398 #define SBUS_CTRL_EDIRQ         0x0020      /* Enable Data DVMA Interrupts      */
0399 #define SBUS_CTRL_ECIRQ         0x0010      /* Enable Command DVMA Interrupts   */
0400 #define SBUS_CTRL_ESIRQ         0x0008      /* Enable SCSI Processor Interrupts */
0401 #define SBUS_CTRL_ERIRQ         0x0004      /* Enable RISC Processor Interrupts */
0402 #define SBUS_CTRL_GENAB         0x0002      /* Global Interrupt Enable          */
0403 #define SBUS_CTRL_RESET         0x0001      /* Soft Reset                       */
0404 
0405 /* SBUS status register */
0406 #define SBUS_STAT_DINT          0x0020      /* Data DVMA IRQ pending            */
0407 #define SBUS_STAT_CINT          0x0010      /* Command DVMA IRQ pending         */
0408 #define SBUS_STAT_SINT          0x0008      /* SCSI Processor IRQ pending       */
0409 #define SBUS_STAT_RINT          0x0004      /* RISC Processor IRQ pending       */
0410 #define SBUS_STAT_GINT          0x0002      /* Global IRQ pending               */
0411 
0412 /* SBUS semaphore register */
0413 #define SBUS_SEMAPHORE_STAT     0x0002      /* Semaphore status bit             */
0414 #define SBUS_SEMAPHORE_LCK      0x0001      /* Semaphore lock bit               */
0415 
0416 /* DVMA control register */
0417 #define DMA_CTRL_CSUSPEND       0x0010      /* DMA channel suspend              */
0418 #define DMA_CTRL_CCLEAR         0x0008      /* DMA channel clear and reset      */
0419 #define DMA_CTRL_FCLEAR         0x0004      /* DMA fifo clear                   */
0420 #define DMA_CTRL_CIRQ           0x0002      /* DMA irq clear                    */
0421 #define DMA_CTRL_DMASTART       0x0001      /* DMA transfer start               */
0422 
0423 /* SCSI processor override register */
0424 #define CPU_ORIDE_ETRIG         0x8000      /* External trigger enable          */
0425 #define CPU_ORIDE_STEP          0x4000      /* Single step mode enable          */
0426 #define CPU_ORIDE_BKPT          0x2000      /* Breakpoint reg enable            */
0427 #define CPU_ORIDE_PWRITE        0x1000      /* SCSI pin write enable            */
0428 #define CPU_ORIDE_OFORCE        0x0800      /* Force outputs on                 */
0429 #define CPU_ORIDE_LBACK         0x0400      /* SCSI loopback enable             */
0430 #define CPU_ORIDE_PTEST         0x0200      /* Parity test enable               */
0431 #define CPU_ORIDE_TENAB         0x0100      /* SCSI pins tristate enable        */
0432 #define CPU_ORIDE_TPINS         0x0080      /* SCSI pins enable                 */
0433 #define CPU_ORIDE_FRESET        0x0008      /* FIFO reset                       */
0434 #define CPU_ORIDE_CTERM         0x0004      /* Command terminate                */
0435 #define CPU_ORIDE_RREG          0x0002      /* Reset SCSI processor regs        */
0436 #define CPU_ORIDE_RMOD          0x0001      /* Reset SCSI processor module      */
0437 
0438 /* SCSI processor commands */
0439 #define CPU_CMD_BRESET          0x300b      /* Reset SCSI bus                   */
0440 
0441 /* SCSI processor pin control register */
0442 #define CPU_PCTRL_PVALID        0x8000      /* Phase bits are valid             */
0443 #define CPU_PCTRL_PHI           0x0400      /* Parity bit high                  */
0444 #define CPU_PCTRL_PLO           0x0200      /* Parity bit low                   */
0445 #define CPU_PCTRL_REQ           0x0100      /* REQ bus signal                   */
0446 #define CPU_PCTRL_ACK           0x0080      /* ACK bus signal                   */
0447 #define CPU_PCTRL_RST           0x0040      /* RST bus signal                   */
0448 #define CPU_PCTRL_BSY           0x0020      /* BSY bus signal                   */
0449 #define CPU_PCTRL_SEL           0x0010      /* SEL bus signal                   */
0450 #define CPU_PCTRL_ATN           0x0008      /* ATN bus signal                   */
0451 #define CPU_PCTRL_MSG           0x0004      /* MSG bus signal                   */
0452 #define CPU_PCTRL_CD            0x0002      /* CD bus signal                    */
0453 #define CPU_PCTRL_IO            0x0001      /* IO bus signal                    */
0454 
0455 /* SCSI processor differential pins register */
0456 #define CPU_PDIFF_SENSE         0x0200      /* Differential sense               */
0457 #define CPU_PDIFF_MODE          0x0100      /* Differential mode                */
0458 #define CPU_PDIFF_OENAB         0x0080      /* Outputs enable                   */
0459 #define CPU_PDIFF_PMASK         0x007c      /* Differential control pins        */
0460 #define CPU_PDIFF_TGT           0x0002      /* Target mode enable               */
0461 #define CPU_PDIFF_INIT          0x0001      /* Initiator mode enable            */
0462 
0463 /* RISC processor status register */
0464 #define RISC_PSR_FTRUE          0x8000      /* Force true                       */
0465 #define RISC_PSR_LCD            0x4000      /* Loop counter shows done status   */
0466 #define RISC_PSR_RIRQ           0x2000      /* RISC irq status                  */
0467 #define RISC_PSR_TOFLOW         0x1000      /* Timer overflow (rollover)        */
0468 #define RISC_PSR_AOFLOW         0x0800      /* Arithmetic overflow              */
0469 #define RISC_PSR_AMSB           0x0400      /* Arithmetic big endian            */
0470 #define RISC_PSR_ACARRY         0x0200      /* Arithmetic carry                 */
0471 #define RISC_PSR_AZERO          0x0100      /* Arithmetic zero                  */
0472 #define RISC_PSR_ULTRA          0x0020      /* Ultra mode                       */
0473 #define RISC_PSR_DIRQ           0x0010      /* DVMA interrupt                   */
0474 #define RISC_PSR_SIRQ           0x0008      /* SCSI processor interrupt         */
0475 #define RISC_PSR_HIRQ           0x0004      /* Host interrupt                   */
0476 #define RISC_PSR_IPEND          0x0002      /* Interrupt pending                */
0477 #define RISC_PSR_FFALSE         0x0001      /* Force false                      */
0478 
0479 /* RISC processor memory timing register */
0480 #define RISC_MTREG_P1DFLT       0x1200      /* Default read/write timing, pg1   */
0481 #define RISC_MTREG_P0DFLT       0x0012      /* Default read/write timing, pg0   */
0482 #define RISC_MTREG_P1ULTRA      0x2300      /* Ultra-mode rw timing, pg1        */
0483 #define RISC_MTREG_P0ULTRA      0x0023      /* Ultra-mode rw timing, pg0        */
0484 
0485 /* Host command/ctrl register */
0486 #define HCCTRL_NOP              0x0000      /* CMD: No operation                */
0487 #define HCCTRL_RESET            0x1000      /* CMD: Reset RISC cpu              */
0488 #define HCCTRL_PAUSE            0x2000      /* CMD: Pause RISC cpu              */
0489 #define HCCTRL_REL              0x3000      /* CMD: Release paused RISC cpu     */
0490 #define HCCTRL_STEP             0x4000      /* CMD: Single step RISC cpu        */
0491 #define HCCTRL_SHIRQ            0x5000      /* CMD: Set host irq                */
0492 #define HCCTRL_CHIRQ            0x6000      /* CMD: Clear host irq              */
0493 #define HCCTRL_CRIRQ            0x7000      /* CMD: Clear RISC cpu irq          */
0494 #define HCCTRL_BKPT             0x8000      /* CMD: Breakpoint enables change   */
0495 #define HCCTRL_TMODE            0xf000      /* CMD: Enable test mode            */
0496 #define HCCTRL_HIRQ             0x0080      /* Host IRQ pending                 */
0497 #define HCCTRL_RRIP             0x0040      /* RISC cpu reset in happening now  */
0498 #define HCCTRL_RPAUSED          0x0020      /* RISC cpu is paused now           */
0499 #define HCCTRL_EBENAB           0x0010      /* External breakpoint enable       */
0500 #define HCCTRL_B1ENAB           0x0008      /* Breakpoint 1 enable              */
0501 #define HCCTRL_B0ENAB           0x0004      /* Breakpoint 0 enable              */
0502 
0503 /* For our interrupt engine. */
0504 #define for_each_qlogicpti(qp) \
0505         for((qp) = qptichain; (qp); (qp) = (qp)->next)
0506 
0507 #endif /* !(_QLOGICPTI_H) */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!