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0007 #ifndef __QLA_DMP27_H__
0008 #define __QLA_DMP27_H__
0009
0010 #define IOBASE_ADDR offsetof(struct device_reg_24xx, iobase_addr)
0011
0012 struct __packed qla27xx_fwdt_template {
0013 __le32 template_type;
0014 __le32 entry_offset;
0015 __le32 template_size;
0016 uint32_t count;
0017
0018 __le32 entry_count;
0019 uint32_t template_version;
0020 __le32 capture_timestamp;
0021 uint32_t template_checksum;
0022
0023 uint32_t reserved_2;
0024 __le32 driver_info[3];
0025
0026 uint32_t saved_state[16];
0027
0028 uint32_t reserved_3[8];
0029 __le32 firmware_version[5];
0030 };
0031
0032 #define TEMPLATE_TYPE_FWDUMP 99
0033
0034 #define ENTRY_TYPE_NOP 0
0035 #define ENTRY_TYPE_TMP_END 255
0036 #define ENTRY_TYPE_RD_IOB_T1 256
0037 #define ENTRY_TYPE_WR_IOB_T1 257
0038 #define ENTRY_TYPE_RD_IOB_T2 258
0039 #define ENTRY_TYPE_WR_IOB_T2 259
0040 #define ENTRY_TYPE_RD_PCI 260
0041 #define ENTRY_TYPE_WR_PCI 261
0042 #define ENTRY_TYPE_RD_RAM 262
0043 #define ENTRY_TYPE_GET_QUEUE 263
0044 #define ENTRY_TYPE_GET_FCE 264
0045 #define ENTRY_TYPE_PSE_RISC 265
0046 #define ENTRY_TYPE_RST_RISC 266
0047 #define ENTRY_TYPE_DIS_INTR 267
0048 #define ENTRY_TYPE_GET_HBUF 268
0049 #define ENTRY_TYPE_SCRATCH 269
0050 #define ENTRY_TYPE_RDREMREG 270
0051 #define ENTRY_TYPE_WRREMREG 271
0052 #define ENTRY_TYPE_RDREMRAM 272
0053 #define ENTRY_TYPE_PCICFG 273
0054 #define ENTRY_TYPE_GET_SHADOW 274
0055 #define ENTRY_TYPE_WRITE_BUF 275
0056 #define ENTRY_TYPE_CONDITIONAL 276
0057 #define ENTRY_TYPE_RDPEPREG 277
0058 #define ENTRY_TYPE_WRPEPREG 278
0059
0060 #define CAPTURE_FLAG_PHYS_ONLY BIT_0
0061 #define CAPTURE_FLAG_PHYS_VIRT BIT_1
0062
0063 #define DRIVER_FLAG_SKIP_ENTRY BIT_7
0064
0065 struct __packed qla27xx_fwdt_entry {
0066 struct __packed {
0067 __le32 type;
0068 __le32 size;
0069 uint32_t reserved_1;
0070
0071 uint8_t capture_flags;
0072 uint8_t reserved_2[2];
0073 uint8_t driver_flags;
0074 } hdr;
0075 union __packed {
0076 struct __packed {
0077 } t0;
0078
0079 struct __packed {
0080 } t255;
0081
0082 struct __packed {
0083 __le32 base_addr;
0084 uint8_t reg_width;
0085 __le16 reg_count;
0086 uint8_t pci_offset;
0087 } t256;
0088
0089 struct __packed {
0090 __le32 base_addr;
0091 __le32 write_data;
0092 uint8_t pci_offset;
0093 uint8_t reserved[3];
0094 } t257;
0095
0096 struct __packed {
0097 __le32 base_addr;
0098 uint8_t reg_width;
0099 __le16 reg_count;
0100 uint8_t pci_offset;
0101 uint8_t banksel_offset;
0102 uint8_t reserved[3];
0103 __le32 bank;
0104 } t258;
0105
0106 struct __packed {
0107 __le32 base_addr;
0108 __le32 write_data;
0109 uint8_t reserved[2];
0110 uint8_t pci_offset;
0111 uint8_t banksel_offset;
0112 __le32 bank;
0113 } t259;
0114
0115 struct __packed {
0116 uint8_t pci_offset;
0117 uint8_t reserved[3];
0118 } t260;
0119
0120 struct __packed {
0121 uint8_t pci_offset;
0122 uint8_t reserved[3];
0123 __le32 write_data;
0124 } t261;
0125
0126 struct __packed {
0127 uint8_t ram_area;
0128 uint8_t reserved[3];
0129 __le32 start_addr;
0130 __le32 end_addr;
0131 } t262;
0132
0133 struct __packed {
0134 uint32_t num_queues;
0135 uint8_t queue_type;
0136 uint8_t reserved[3];
0137 } t263;
0138
0139 struct __packed {
0140 uint32_t fce_trace_size;
0141 uint64_t write_pointer;
0142 uint64_t base_pointer;
0143 uint32_t fce_enable_mb0;
0144 uint32_t fce_enable_mb2;
0145 uint32_t fce_enable_mb3;
0146 uint32_t fce_enable_mb4;
0147 uint32_t fce_enable_mb5;
0148 uint32_t fce_enable_mb6;
0149 } t264;
0150
0151 struct __packed {
0152 } t265;
0153
0154 struct __packed {
0155 } t266;
0156
0157 struct __packed {
0158 uint8_t pci_offset;
0159 uint8_t reserved[3];
0160 __le32 data;
0161 } t267;
0162
0163 struct __packed {
0164 uint8_t buf_type;
0165 uint8_t reserved[3];
0166 uint32_t buf_size;
0167 uint64_t start_addr;
0168 } t268;
0169
0170 struct __packed {
0171 uint32_t scratch_size;
0172 } t269;
0173
0174 struct __packed {
0175 __le32 addr;
0176 __le32 count;
0177 } t270;
0178
0179 struct __packed {
0180 __le32 addr;
0181 __le32 data;
0182 } t271;
0183
0184 struct __packed {
0185 __le32 addr;
0186 __le32 count;
0187 } t272;
0188
0189 struct __packed {
0190 __le32 addr;
0191 __le32 count;
0192 } t273;
0193
0194 struct __packed {
0195 uint32_t num_queues;
0196 uint8_t queue_type;
0197 uint8_t reserved[3];
0198 } t274;
0199
0200 struct __packed {
0201 __le32 length;
0202 uint8_t buffer[];
0203 } t275;
0204
0205 struct __packed {
0206 __le32 cond1;
0207 __le32 cond2;
0208 } t276;
0209
0210 struct __packed {
0211 __le32 cmd_addr;
0212 __le32 wr_cmd_data;
0213 __le32 data_addr;
0214 } t277;
0215
0216 struct __packed {
0217 __le32 cmd_addr;
0218 __le32 wr_cmd_data;
0219 __le32 data_addr;
0220 __le32 wr_data;
0221 } t278;
0222 };
0223 };
0224
0225 #define T262_RAM_AREA_CRITICAL_RAM 1
0226 #define T262_RAM_AREA_EXTERNAL_RAM 2
0227 #define T262_RAM_AREA_SHARED_RAM 3
0228 #define T262_RAM_AREA_DDR_RAM 4
0229 #define T262_RAM_AREA_MISC 5
0230
0231 #define T263_QUEUE_TYPE_REQ 1
0232 #define T263_QUEUE_TYPE_RSP 2
0233 #define T263_QUEUE_TYPE_ATIO 3
0234
0235 #define T268_BUF_TYPE_EXTD_TRACE 1
0236 #define T268_BUF_TYPE_EXCH_BUFOFF 2
0237 #define T268_BUF_TYPE_EXTD_LOGIN 3
0238 #define T268_BUF_TYPE_REQ_MIRROR 4
0239 #define T268_BUF_TYPE_RSP_MIRROR 5
0240
0241 #define T274_QUEUE_TYPE_REQ_SHAD 1
0242 #define T274_QUEUE_TYPE_RSP_SHAD 2
0243 #define T274_QUEUE_TYPE_ATIO_SHAD 3
0244
0245 #endif
