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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * QLogic Fibre Channel HBA Driver
0004  * Copyright (c)  2003-2014 QLogic Corporation
0005  */
0006 #include "qla_def.h"
0007 #include "qla_tmpl.h"
0008 
0009 #define ISPREG(vha) (&(vha)->hw->iobase->isp24)
0010 #define IOBAR(reg)  offsetof(typeof(*(reg)), iobase_addr)
0011 #define IOBASE(vha) IOBAR(ISPREG(vha))
0012 #define INVALID_ENTRY ((struct qla27xx_fwdt_entry *)0xffffffffffffffffUL)
0013 
0014 static inline void
0015 qla27xx_insert16(uint16_t value, void *buf, ulong *len)
0016 {
0017     if (buf) {
0018         buf += *len;
0019         *(__le16 *)buf = cpu_to_le16(value);
0020     }
0021     *len += sizeof(value);
0022 }
0023 
0024 static inline void
0025 qla27xx_insert32(uint32_t value, void *buf, ulong *len)
0026 {
0027     if (buf) {
0028         buf += *len;
0029         *(__le32 *)buf = cpu_to_le32(value);
0030     }
0031     *len += sizeof(value);
0032 }
0033 
0034 static inline void
0035 qla27xx_insertbuf(void *mem, ulong size, void *buf, ulong *len)
0036 {
0037     if (buf && mem && size) {
0038         buf += *len;
0039         memcpy(buf, mem, size);
0040     }
0041     *len += size;
0042 }
0043 
0044 static inline void
0045 qla27xx_read8(void __iomem *window, void *buf, ulong *len)
0046 {
0047     uint8_t value = ~0;
0048 
0049     if (buf) {
0050         value = rd_reg_byte(window);
0051     }
0052     qla27xx_insert32(value, buf, len);
0053 }
0054 
0055 static inline void
0056 qla27xx_read16(void __iomem *window, void *buf, ulong *len)
0057 {
0058     uint16_t value = ~0;
0059 
0060     if (buf) {
0061         value = rd_reg_word(window);
0062     }
0063     qla27xx_insert32(value, buf, len);
0064 }
0065 
0066 static inline void
0067 qla27xx_read32(void __iomem *window, void *buf, ulong *len)
0068 {
0069     uint32_t value = ~0;
0070 
0071     if (buf) {
0072         value = rd_reg_dword(window);
0073     }
0074     qla27xx_insert32(value, buf, len);
0075 }
0076 
0077 static inline void (*qla27xx_read_vector(uint width))(void __iomem*, void *, ulong *)
0078 {
0079     return
0080         (width == 1) ? qla27xx_read8 :
0081         (width == 2) ? qla27xx_read16 :
0082                qla27xx_read32;
0083 }
0084 
0085 static inline void
0086 qla27xx_read_reg(__iomem struct device_reg_24xx *reg,
0087     uint offset, void *buf, ulong *len)
0088 {
0089     void __iomem *window = (void __iomem *)reg + offset;
0090 
0091     qla27xx_read32(window, buf, len);
0092 }
0093 
0094 static inline void
0095 qla27xx_write_reg(__iomem struct device_reg_24xx *reg,
0096     uint offset, uint32_t data, void *buf)
0097 {
0098     if (buf) {
0099         void __iomem *window = (void __iomem *)reg + offset;
0100 
0101         wrt_reg_dword(window, data);
0102     }
0103 }
0104 
0105 static inline void
0106 qla27xx_read_window(__iomem struct device_reg_24xx *reg,
0107     uint32_t addr, uint offset, uint count, uint width, void *buf,
0108     ulong *len)
0109 {
0110     void __iomem *window = (void __iomem *)reg + offset;
0111     void (*readn)(void __iomem*, void *, ulong *) = qla27xx_read_vector(width);
0112 
0113     qla27xx_write_reg(reg, IOBAR(reg), addr, buf);
0114     while (count--) {
0115         qla27xx_insert32(addr, buf, len);
0116         readn(window, buf, len);
0117         window += width;
0118         addr++;
0119     }
0120 }
0121 
0122 static inline void
0123 qla27xx_skip_entry(struct qla27xx_fwdt_entry *ent, void *buf)
0124 {
0125     if (buf)
0126         ent->hdr.driver_flags |= DRIVER_FLAG_SKIP_ENTRY;
0127 }
0128 
0129 static inline struct qla27xx_fwdt_entry *
0130 qla27xx_next_entry(struct qla27xx_fwdt_entry *ent)
0131 {
0132     return (void *)ent + le32_to_cpu(ent->hdr.size);
0133 }
0134 
0135 static struct qla27xx_fwdt_entry *
0136 qla27xx_fwdt_entry_t0(struct scsi_qla_host *vha,
0137     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0138 {
0139     ql_dbg(ql_dbg_misc, vha, 0xd100,
0140         "%s: nop [%lx]\n", __func__, *len);
0141     qla27xx_skip_entry(ent, buf);
0142 
0143     return qla27xx_next_entry(ent);
0144 }
0145 
0146 static struct qla27xx_fwdt_entry *
0147 qla27xx_fwdt_entry_t255(struct scsi_qla_host *vha,
0148     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0149 {
0150     ql_dbg(ql_dbg_misc, vha, 0xd1ff,
0151         "%s: end [%lx]\n", __func__, *len);
0152     qla27xx_skip_entry(ent, buf);
0153 
0154     /* terminate */
0155     return NULL;
0156 }
0157 
0158 static struct qla27xx_fwdt_entry *
0159 qla27xx_fwdt_entry_t256(struct scsi_qla_host *vha,
0160     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0161 {
0162     ulong addr = le32_to_cpu(ent->t256.base_addr);
0163     uint offset = ent->t256.pci_offset;
0164     ulong count = le16_to_cpu(ent->t256.reg_count);
0165     uint width = ent->t256.reg_width;
0166 
0167     ql_dbg(ql_dbg_misc, vha, 0xd200,
0168         "%s: rdio t1 [%lx]\n", __func__, *len);
0169     qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
0170 
0171     return qla27xx_next_entry(ent);
0172 }
0173 
0174 static struct qla27xx_fwdt_entry *
0175 qla27xx_fwdt_entry_t257(struct scsi_qla_host *vha,
0176     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0177 {
0178     ulong addr = le32_to_cpu(ent->t257.base_addr);
0179     uint offset = ent->t257.pci_offset;
0180     ulong data = le32_to_cpu(ent->t257.write_data);
0181 
0182     ql_dbg(ql_dbg_misc, vha, 0xd201,
0183         "%s: wrio t1 [%lx]\n", __func__, *len);
0184     qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
0185     qla27xx_write_reg(ISPREG(vha), offset, data, buf);
0186 
0187     return qla27xx_next_entry(ent);
0188 }
0189 
0190 static struct qla27xx_fwdt_entry *
0191 qla27xx_fwdt_entry_t258(struct scsi_qla_host *vha,
0192     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0193 {
0194     uint banksel = ent->t258.banksel_offset;
0195     ulong bank = le32_to_cpu(ent->t258.bank);
0196     ulong addr = le32_to_cpu(ent->t258.base_addr);
0197     uint offset = ent->t258.pci_offset;
0198     uint count = le16_to_cpu(ent->t258.reg_count);
0199     uint width = ent->t258.reg_width;
0200 
0201     ql_dbg(ql_dbg_misc, vha, 0xd202,
0202         "%s: rdio t2 [%lx]\n", __func__, *len);
0203     qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
0204     qla27xx_read_window(ISPREG(vha), addr, offset, count, width, buf, len);
0205 
0206     return qla27xx_next_entry(ent);
0207 }
0208 
0209 static struct qla27xx_fwdt_entry *
0210 qla27xx_fwdt_entry_t259(struct scsi_qla_host *vha,
0211     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0212 {
0213     ulong addr = le32_to_cpu(ent->t259.base_addr);
0214     uint banksel = ent->t259.banksel_offset;
0215     ulong bank = le32_to_cpu(ent->t259.bank);
0216     uint offset = ent->t259.pci_offset;
0217     ulong data = le32_to_cpu(ent->t259.write_data);
0218 
0219     ql_dbg(ql_dbg_misc, vha, 0xd203,
0220         "%s: wrio t2 [%lx]\n", __func__, *len);
0221     qla27xx_write_reg(ISPREG(vha), IOBASE(vha), addr, buf);
0222     qla27xx_write_reg(ISPREG(vha), banksel, bank, buf);
0223     qla27xx_write_reg(ISPREG(vha), offset, data, buf);
0224 
0225     return qla27xx_next_entry(ent);
0226 }
0227 
0228 static struct qla27xx_fwdt_entry *
0229 qla27xx_fwdt_entry_t260(struct scsi_qla_host *vha,
0230     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0231 {
0232     uint offset = ent->t260.pci_offset;
0233 
0234     ql_dbg(ql_dbg_misc, vha, 0xd204,
0235         "%s: rdpci [%lx]\n", __func__, *len);
0236     qla27xx_insert32(offset, buf, len);
0237     qla27xx_read_reg(ISPREG(vha), offset, buf, len);
0238 
0239     return qla27xx_next_entry(ent);
0240 }
0241 
0242 static struct qla27xx_fwdt_entry *
0243 qla27xx_fwdt_entry_t261(struct scsi_qla_host *vha,
0244     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0245 {
0246     uint offset = ent->t261.pci_offset;
0247     ulong data = le32_to_cpu(ent->t261.write_data);
0248 
0249     ql_dbg(ql_dbg_misc, vha, 0xd205,
0250         "%s: wrpci [%lx]\n", __func__, *len);
0251     qla27xx_write_reg(ISPREG(vha), offset, data, buf);
0252 
0253     return qla27xx_next_entry(ent);
0254 }
0255 
0256 static struct qla27xx_fwdt_entry *
0257 qla27xx_fwdt_entry_t262(struct scsi_qla_host *vha,
0258     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0259 {
0260     uint area = ent->t262.ram_area;
0261     ulong start = le32_to_cpu(ent->t262.start_addr);
0262     ulong end = le32_to_cpu(ent->t262.end_addr);
0263     ulong dwords;
0264     int rc;
0265 
0266     ql_dbg(ql_dbg_misc, vha, 0xd206,
0267         "%s: rdram(%x) [%lx]\n", __func__, ent->t262.ram_area, *len);
0268 
0269     if (area == T262_RAM_AREA_CRITICAL_RAM) {
0270         ;
0271     } else if (area == T262_RAM_AREA_EXTERNAL_RAM) {
0272         end = vha->hw->fw_memory_size;
0273         if (buf)
0274             ent->t262.end_addr = cpu_to_le32(end);
0275     } else if (area == T262_RAM_AREA_SHARED_RAM) {
0276         start = vha->hw->fw_shared_ram_start;
0277         end = vha->hw->fw_shared_ram_end;
0278         if (buf) {
0279             ent->t262.start_addr = cpu_to_le32(start);
0280             ent->t262.end_addr = cpu_to_le32(end);
0281         }
0282     } else if (area == T262_RAM_AREA_DDR_RAM) {
0283         start = vha->hw->fw_ddr_ram_start;
0284         end = vha->hw->fw_ddr_ram_end;
0285         if (buf) {
0286             ent->t262.start_addr = cpu_to_le32(start);
0287             ent->t262.end_addr = cpu_to_le32(end);
0288         }
0289     } else if (area == T262_RAM_AREA_MISC) {
0290         if (buf) {
0291             ent->t262.start_addr = cpu_to_le32(start);
0292             ent->t262.end_addr = cpu_to_le32(end);
0293         }
0294     } else {
0295         ql_dbg(ql_dbg_misc, vha, 0xd022,
0296             "%s: unknown area %x\n", __func__, area);
0297         qla27xx_skip_entry(ent, buf);
0298         goto done;
0299     }
0300 
0301     if (end < start || start == 0 || end == 0) {
0302         ql_dbg(ql_dbg_misc, vha, 0xd023,
0303             "%s: unusable range (start=%lx end=%lx)\n",
0304             __func__, start, end);
0305         qla27xx_skip_entry(ent, buf);
0306         goto done;
0307     }
0308 
0309     dwords = end - start + 1;
0310     if (buf) {
0311         buf += *len;
0312         rc = qla24xx_dump_ram(vha->hw, start, buf, dwords, &buf);
0313         if (rc != QLA_SUCCESS) {
0314             ql_dbg(ql_dbg_async, vha, 0xffff,
0315                 "%s: dump ram MB failed. Area %xh start %lxh end %lxh\n",
0316                 __func__, area, start, end);
0317             return INVALID_ENTRY;
0318         }
0319     }
0320     *len += dwords * sizeof(uint32_t);
0321 done:
0322     return qla27xx_next_entry(ent);
0323 }
0324 
0325 static struct qla27xx_fwdt_entry *
0326 qla27xx_fwdt_entry_t263(struct scsi_qla_host *vha,
0327     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0328 {
0329     uint type = ent->t263.queue_type;
0330     uint count = 0;
0331     uint i;
0332     uint length;
0333 
0334     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd207,
0335         "%s: getq(%x) [%lx]\n", __func__, type, *len);
0336     if (type == T263_QUEUE_TYPE_REQ) {
0337         for (i = 0; i < vha->hw->max_req_queues; i++) {
0338             struct req_que *req = vha->hw->req_q_map[i];
0339 
0340             if (req || !buf) {
0341                 length = req ?
0342                     req->length : REQUEST_ENTRY_CNT_24XX;
0343                 qla27xx_insert16(i, buf, len);
0344                 qla27xx_insert16(length, buf, len);
0345                 qla27xx_insertbuf(req ? req->ring : NULL,
0346                     length * sizeof(*req->ring), buf, len);
0347                 count++;
0348             }
0349         }
0350     } else if (type == T263_QUEUE_TYPE_RSP) {
0351         for (i = 0; i < vha->hw->max_rsp_queues; i++) {
0352             struct rsp_que *rsp = vha->hw->rsp_q_map[i];
0353 
0354             if (rsp || !buf) {
0355                 length = rsp ?
0356                     rsp->length : RESPONSE_ENTRY_CNT_MQ;
0357                 qla27xx_insert16(i, buf, len);
0358                 qla27xx_insert16(length, buf, len);
0359                 qla27xx_insertbuf(rsp ? rsp->ring : NULL,
0360                     length * sizeof(*rsp->ring), buf, len);
0361                 count++;
0362             }
0363         }
0364     } else if (QLA_TGT_MODE_ENABLED() &&
0365         ent->t263.queue_type == T263_QUEUE_TYPE_ATIO) {
0366         struct qla_hw_data *ha = vha->hw;
0367         struct atio *atr = ha->tgt.atio_ring;
0368 
0369         if (atr || !buf) {
0370             length = ha->tgt.atio_q_length;
0371             qla27xx_insert16(0, buf, len);
0372             qla27xx_insert16(length, buf, len);
0373             qla27xx_insertbuf(atr, length * sizeof(*atr), buf, len);
0374             count++;
0375         }
0376     } else {
0377         ql_dbg(ql_dbg_misc, vha, 0xd026,
0378             "%s: unknown queue %x\n", __func__, type);
0379         qla27xx_skip_entry(ent, buf);
0380     }
0381 
0382     if (buf) {
0383         if (count)
0384             ent->t263.num_queues = count;
0385         else
0386             qla27xx_skip_entry(ent, buf);
0387     }
0388 
0389     return qla27xx_next_entry(ent);
0390 }
0391 
0392 static struct qla27xx_fwdt_entry *
0393 qla27xx_fwdt_entry_t264(struct scsi_qla_host *vha,
0394     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0395 {
0396     ql_dbg(ql_dbg_misc, vha, 0xd208,
0397         "%s: getfce [%lx]\n", __func__, *len);
0398     if (vha->hw->fce) {
0399         if (buf) {
0400             ent->t264.fce_trace_size = FCE_SIZE;
0401             ent->t264.write_pointer = vha->hw->fce_wr;
0402             ent->t264.base_pointer = vha->hw->fce_dma;
0403             ent->t264.fce_enable_mb0 = vha->hw->fce_mb[0];
0404             ent->t264.fce_enable_mb2 = vha->hw->fce_mb[2];
0405             ent->t264.fce_enable_mb3 = vha->hw->fce_mb[3];
0406             ent->t264.fce_enable_mb4 = vha->hw->fce_mb[4];
0407             ent->t264.fce_enable_mb5 = vha->hw->fce_mb[5];
0408             ent->t264.fce_enable_mb6 = vha->hw->fce_mb[6];
0409         }
0410         qla27xx_insertbuf(vha->hw->fce, FCE_SIZE, buf, len);
0411     } else {
0412         ql_dbg(ql_dbg_misc, vha, 0xd027,
0413             "%s: missing fce\n", __func__);
0414         qla27xx_skip_entry(ent, buf);
0415     }
0416 
0417     return qla27xx_next_entry(ent);
0418 }
0419 
0420 static struct qla27xx_fwdt_entry *
0421 qla27xx_fwdt_entry_t265(struct scsi_qla_host *vha,
0422     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0423 {
0424     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd209,
0425         "%s: pause risc [%lx]\n", __func__, *len);
0426     if (buf)
0427         qla24xx_pause_risc(ISPREG(vha), vha->hw);
0428 
0429     return qla27xx_next_entry(ent);
0430 }
0431 
0432 static struct qla27xx_fwdt_entry *
0433 qla27xx_fwdt_entry_t266(struct scsi_qla_host *vha,
0434     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0435 {
0436     ql_dbg(ql_dbg_misc, vha, 0xd20a,
0437         "%s: reset risc [%lx]\n", __func__, *len);
0438     if (buf) {
0439         if (qla24xx_soft_reset(vha->hw) != QLA_SUCCESS) {
0440             ql_dbg(ql_dbg_async, vha, 0x5001,
0441                 "%s: unable to soft reset\n", __func__);
0442             return INVALID_ENTRY;
0443         }
0444     }
0445 
0446     return qla27xx_next_entry(ent);
0447 }
0448 
0449 static struct qla27xx_fwdt_entry *
0450 qla27xx_fwdt_entry_t267(struct scsi_qla_host *vha,
0451     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0452 {
0453     uint offset = ent->t267.pci_offset;
0454     ulong data = le32_to_cpu(ent->t267.data);
0455 
0456     ql_dbg(ql_dbg_misc, vha, 0xd20b,
0457         "%s: dis intr [%lx]\n", __func__, *len);
0458     qla27xx_write_reg(ISPREG(vha), offset, data, buf);
0459 
0460     return qla27xx_next_entry(ent);
0461 }
0462 
0463 static struct qla27xx_fwdt_entry *
0464 qla27xx_fwdt_entry_t268(struct scsi_qla_host *vha,
0465     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0466 {
0467     ql_dbg(ql_dbg_misc, vha, 0xd20c,
0468         "%s: gethb(%x) [%lx]\n", __func__, ent->t268.buf_type, *len);
0469     switch (ent->t268.buf_type) {
0470     case T268_BUF_TYPE_EXTD_TRACE:
0471         if (vha->hw->eft) {
0472             if (buf) {
0473                 ent->t268.buf_size = EFT_SIZE;
0474                 ent->t268.start_addr = vha->hw->eft_dma;
0475             }
0476             qla27xx_insertbuf(vha->hw->eft, EFT_SIZE, buf, len);
0477         } else {
0478             ql_dbg(ql_dbg_misc, vha, 0xd028,
0479                 "%s: missing eft\n", __func__);
0480             qla27xx_skip_entry(ent, buf);
0481         }
0482         break;
0483     case T268_BUF_TYPE_EXCH_BUFOFF:
0484         if (vha->hw->exchoffld_buf) {
0485             if (buf) {
0486                 ent->t268.buf_size = vha->hw->exchoffld_size;
0487                 ent->t268.start_addr =
0488                     vha->hw->exchoffld_buf_dma;
0489             }
0490             qla27xx_insertbuf(vha->hw->exchoffld_buf,
0491                 vha->hw->exchoffld_size, buf, len);
0492         } else {
0493             ql_dbg(ql_dbg_misc, vha, 0xd028,
0494                 "%s: missing exch offld\n", __func__);
0495             qla27xx_skip_entry(ent, buf);
0496         }
0497         break;
0498     case T268_BUF_TYPE_EXTD_LOGIN:
0499         if (vha->hw->exlogin_buf) {
0500             if (buf) {
0501                 ent->t268.buf_size = vha->hw->exlogin_size;
0502                 ent->t268.start_addr =
0503                     vha->hw->exlogin_buf_dma;
0504             }
0505             qla27xx_insertbuf(vha->hw->exlogin_buf,
0506                 vha->hw->exlogin_size, buf, len);
0507         } else {
0508             ql_dbg(ql_dbg_misc, vha, 0xd028,
0509                 "%s: missing ext login\n", __func__);
0510             qla27xx_skip_entry(ent, buf);
0511         }
0512         break;
0513 
0514     case T268_BUF_TYPE_REQ_MIRROR:
0515     case T268_BUF_TYPE_RSP_MIRROR:
0516         /*
0517          * Mirror pointers are not implemented in the
0518          * driver, instead shadow pointers are used by
0519          * the drier. Skip these entries.
0520          */
0521         qla27xx_skip_entry(ent, buf);
0522         break;
0523     default:
0524         ql_dbg(ql_dbg_async, vha, 0xd02b,
0525             "%s: unknown buffer %x\n", __func__, ent->t268.buf_type);
0526         qla27xx_skip_entry(ent, buf);
0527         break;
0528     }
0529 
0530     return qla27xx_next_entry(ent);
0531 }
0532 
0533 static struct qla27xx_fwdt_entry *
0534 qla27xx_fwdt_entry_t269(struct scsi_qla_host *vha,
0535     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0536 {
0537     ql_dbg(ql_dbg_misc, vha, 0xd20d,
0538         "%s: scratch [%lx]\n", __func__, *len);
0539     qla27xx_insert32(0xaaaaaaaa, buf, len);
0540     qla27xx_insert32(0xbbbbbbbb, buf, len);
0541     qla27xx_insert32(0xcccccccc, buf, len);
0542     qla27xx_insert32(0xdddddddd, buf, len);
0543     qla27xx_insert32(*len + sizeof(uint32_t), buf, len);
0544     if (buf)
0545         ent->t269.scratch_size = 5 * sizeof(uint32_t);
0546 
0547     return qla27xx_next_entry(ent);
0548 }
0549 
0550 static struct qla27xx_fwdt_entry *
0551 qla27xx_fwdt_entry_t270(struct scsi_qla_host *vha,
0552     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0553 {
0554     ulong addr = le32_to_cpu(ent->t270.addr);
0555     ulong dwords = le32_to_cpu(ent->t270.count);
0556 
0557     ql_dbg(ql_dbg_misc, vha, 0xd20e,
0558         "%s: rdremreg [%lx]\n", __func__, *len);
0559     qla27xx_write_reg(ISPREG(vha), IOBASE_ADDR, 0x40, buf);
0560     while (dwords--) {
0561         qla27xx_write_reg(ISPREG(vha), 0xc0, addr|0x80000000, buf);
0562         qla27xx_insert32(addr, buf, len);
0563         qla27xx_read_reg(ISPREG(vha), 0xc4, buf, len);
0564         addr += sizeof(uint32_t);
0565     }
0566 
0567     return qla27xx_next_entry(ent);
0568 }
0569 
0570 static struct qla27xx_fwdt_entry *
0571 qla27xx_fwdt_entry_t271(struct scsi_qla_host *vha,
0572     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0573 {
0574     ulong addr = le32_to_cpu(ent->t271.addr);
0575     ulong data = le32_to_cpu(ent->t271.data);
0576 
0577     ql_dbg(ql_dbg_misc, vha, 0xd20f,
0578         "%s: wrremreg [%lx]\n", __func__, *len);
0579     qla27xx_write_reg(ISPREG(vha), IOBASE(vha), 0x40, buf);
0580     qla27xx_write_reg(ISPREG(vha), 0xc4, data, buf);
0581     qla27xx_write_reg(ISPREG(vha), 0xc0, addr, buf);
0582 
0583     return qla27xx_next_entry(ent);
0584 }
0585 
0586 static struct qla27xx_fwdt_entry *
0587 qla27xx_fwdt_entry_t272(struct scsi_qla_host *vha,
0588     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0589 {
0590     ulong dwords = le32_to_cpu(ent->t272.count);
0591     ulong start = le32_to_cpu(ent->t272.addr);
0592 
0593     ql_dbg(ql_dbg_misc, vha, 0xd210,
0594         "%s: rdremram [%lx]\n", __func__, *len);
0595     if (buf) {
0596         ql_dbg(ql_dbg_misc, vha, 0xd02c,
0597             "%s: @%lx -> (%lx dwords)\n", __func__, start, dwords);
0598         buf += *len;
0599         qla27xx_dump_mpi_ram(vha->hw, start, buf, dwords, &buf);
0600     }
0601     *len += dwords * sizeof(uint32_t);
0602 
0603     return qla27xx_next_entry(ent);
0604 }
0605 
0606 static struct qla27xx_fwdt_entry *
0607 qla27xx_fwdt_entry_t273(struct scsi_qla_host *vha,
0608     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0609 {
0610     ulong dwords = le32_to_cpu(ent->t273.count);
0611     ulong addr = le32_to_cpu(ent->t273.addr);
0612     uint32_t value;
0613 
0614     ql_dbg(ql_dbg_misc, vha, 0xd211,
0615         "%s: pcicfg [%lx]\n", __func__, *len);
0616     while (dwords--) {
0617         value = ~0;
0618         if (pci_read_config_dword(vha->hw->pdev, addr, &value))
0619             ql_dbg(ql_dbg_misc, vha, 0xd02d,
0620                 "%s: failed pcicfg read at %lx\n", __func__, addr);
0621         qla27xx_insert32(addr, buf, len);
0622         qla27xx_insert32(value, buf, len);
0623         addr += sizeof(uint32_t);
0624     }
0625 
0626     return qla27xx_next_entry(ent);
0627 }
0628 
0629 static struct qla27xx_fwdt_entry *
0630 qla27xx_fwdt_entry_t274(struct scsi_qla_host *vha,
0631     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0632 {
0633     ulong type = ent->t274.queue_type;
0634     uint count = 0;
0635     uint i;
0636 
0637     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd212,
0638         "%s: getqsh(%lx) [%lx]\n", __func__, type, *len);
0639     if (type == T274_QUEUE_TYPE_REQ_SHAD) {
0640         for (i = 0; i < vha->hw->max_req_queues; i++) {
0641             struct req_que *req = vha->hw->req_q_map[i];
0642 
0643             if (req || !buf) {
0644                 qla27xx_insert16(i, buf, len);
0645                 qla27xx_insert16(1, buf, len);
0646                 qla27xx_insert32(req && req->out_ptr ?
0647                     *req->out_ptr : 0, buf, len);
0648                 count++;
0649             }
0650         }
0651     } else if (type == T274_QUEUE_TYPE_RSP_SHAD) {
0652         for (i = 0; i < vha->hw->max_rsp_queues; i++) {
0653             struct rsp_que *rsp = vha->hw->rsp_q_map[i];
0654 
0655             if (rsp || !buf) {
0656                 qla27xx_insert16(i, buf, len);
0657                 qla27xx_insert16(1, buf, len);
0658                 qla27xx_insert32(rsp && rsp->in_ptr ?
0659                     *rsp->in_ptr : 0, buf, len);
0660                 count++;
0661             }
0662         }
0663     } else if (QLA_TGT_MODE_ENABLED() &&
0664         ent->t274.queue_type == T274_QUEUE_TYPE_ATIO_SHAD) {
0665         struct qla_hw_data *ha = vha->hw;
0666         struct atio *atr = ha->tgt.atio_ring_ptr;
0667 
0668         if (atr || !buf) {
0669             qla27xx_insert16(0, buf, len);
0670             qla27xx_insert16(1, buf, len);
0671             qla27xx_insert32(ha->tgt.atio_q_in ?
0672                 readl(ha->tgt.atio_q_in) : 0, buf, len);
0673             count++;
0674         }
0675     } else {
0676         ql_dbg(ql_dbg_misc, vha, 0xd02f,
0677             "%s: unknown queue %lx\n", __func__, type);
0678         qla27xx_skip_entry(ent, buf);
0679     }
0680 
0681     if (buf) {
0682         if (count)
0683             ent->t274.num_queues = count;
0684         else
0685             qla27xx_skip_entry(ent, buf);
0686     }
0687 
0688     return qla27xx_next_entry(ent);
0689 }
0690 
0691 static struct qla27xx_fwdt_entry *
0692 qla27xx_fwdt_entry_t275(struct scsi_qla_host *vha,
0693     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0694 {
0695     ulong offset = offsetof(typeof(*ent), t275.buffer);
0696     ulong length = le32_to_cpu(ent->t275.length);
0697     ulong size = le32_to_cpu(ent->hdr.size);
0698     void *buffer = ent->t275.buffer;
0699 
0700     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd213,
0701         "%s: buffer(%lx) [%lx]\n", __func__, length, *len);
0702     if (!length) {
0703         ql_dbg(ql_dbg_misc, vha, 0xd020,
0704             "%s: buffer zero length\n", __func__);
0705         qla27xx_skip_entry(ent, buf);
0706         goto done;
0707     }
0708     if (offset + length > size) {
0709         length = size - offset;
0710         ql_dbg(ql_dbg_misc, vha, 0xd030,
0711             "%s: buffer overflow, truncate [%lx]\n", __func__, length);
0712         ent->t275.length = cpu_to_le32(length);
0713     }
0714 
0715     qla27xx_insertbuf(buffer, length, buf, len);
0716 done:
0717     return qla27xx_next_entry(ent);
0718 }
0719 
0720 static struct qla27xx_fwdt_entry *
0721 qla27xx_fwdt_entry_t276(struct scsi_qla_host *vha,
0722     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0723 {
0724     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd214,
0725         "%s: cond [%lx]\n", __func__, *len);
0726 
0727     if (buf) {
0728         ulong cond1 = le32_to_cpu(ent->t276.cond1);
0729         ulong cond2 = le32_to_cpu(ent->t276.cond2);
0730         uint type = vha->hw->pdev->device >> 4 & 0xf;
0731         uint func = vha->hw->port_no & 0x3;
0732 
0733         if (type != cond1 || func != cond2) {
0734             struct qla27xx_fwdt_template *tmp = buf;
0735 
0736             tmp->count--;
0737             ent = qla27xx_next_entry(ent);
0738             qla27xx_skip_entry(ent, buf);
0739         }
0740     }
0741 
0742     return qla27xx_next_entry(ent);
0743 }
0744 
0745 static struct qla27xx_fwdt_entry *
0746 qla27xx_fwdt_entry_t277(struct scsi_qla_host *vha,
0747     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0748 {
0749     ulong cmd_addr = le32_to_cpu(ent->t277.cmd_addr);
0750     ulong wr_cmd_data = le32_to_cpu(ent->t277.wr_cmd_data);
0751     ulong data_addr = le32_to_cpu(ent->t277.data_addr);
0752 
0753     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd215,
0754         "%s: rdpep [%lx]\n", __func__, *len);
0755     qla27xx_insert32(wr_cmd_data, buf, len);
0756     qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
0757     qla27xx_read_reg(ISPREG(vha), data_addr, buf, len);
0758 
0759     return qla27xx_next_entry(ent);
0760 }
0761 
0762 static struct qla27xx_fwdt_entry *
0763 qla27xx_fwdt_entry_t278(struct scsi_qla_host *vha,
0764     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0765 {
0766     ulong cmd_addr = le32_to_cpu(ent->t278.cmd_addr);
0767     ulong wr_cmd_data = le32_to_cpu(ent->t278.wr_cmd_data);
0768     ulong data_addr = le32_to_cpu(ent->t278.data_addr);
0769     ulong wr_data = le32_to_cpu(ent->t278.wr_data);
0770 
0771     ql_dbg(ql_dbg_misc + ql_dbg_verbose, vha, 0xd216,
0772         "%s: wrpep [%lx]\n", __func__, *len);
0773     qla27xx_write_reg(ISPREG(vha), data_addr, wr_data, buf);
0774     qla27xx_write_reg(ISPREG(vha), cmd_addr, wr_cmd_data, buf);
0775 
0776     return qla27xx_next_entry(ent);
0777 }
0778 
0779 static struct qla27xx_fwdt_entry *
0780 qla27xx_fwdt_entry_other(struct scsi_qla_host *vha,
0781     struct qla27xx_fwdt_entry *ent, void *buf, ulong *len)
0782 {
0783     ulong type = le32_to_cpu(ent->hdr.type);
0784 
0785     ql_dbg(ql_dbg_misc, vha, 0xd2ff,
0786         "%s: other %lx [%lx]\n", __func__, type, *len);
0787     qla27xx_skip_entry(ent, buf);
0788 
0789     return qla27xx_next_entry(ent);
0790 }
0791 
0792 static struct {
0793     uint type;
0794     typeof(qla27xx_fwdt_entry_other)(*call);
0795 } qla27xx_fwdt_entry_call[] = {
0796     { ENTRY_TYPE_NOP,       qla27xx_fwdt_entry_t0    },
0797     { ENTRY_TYPE_TMP_END,       qla27xx_fwdt_entry_t255  },
0798     { ENTRY_TYPE_RD_IOB_T1,     qla27xx_fwdt_entry_t256  },
0799     { ENTRY_TYPE_WR_IOB_T1,     qla27xx_fwdt_entry_t257  },
0800     { ENTRY_TYPE_RD_IOB_T2,     qla27xx_fwdt_entry_t258  },
0801     { ENTRY_TYPE_WR_IOB_T2,     qla27xx_fwdt_entry_t259  },
0802     { ENTRY_TYPE_RD_PCI,        qla27xx_fwdt_entry_t260  },
0803     { ENTRY_TYPE_WR_PCI,        qla27xx_fwdt_entry_t261  },
0804     { ENTRY_TYPE_RD_RAM,        qla27xx_fwdt_entry_t262  },
0805     { ENTRY_TYPE_GET_QUEUE,     qla27xx_fwdt_entry_t263  },
0806     { ENTRY_TYPE_GET_FCE,       qla27xx_fwdt_entry_t264  },
0807     { ENTRY_TYPE_PSE_RISC,      qla27xx_fwdt_entry_t265  },
0808     { ENTRY_TYPE_RST_RISC,      qla27xx_fwdt_entry_t266  },
0809     { ENTRY_TYPE_DIS_INTR,      qla27xx_fwdt_entry_t267  },
0810     { ENTRY_TYPE_GET_HBUF,      qla27xx_fwdt_entry_t268  },
0811     { ENTRY_TYPE_SCRATCH,       qla27xx_fwdt_entry_t269  },
0812     { ENTRY_TYPE_RDREMREG,      qla27xx_fwdt_entry_t270  },
0813     { ENTRY_TYPE_WRREMREG,      qla27xx_fwdt_entry_t271  },
0814     { ENTRY_TYPE_RDREMRAM,      qla27xx_fwdt_entry_t272  },
0815     { ENTRY_TYPE_PCICFG,        qla27xx_fwdt_entry_t273  },
0816     { ENTRY_TYPE_GET_SHADOW,    qla27xx_fwdt_entry_t274  },
0817     { ENTRY_TYPE_WRITE_BUF,     qla27xx_fwdt_entry_t275  },
0818     { ENTRY_TYPE_CONDITIONAL,   qla27xx_fwdt_entry_t276  },
0819     { ENTRY_TYPE_RDPEPREG,      qla27xx_fwdt_entry_t277  },
0820     { ENTRY_TYPE_WRPEPREG,      qla27xx_fwdt_entry_t278  },
0821     { -1,               qla27xx_fwdt_entry_other }
0822 };
0823 
0824 static inline
0825 typeof(qla27xx_fwdt_entry_call->call)(qla27xx_find_entry(uint type))
0826 {
0827     typeof(*qla27xx_fwdt_entry_call) *list = qla27xx_fwdt_entry_call;
0828 
0829     while (list->type < type)
0830         list++;
0831 
0832     if (list->type == type)
0833         return list->call;
0834     return qla27xx_fwdt_entry_other;
0835 }
0836 
0837 static void
0838 qla27xx_walk_template(struct scsi_qla_host *vha,
0839     struct qla27xx_fwdt_template *tmp, void *buf, ulong *len)
0840 {
0841     struct qla27xx_fwdt_entry *ent = (void *)tmp +
0842         le32_to_cpu(tmp->entry_offset);
0843     ulong type;
0844 
0845     tmp->count = le32_to_cpu(tmp->entry_count);
0846     ql_dbg(ql_dbg_misc, vha, 0xd01a,
0847         "%s: entry count %u\n", __func__, tmp->count);
0848     while (ent && tmp->count--) {
0849         type = le32_to_cpu(ent->hdr.type);
0850         ent = qla27xx_find_entry(type)(vha, ent, buf, len);
0851         if (!ent)
0852             break;
0853 
0854         if (ent == INVALID_ENTRY) {
0855             *len = 0;
0856             ql_dbg(ql_dbg_async, vha, 0xffff,
0857                 "Unable to capture FW dump");
0858             goto bailout;
0859         }
0860     }
0861 
0862     if (tmp->count)
0863         ql_dbg(ql_dbg_misc, vha, 0xd018,
0864             "%s: entry count residual=+%u\n", __func__, tmp->count);
0865 
0866     if (ent)
0867         ql_dbg(ql_dbg_misc, vha, 0xd019,
0868             "%s: missing end entry\n", __func__);
0869 
0870 bailout:
0871     cpu_to_le32s(&tmp->count);  /* endianize residual count */
0872 }
0873 
0874 static void
0875 qla27xx_time_stamp(struct qla27xx_fwdt_template *tmp)
0876 {
0877     tmp->capture_timestamp = cpu_to_le32(jiffies);
0878 }
0879 
0880 static void
0881 qla27xx_driver_info(struct qla27xx_fwdt_template *tmp)
0882 {
0883     uint8_t v[] = { 0, 0, 0, 0, 0, 0 };
0884 
0885     WARN_ON_ONCE(sscanf(qla2x00_version_str,
0886                 "%hhu.%hhu.%hhu.%hhu",
0887                 v + 0, v + 1, v + 2, v + 3) != 4);
0888 
0889     tmp->driver_info[0] = cpu_to_le32(
0890         v[3] << 24 | v[2] << 16 | v[1] << 8 | v[0]);
0891     tmp->driver_info[1] = cpu_to_le32(v[5] << 8 | v[4]);
0892     tmp->driver_info[2] = __constant_cpu_to_le32(0x12345678);
0893 }
0894 
0895 static void
0896 qla27xx_firmware_info(struct scsi_qla_host *vha,
0897     struct qla27xx_fwdt_template *tmp)
0898 {
0899     tmp->firmware_version[0] = cpu_to_le32(vha->hw->fw_major_version);
0900     tmp->firmware_version[1] = cpu_to_le32(vha->hw->fw_minor_version);
0901     tmp->firmware_version[2] = cpu_to_le32(vha->hw->fw_subminor_version);
0902     tmp->firmware_version[3] = cpu_to_le32(
0903         vha->hw->fw_attributes_h << 16 | vha->hw->fw_attributes);
0904     tmp->firmware_version[4] = cpu_to_le32(
0905       vha->hw->fw_attributes_ext[1] << 16 | vha->hw->fw_attributes_ext[0]);
0906 }
0907 
0908 static void
0909 ql27xx_edit_template(struct scsi_qla_host *vha,
0910     struct qla27xx_fwdt_template *tmp)
0911 {
0912     qla27xx_time_stamp(tmp);
0913     qla27xx_driver_info(tmp);
0914     qla27xx_firmware_info(vha, tmp);
0915 }
0916 
0917 static inline uint32_t
0918 qla27xx_template_checksum(void *p, ulong size)
0919 {
0920     __le32 *buf = p;
0921     uint64_t sum = 0;
0922 
0923     size /= sizeof(*buf);
0924 
0925     for ( ; size--; buf++)
0926         sum += le32_to_cpu(*buf);
0927 
0928     sum = (sum & 0xffffffff) + (sum >> 32);
0929 
0930     return ~sum;
0931 }
0932 
0933 static inline int
0934 qla27xx_verify_template_checksum(struct qla27xx_fwdt_template *tmp)
0935 {
0936     return qla27xx_template_checksum(tmp,
0937         le32_to_cpu(tmp->template_size)) == 0;
0938 }
0939 
0940 static inline int
0941 qla27xx_verify_template_header(struct qla27xx_fwdt_template *tmp)
0942 {
0943     return le32_to_cpu(tmp->template_type) == TEMPLATE_TYPE_FWDUMP;
0944 }
0945 
0946 static ulong
0947 qla27xx_execute_fwdt_template(struct scsi_qla_host *vha,
0948     struct qla27xx_fwdt_template *tmp, void *buf)
0949 {
0950     ulong len = 0;
0951 
0952     if (qla27xx_fwdt_template_valid(tmp)) {
0953         len = le32_to_cpu(tmp->template_size);
0954         tmp = memcpy(buf, tmp, len);
0955         ql27xx_edit_template(vha, tmp);
0956         qla27xx_walk_template(vha, tmp, buf, &len);
0957     }
0958 
0959     return len;
0960 }
0961 
0962 ulong
0963 qla27xx_fwdt_calculate_dump_size(struct scsi_qla_host *vha, void *p)
0964 {
0965     struct qla27xx_fwdt_template *tmp = p;
0966     ulong len = 0;
0967 
0968     if (qla27xx_fwdt_template_valid(tmp)) {
0969         len = le32_to_cpu(tmp->template_size);
0970         qla27xx_walk_template(vha, tmp, NULL, &len);
0971     }
0972 
0973     return len;
0974 }
0975 
0976 ulong
0977 qla27xx_fwdt_template_size(void *p)
0978 {
0979     struct qla27xx_fwdt_template *tmp = p;
0980 
0981     return le32_to_cpu(tmp->template_size);
0982 }
0983 
0984 int
0985 qla27xx_fwdt_template_valid(void *p)
0986 {
0987     struct qla27xx_fwdt_template *tmp = p;
0988 
0989     if (!qla27xx_verify_template_header(tmp)) {
0990         ql_log(ql_log_warn, NULL, 0xd01c,
0991             "%s: template type %x\n", __func__,
0992             le32_to_cpu(tmp->template_type));
0993         return false;
0994     }
0995 
0996     if (!qla27xx_verify_template_checksum(tmp)) {
0997         ql_log(ql_log_warn, NULL, 0xd01d,
0998             "%s: failed template checksum\n", __func__);
0999         return false;
1000     }
1001 
1002     return true;
1003 }
1004 
1005 void
1006 qla27xx_mpi_fwdump(scsi_qla_host_t *vha, int hardware_locked)
1007 {
1008     ulong flags = 0;
1009 
1010     if (!hardware_locked)
1011         spin_lock_irqsave(&vha->hw->hardware_lock, flags);
1012     if (!vha->hw->mpi_fw_dump) {
1013         ql_log(ql_log_warn, vha, 0x02f3, "-> mpi_fwdump no buffer\n");
1014     } else {
1015         struct fwdt *fwdt = &vha->hw->fwdt[1];
1016         ulong len;
1017         void *buf = vha->hw->mpi_fw_dump;
1018         bool walk_template_only = false;
1019 
1020         if (vha->hw->mpi_fw_dumped) {
1021             /* Use the spare area for any further dumps. */
1022             buf += fwdt->dump_size;
1023             walk_template_only = true;
1024             ql_log(ql_log_warn, vha, 0x02f4,
1025                    "-> MPI firmware already dumped -- dump saving to temporary buffer %p.\n",
1026                    buf);
1027         }
1028 
1029         ql_log(ql_log_warn, vha, 0x02f5, "-> fwdt1 running...\n");
1030         if (!fwdt->template) {
1031             ql_log(ql_log_warn, vha, 0x02f6,
1032                    "-> fwdt1 no template\n");
1033             goto bailout;
1034         }
1035         len = qla27xx_execute_fwdt_template(vha, fwdt->template, buf);
1036         if (len == 0) {
1037             goto bailout;
1038         } else if (len != fwdt->dump_size) {
1039             ql_log(ql_log_warn, vha, 0x02f7,
1040                    "-> fwdt1 fwdump residual=%+ld\n",
1041                    fwdt->dump_size - len);
1042         }
1043         vha->hw->stat.num_mpi_reset++;
1044         if (walk_template_only)
1045             goto bailout;
1046 
1047         vha->hw->mpi_fw_dump_len = len;
1048         vha->hw->mpi_fw_dumped = 1;
1049 
1050         ql_log(ql_log_warn, vha, 0x02f8,
1051                "-> MPI firmware dump saved to buffer (%lu/%p)\n",
1052                vha->host_no, vha->hw->mpi_fw_dump);
1053         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
1054     }
1055 
1056 bailout:
1057     if (!hardware_locked)
1058         spin_unlock_irqrestore(&vha->hw->hardware_lock, flags);
1059 }
1060 
1061 void
1062 qla27xx_fwdump(scsi_qla_host_t *vha)
1063 {
1064     lockdep_assert_held(&vha->hw->hardware_lock);
1065 
1066     if (!vha->hw->fw_dump) {
1067         ql_log(ql_log_warn, vha, 0xd01e, "-> fwdump no buffer\n");
1068     } else if (vha->hw->fw_dumped) {
1069         ql_log(ql_log_warn, vha, 0xd01f,
1070             "-> Firmware already dumped (%p) -- ignoring request\n",
1071             vha->hw->fw_dump);
1072     } else {
1073         struct fwdt *fwdt = vha->hw->fwdt;
1074         ulong len;
1075         void *buf = vha->hw->fw_dump;
1076 
1077         ql_log(ql_log_warn, vha, 0xd011, "-> fwdt0 running...\n");
1078         if (!fwdt->template) {
1079             ql_log(ql_log_warn, vha, 0xd012,
1080                    "-> fwdt0 no template\n");
1081             return;
1082         }
1083         len = qla27xx_execute_fwdt_template(vha, fwdt->template, buf);
1084         if (len == 0) {
1085             return;
1086         } else if (len != fwdt->dump_size) {
1087             ql_log(ql_log_warn, vha, 0xd013,
1088                    "-> fwdt0 fwdump residual=%+ld\n",
1089                 fwdt->dump_size - len);
1090         }
1091 
1092         vha->hw->fw_dump_len = len;
1093         vha->hw->fw_dumped = true;
1094 
1095         ql_log(ql_log_warn, vha, 0xd015,
1096             "-> Firmware dump saved to buffer (%lu/%p) <%lx>\n",
1097             vha->host_no, vha->hw->fw_dump, vha->hw->fw_dump_cap_flags);
1098         qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
1099     }
1100 }
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