scsi/qla2xxx/qla_nx2.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * QLogic Fibre Channel HBA Driver
0004  * Copyright (c)  2003-2014 QLogic Corporation
0005  */
0006
0007 #ifndef __QLA_NX2_H
0008 #define __QLA_NX2_H
0009
0010 #define QSNT_ACK_TOV                30
0011 #define INTENT_TO_RECOVER           0x01
0012 #define PROCEED_TO_RECOVER          0x02
0013 #define IDC_LOCK_RECOVERY_OWNER_MASK        0x3C
0014 #define IDC_LOCK_RECOVERY_STATE_MASK        0x3
0015 #define IDC_LOCK_RECOVERY_STATE_SHIFT_BITS  2
0016
0017 #define QLA8044_DRV_LOCK_MSLEEP     200
0018 #define QLA8044_ADDR_DDR_NET        (0x0000000000000000ULL)
0019 #define QLA8044_ADDR_DDR_NET_MAX    (0x000000000fffffffULL)
0020
0021 #define MD_MIU_TEST_AGT_WRDATA_LO       0x410000A0
0022 #define MD_MIU_TEST_AGT_WRDATA_HI       0x410000A4
0023 #define MD_MIU_TEST_AGT_WRDATA_ULO      0x410000B0
0024 #define MD_MIU_TEST_AGT_WRDATA_UHI      0x410000B4
0025
0026 /* MIU_TEST_AGT_CTRL flags. work for SIU as well */
0027 #define MIU_TA_CTL_WRITE_ENABLE (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE)
0028 #define MIU_TA_CTL_WRITE_START  (MIU_TA_CTL_WRITE | MIU_TA_CTL_ENABLE | \
0029                  MIU_TA_CTL_START)
0030 #define MIU_TA_CTL_START_ENABLE (MIU_TA_CTL_START | MIU_TA_CTL_ENABLE)
0031
0032 /* Imbus address bit used to indicate a host address. This bit is
0033  * eliminated by the pcie bar and bar select before presentation
0034  * over pcie. */
0035 /* host memory via IMBUS */
0036 #define QLA8044_P2_ADDR_PCIE    (0x0000000800000000ULL)
0037 #define QLA8044_P3_ADDR_PCIE    (0x0000008000000000ULL)
0038 #define QLA8044_ADDR_PCIE_MAX   (0x0000000FFFFFFFFFULL)
0039 #define QLA8044_ADDR_OCM0   (0x0000000200000000ULL)
0040 #define QLA8044_ADDR_OCM0_MAX   (0x00000002000fffffULL)
0041 #define QLA8044_ADDR_OCM1   (0x0000000200400000ULL)
0042 #define QLA8044_ADDR_OCM1_MAX   (0x00000002004fffffULL)
0043 #define QLA8044_ADDR_QDR_NET    (0x0000000300000000ULL)
0044 #define QLA8044_P2_ADDR_QDR_NET_MAX (0x00000003001fffffULL)
0045 #define QLA8044_P3_ADDR_QDR_NET_MAX (0x0000000303ffffffULL)
0046 #define QLA8044_ADDR_QDR_NET_MAX    (0x0000000307ffffffULL)
0047 #define QLA8044_PCI_CRBSPACE        ((unsigned long)0x06000000)
0048 #define QLA8044_PCI_DIRECT_CRB      ((unsigned long)0x04400000)
0049 #define QLA8044_PCI_CAMQM       ((unsigned long)0x04800000)
0050 #define QLA8044_PCI_CAMQM_MAX       ((unsigned long)0x04ffffff)
0051 #define QLA8044_PCI_DDR_NET     ((unsigned long)0x00000000)
0052 #define QLA8044_PCI_QDR_NET     ((unsigned long)0x04000000)
0053 #define QLA8044_PCI_QDR_NET_MAX     ((unsigned long)0x043fffff)
0054
0055 /*  PCI Windowing for DDR regions.  */
0056 static inline bool addr_in_range(u64 addr, u64 low, u64 high)
0057 {
0058     return addr <= high && addr >= low;
0059 }
0060
0061 /* Indirectly Mapped Registers */
0062 #define QLA8044_FLASH_SPI_STATUS    0x2808E010
0063 #define QLA8044_FLASH_SPI_CONTROL   0x2808E014
0064 #define QLA8044_FLASH_STATUS        0x42100004
0065 #define QLA8044_FLASH_CONTROL       0x42110004
0066 #define QLA8044_FLASH_ADDR      0x42110008
0067 #define QLA8044_FLASH_WRDATA        0x4211000C
0068 #define QLA8044_FLASH_RDDATA        0x42110018
0069 #define QLA8044_FLASH_DIRECT_WINDOW 0x42110030
0070 #define QLA8044_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA))
0071
0072 /* Flash access regs */
0073 #define QLA8044_FLASH_LOCK      0x3850
0074 #define QLA8044_FLASH_UNLOCK        0x3854
0075 #define QLA8044_FLASH_LOCK_ID       0x3500
0076
0077 /* Driver Lock regs */
0078 #define QLA8044_DRV_LOCK        0x3868
0079 #define QLA8044_DRV_UNLOCK      0x386C
0080 #define QLA8044_DRV_LOCK_ID     0x3504
0081 #define QLA8044_DRV_LOCKRECOVERY    0x379C
0082
0083 /* IDC version */
0084 #define QLA8044_IDC_VER_MAJ_VALUE       0x1
0085 #define QLA8044_IDC_VER_MIN_VALUE       0x0
0086
0087 /* IDC Registers : Driver Coexistence Defines */
0088 #define QLA8044_CRB_IDC_VER_MAJOR   0x3780
0089 #define QLA8044_CRB_IDC_VER_MINOR   0x3798
0090 #define QLA8044_IDC_DRV_AUDIT       0x3794
0091 #define QLA8044_SRE_SHIM_CONTROL    0x0D200284
0092 #define QLA8044_PORT0_RXB_PAUSE_THRS    0x0B2003A4
0093 #define QLA8044_PORT1_RXB_PAUSE_THRS    0x0B2013A4
0094 #define QLA8044_PORT0_RXB_TC_MAX_CELL   0x0B200388
0095 #define QLA8044_PORT1_RXB_TC_MAX_CELL   0x0B201388
0096 #define QLA8044_PORT0_RXB_TC_STATS  0x0B20039C
0097 #define QLA8044_PORT1_RXB_TC_STATS  0x0B20139C
0098 #define QLA8044_PORT2_IFB_PAUSE_THRS    0x0B200704
0099 #define QLA8044_PORT3_IFB_PAUSE_THRS    0x0B201704
0100
0101 /* set value to pause threshold value */
0102 #define QLA8044_SET_PAUSE_VAL       0x0
0103 #define QLA8044_SET_TC_MAX_CELL_VAL 0x03FF03FF
0104 #define QLA8044_PEG_HALT_STATUS1    0x34A8
0105 #define QLA8044_PEG_HALT_STATUS2    0x34AC
0106 #define QLA8044_PEG_ALIVE_COUNTER   0x34B0 /* FW_HEARTBEAT */
0107 #define QLA8044_FW_CAPABILITIES     0x3528
0108 #define QLA8044_CRB_DRV_ACTIVE      0x3788 /* IDC_DRV_PRESENCE */
0109 #define QLA8044_CRB_DEV_STATE       0x3784 /* IDC_DEV_STATE */
0110 #define QLA8044_CRB_DRV_STATE       0x378C /* IDC_DRV_ACK */
0111 #define QLA8044_CRB_DRV_SCRATCH     0x3548
0112 #define QLA8044_CRB_DEV_PART_INFO1  0x37E0
0113 #define QLA8044_CRB_DEV_PART_INFO2  0x37E4
0114 #define QLA8044_FW_VER_MAJOR        0x3550
0115 #define QLA8044_FW_VER_MINOR        0x3554
0116 #define QLA8044_FW_VER_SUB      0x3558
0117 #define QLA8044_NPAR_STATE      0x359C
0118 #define QLA8044_FW_IMAGE_VALID      0x35FC
0119 #define QLA8044_CMDPEG_STATE        0x3650
0120 #define QLA8044_ASIC_TEMP       0x37B4
0121 #define QLA8044_FW_API          0x356C
0122 #define QLA8044_DRV_OP_MODE     0x3570
0123 #define QLA8044_CRB_WIN_BASE        0x3800
0124 #define QLA8044_CRB_WIN_FUNC(f)     (QLA8044_CRB_WIN_BASE+((f)*4))
0125 #define QLA8044_SEM_LOCK_BASE       0x3840
0126 #define QLA8044_SEM_UNLOCK_BASE     0x3844
0127 #define QLA8044_SEM_LOCK_FUNC(f)    (QLA8044_SEM_LOCK_BASE+((f)*8))
0128 #define QLA8044_SEM_UNLOCK_FUNC(f)  (QLA8044_SEM_UNLOCK_BASE+((f)*8))
0129 #define QLA8044_LINK_STATE(f)       (0x3698+((f) > 7 ? 4 : 0))
0130 #define QLA8044_LINK_SPEED(f)       (0x36E0+(((f) >> 2) * 4))
0131 #define QLA8044_MAX_LINK_SPEED(f)       (0x36F0+(((f) / 4) * 4))
0132 #define QLA8044_LINK_SPEED_FACTOR   10
0133 #define QLA8044_FUN7_ACTIVE_INDEX   0x80
0134
0135 /* FLASH API Defines */
0136 #define QLA8044_FLASH_MAX_WAIT_USEC 100
0137 #define QLA8044_FLASH_LOCK_TIMEOUT  10000
0138 #define QLA8044_FLASH_SECTOR_SIZE   65536
0139 #define QLA8044_DRV_LOCK_TIMEOUT    2000
0140 #define QLA8044_FLASH_SECTOR_ERASE_CMD  0xdeadbeef
0141 #define QLA8044_FLASH_WRITE_CMD     0xdacdacda
0142 #define QLA8044_FLASH_BUFFER_WRITE_CMD  0xcadcadca
0143 #define QLA8044_FLASH_READ_RETRY_COUNT  2000
0144 #define QLA8044_FLASH_STATUS_READY  0x6
0145 #define QLA8044_FLASH_BUFFER_WRITE_MIN  2
0146 #define QLA8044_FLASH_BUFFER_WRITE_MAX  64
0147 #define QLA8044_FLASH_STATUS_REG_POLL_DELAY 1
0148 #define QLA8044_ERASE_MODE      1
0149 #define QLA8044_WRITE_MODE      2
0150 #define QLA8044_DWORD_WRITE_MODE    3
0151 #define QLA8044_GLOBAL_RESET        0x38CC
0152 #define QLA8044_WILDCARD        0x38F0
0153 #define QLA8044_INFORMANT       0x38FC
0154 #define QLA8044_HOST_MBX_CTRL       0x3038
0155 #define QLA8044_FW_MBX_CTRL     0x303C
0156 #define QLA8044_BOOTLOADER_ADDR     0x355C
0157 #define QLA8044_BOOTLOADER_SIZE     0x3560
0158 #define QLA8044_FW_IMAGE_ADDR       0x3564
0159 #define QLA8044_MBX_INTR_ENABLE     0x1000
0160 #define QLA8044_MBX_INTR_MASK       0x1200
0161
0162 /* IDC Control Register bit defines */
0163 #define DONTRESET_BIT0      0x1
0164 #define GRACEFUL_RESET_BIT1 0x2
0165
0166 /* ISP8044 PEG_HALT_STATUS1 bits */
0167 #define QLA8044_HALT_STATUS_INFORMATIONAL (0x1 << 29)
0168 #define QLA8044_HALT_STATUS_FW_RESET      (0x2 << 29)
0169 #define QLA8044_HALT_STATUS_UNRECOVERABLE (0x4 << 29)
0170
0171 /* Firmware image definitions */
0172 #define QLA8044_BOOTLOADER_FLASH_ADDR   0x10000
0173 #define QLA8044_BOOT_FROM_FLASH     0
0174 #define QLA8044_IDC_PARAM_ADDR      0x3e8020
0175
0176 /* FLASH related definitions */
0177 #define QLA8044_OPTROM_BURST_SIZE       0x100
0178 #define QLA8044_MAX_OPTROM_BURST_DWORDS     (QLA8044_OPTROM_BURST_SIZE / 4)
0179 #define QLA8044_MIN_OPTROM_BURST_DWORDS     2
0180 #define QLA8044_SECTOR_SIZE         (64 * 1024)
0181
0182 #define QLA8044_FLASH_SPI_CTL           0x4
0183 #define QLA8044_FLASH_FIRST_TEMP_VAL        0x00800000
0184 #define QLA8044_FLASH_SECOND_TEMP_VAL       0x00800001
0185 #define QLA8044_FLASH_FIRST_MS_PATTERN      0x43
0186 #define QLA8044_FLASH_SECOND_MS_PATTERN     0x7F
0187 #define QLA8044_FLASH_LAST_MS_PATTERN       0x7D
0188 #define QLA8044_FLASH_STATUS_WRITE_DEF_SIG  0xFD0100
0189 #define QLA8044_FLASH_SECOND_ERASE_MS_VAL   0x5
0190 #define QLA8044_FLASH_ERASE_SIG         0xFD0300
0191 #define QLA8044_FLASH_LAST_ERASE_MS_VAL     0x3D
0192
0193 /* Reset template definitions */
0194 #define QLA8044_MAX_RESET_SEQ_ENTRIES   16
0195 #define QLA8044_RESTART_TEMPLATE_SIZE   0x2000
0196 #define QLA8044_RESET_TEMPLATE_ADDR 0x4F0000
0197 #define QLA8044_RESET_SEQ_VERSION   0x0101
0198
0199 /* Reset template entry opcodes */
0200 #define OPCODE_NOP          0x0000
0201 #define OPCODE_WRITE_LIST       0x0001
0202 #define OPCODE_READ_WRITE_LIST      0x0002
0203 #define OPCODE_POLL_LIST        0x0004
0204 #define OPCODE_POLL_WRITE_LIST      0x0008
0205 #define OPCODE_READ_MODIFY_WRITE    0x0010
0206 #define OPCODE_SEQ_PAUSE        0x0020
0207 #define OPCODE_SEQ_END          0x0040
0208 #define OPCODE_TMPL_END         0x0080
0209 #define OPCODE_POLL_READ_LIST       0x0100
0210
0211 /* Template Header */
0212 #define RESET_TMPLT_HDR_SIGNATURE   0xCAFE
0213 #define QLA8044_IDC_DRV_CTRL            0x3790
0214 #define AF_8044_NO_FW_DUMP              27 /* 0x08000000 */
0215
0216 #define MINIDUMP_SIZE_36K       36864
0217
0218 struct qla8044_reset_template_hdr {
0219     uint16_t    version;
0220     uint16_t    signature;
0221     uint16_t    size;
0222     uint16_t    entries;
0223     uint16_t    hdr_size;
0224     uint16_t    checksum;
0225     uint16_t    init_seq_offset;
0226     uint16_t    start_seq_offset;
0227 } __packed;
0228
0229 /* Common Entry Header. */
0230 struct qla8044_reset_entry_hdr {
0231     uint16_t cmd;
0232     uint16_t size;
0233     uint16_t count;
0234     uint16_t delay;
0235 } __packed;
0236
0237 /* Generic poll entry type. */
0238 struct qla8044_poll {
0239     uint32_t  test_mask;
0240     uint32_t  test_value;
0241 } __packed;
0242
0243 /* Read modify write entry type. */
0244 struct qla8044_rmw {
0245     uint32_t test_mask;
0246     uint32_t xor_value;
0247     uint32_t  or_value;
0248     uint8_t shl;
0249     uint8_t shr;
0250     uint8_t index_a;
0251     uint8_t rsvd;
0252 } __packed;
0253
0254 /* Generic Entry Item with 2 DWords. */
0255 struct qla8044_entry {
0256     uint32_t arg1;
0257     uint32_t arg2;
0258 } __packed;
0259
0260 /* Generic Entry Item with 4 DWords.*/
0261 struct qla8044_quad_entry {
0262     uint32_t dr_addr;
0263     uint32_t dr_value;
0264     uint32_t ar_addr;
0265     uint32_t ar_value;
0266 } __packed;
0267
0268 struct qla8044_reset_template {
0269     int seq_index;
0270     int seq_error;
0271     int array_index;
0272     uint32_t array[QLA8044_MAX_RESET_SEQ_ENTRIES];
0273     uint8_t *buff;
0274     uint8_t *stop_offset;
0275     uint8_t *start_offset;
0276     uint8_t *init_offset;
0277     struct qla8044_reset_template_hdr *hdr;
0278     uint8_t seq_end;
0279     uint8_t template_end;
0280 };
0281
0282 /* Driver_code is for driver to write some info about the entry
0283  * currently not used.
0284  */
0285 struct qla8044_minidump_entry_hdr {
0286     uint32_t entry_type;
0287     uint32_t entry_size;
0288     uint32_t entry_capture_size;
0289     struct {
0290         uint8_t entry_capture_mask;
0291         uint8_t entry_code;
0292         uint8_t driver_code;
0293         uint8_t driver_flags;
0294     } d_ctrl;
0295 } __packed;
0296
0297 /*  Read CRB entry header */
0298 struct qla8044_minidump_entry_crb {
0299     struct qla8044_minidump_entry_hdr h;
0300     uint32_t addr;
0301     struct {
0302         uint8_t addr_stride;
0303         uint8_t state_index_a;
0304         uint16_t poll_timeout;
0305     } crb_strd;
0306     uint32_t data_size;
0307     uint32_t op_count;
0308
0309     struct {
0310         uint8_t opcode;
0311         uint8_t state_index_v;
0312         uint8_t shl;
0313         uint8_t shr;
0314     } crb_ctrl;
0315
0316     uint32_t value_1;
0317     uint32_t value_2;
0318     uint32_t value_3;
0319 } __packed;
0320
0321 struct qla8044_minidump_entry_cache {
0322     struct qla8044_minidump_entry_hdr h;
0323     uint32_t tag_reg_addr;
0324     struct {
0325         uint16_t tag_value_stride;
0326         uint16_t init_tag_value;
0327     } addr_ctrl;
0328     uint32_t data_size;
0329     uint32_t op_count;
0330     uint32_t control_addr;
0331     struct {
0332         uint16_t write_value;
0333         uint8_t poll_mask;
0334         uint8_t poll_wait;
0335     } cache_ctrl;
0336     uint32_t read_addr;
0337     struct {
0338         uint8_t read_addr_stride;
0339         uint8_t read_addr_cnt;
0340         uint16_t rsvd_1;
0341     } read_ctrl;
0342 } __packed;
0343
0344 /* Read OCM */
0345 struct qla8044_minidump_entry_rdocm {
0346     struct qla8044_minidump_entry_hdr h;
0347     uint32_t rsvd_0;
0348     uint32_t rsvd_1;
0349     uint32_t data_size;
0350     uint32_t op_count;
0351     uint32_t rsvd_2;
0352     uint32_t rsvd_3;
0353     uint32_t read_addr;
0354     uint32_t read_addr_stride;
0355 } __packed;
0356
0357 /* Read Memory */
0358 struct qla8044_minidump_entry_rdmem {
0359     struct qla8044_minidump_entry_hdr h;
0360     uint32_t rsvd[6];
0361     uint32_t read_addr;
0362     uint32_t read_data_size;
0363 };
0364
0365 /* Read Memory: For Pex-DMA */
0366 struct qla8044_minidump_entry_rdmem_pex_dma {
0367     struct qla8044_minidump_entry_hdr h;
0368     uint32_t desc_card_addr;
0369     uint16_t dma_desc_cmd;
0370     uint8_t rsvd[2];
0371     uint32_t start_dma_cmd;
0372     uint8_t rsvd2[12];
0373     uint32_t read_addr;
0374     uint32_t read_data_size;
0375 } __packed;
0376
0377 /* Read ROM */
0378 struct qla8044_minidump_entry_rdrom {
0379     struct qla8044_minidump_entry_hdr h;
0380     uint32_t rsvd[6];
0381     uint32_t read_addr;
0382     uint32_t read_data_size;
0383 } __packed;
0384
0385 /* Mux entry */
0386 struct qla8044_minidump_entry_mux {
0387     struct qla8044_minidump_entry_hdr h;
0388     uint32_t select_addr;
0389     uint32_t rsvd_0;
0390     uint32_t data_size;
0391     uint32_t op_count;
0392     uint32_t select_value;
0393     uint32_t select_value_stride;
0394     uint32_t read_addr;
0395     uint32_t rsvd_1;
0396 } __packed;
0397
0398 /* Queue entry */
0399 struct qla8044_minidump_entry_queue {
0400     struct qla8044_minidump_entry_hdr h;
0401     uint32_t select_addr;
0402     struct {
0403         uint16_t queue_id_stride;
0404         uint16_t rsvd_0;
0405     } q_strd;
0406     uint32_t data_size;
0407     uint32_t op_count;
0408     uint32_t rsvd_1;
0409     uint32_t rsvd_2;
0410     uint32_t read_addr;
0411     struct {
0412         uint8_t read_addr_stride;
0413         uint8_t read_addr_cnt;
0414         uint16_t rsvd_3;
0415     } rd_strd;
0416 } __packed;
0417
0418 /* POLLRD Entry */
0419 struct qla8044_minidump_entry_pollrd {
0420     struct qla8044_minidump_entry_hdr h;
0421     uint32_t select_addr;
0422     uint32_t read_addr;
0423     uint32_t select_value;
0424     uint16_t select_value_stride;
0425     uint16_t op_count;
0426     uint32_t poll_wait;
0427     uint32_t poll_mask;
0428     uint32_t data_size;
0429     uint32_t rsvd_1;
0430 } __packed;
0431
0432 struct qla8044_minidump_entry_rddfe {
0433     struct qla8044_minidump_entry_hdr h;
0434     uint32_t addr_1;
0435     uint32_t value;
0436     uint8_t stride;
0437     uint8_t stride2;
0438     uint16_t count;
0439     uint32_t poll;
0440     uint32_t mask;
0441     uint32_t modify_mask;
0442     uint32_t data_size;
0443     uint32_t rsvd;
0444
0445 } __packed;
0446
0447 struct qla8044_minidump_entry_rdmdio {
0448     struct qla8044_minidump_entry_hdr h;
0449
0450     uint32_t addr_1;
0451     uint32_t addr_2;
0452     uint32_t value_1;
0453     uint8_t stride_1;
0454     uint8_t stride_2;
0455     uint16_t count;
0456     uint32_t poll;
0457     uint32_t mask;
0458     uint32_t value_2;
0459     uint32_t data_size;
0460
0461 } __packed;
0462
0463 struct qla8044_minidump_entry_pollwr {
0464     struct qla8044_minidump_entry_hdr h;
0465     uint32_t addr_1;
0466     uint32_t addr_2;
0467     uint32_t value_1;
0468     uint32_t value_2;
0469     uint32_t poll;
0470     uint32_t mask;
0471     uint32_t data_size;
0472     uint32_t rsvd;
0473
0474 }  __packed;
0475
0476 /* RDMUX2 Entry */
0477 struct qla8044_minidump_entry_rdmux2 {
0478     struct qla8044_minidump_entry_hdr h;
0479     uint32_t select_addr_1;
0480     uint32_t select_addr_2;
0481     uint32_t select_value_1;
0482     uint32_t select_value_2;
0483     uint32_t op_count;
0484     uint32_t select_value_mask;
0485     uint32_t read_addr;
0486     uint8_t select_value_stride;
0487     uint8_t data_size;
0488     uint8_t rsvd[2];
0489 } __packed;
0490
0491 /* POLLRDMWR Entry */
0492 struct qla8044_minidump_entry_pollrdmwr {
0493     struct qla8044_minidump_entry_hdr h;
0494     uint32_t addr_1;
0495     uint32_t addr_2;
0496     uint32_t value_1;
0497     uint32_t value_2;
0498     uint32_t poll_wait;
0499     uint32_t poll_mask;
0500     uint32_t modify_mask;
0501     uint32_t data_size;
0502 } __packed;
0503
0504 /* IDC additional information */
0505 struct qla8044_idc_information {
0506     uint32_t request_desc;  /* IDC request descriptor */
0507     uint32_t info1; /* IDC additional info */
0508     uint32_t info2; /* IDC additional info */
0509     uint32_t info3; /* IDC additional info */
0510 } __packed;
0511
0512 enum qla_regs {
0513     QLA8044_PEG_HALT_STATUS1_INDEX = 0,
0514     QLA8044_PEG_HALT_STATUS2_INDEX,
0515     QLA8044_PEG_ALIVE_COUNTER_INDEX,
0516     QLA8044_CRB_DRV_ACTIVE_INDEX,
0517     QLA8044_CRB_DEV_STATE_INDEX,
0518     QLA8044_CRB_DRV_STATE_INDEX,
0519     QLA8044_CRB_DRV_SCRATCH_INDEX,
0520     QLA8044_CRB_DEV_PART_INFO_INDEX,
0521     QLA8044_CRB_DRV_IDC_VERSION_INDEX,
0522     QLA8044_FW_VERSION_MAJOR_INDEX,
0523     QLA8044_FW_VERSION_MINOR_INDEX,
0524     QLA8044_FW_VERSION_SUB_INDEX,
0525     QLA8044_CRB_CMDPEG_STATE_INDEX,
0526     QLA8044_CRB_TEMP_STATE_INDEX,
0527 } __packed;
0528
0529 #define CRB_REG_INDEX_MAX   14
0530 #define CRB_CMDPEG_CHECK_RETRY_COUNT    60
0531 #define CRB_CMDPEG_CHECK_DELAY          500
0532
0533 /* MiniDump Structures */
0534
0535 /* Driver_code is for driver to write some info about the entry
0536  * currently not used.
0537  */
0538 #define QLA8044_SS_OCM_WNDREG_INDEX             3
0539 #define QLA8044_DBG_STATE_ARRAY_LEN             16
0540 #define QLA8044_DBG_CAP_SIZE_ARRAY_LEN          8
0541 #define QLA8044_DBG_RSVD_ARRAY_LEN              8
0542 #define QLA8044_DBG_OCM_WNDREG_ARRAY_LEN        16
0543 #define QLA8044_SS_PCI_INDEX                    0
0544 #define QLA8044_RDDFE          38
0545 #define QLA8044_RDMDIO         39
0546 #define QLA8044_POLLWR         40
0547
0548 struct qla8044_minidump_template_hdr {
0549     uint32_t entry_type;
0550     uint32_t first_entry_offset;
0551     uint32_t size_of_template;
0552     uint32_t capture_debug_level;
0553     uint32_t num_of_entries;
0554     uint32_t version;
0555     uint32_t driver_timestamp;
0556     uint32_t checksum;
0557
0558     uint32_t driver_capture_mask;
0559     uint32_t driver_info_word2;
0560     uint32_t driver_info_word3;
0561     uint32_t driver_info_word4;
0562
0563     uint32_t saved_state_array[QLA8044_DBG_STATE_ARRAY_LEN];
0564     uint32_t capture_size_array[QLA8044_DBG_CAP_SIZE_ARRAY_LEN];
0565     uint32_t ocm_window_reg[QLA8044_DBG_OCM_WNDREG_ARRAY_LEN];
0566 };
0567
0568 struct qla8044_pex_dma_descriptor {
0569     struct {
0570         uint32_t read_data_size; /* 0-23: size, 24-31: rsvd */
0571         uint8_t rsvd[2];
0572         uint16_t dma_desc_cmd;
0573     } cmd;
0574     uint64_t src_addr;
0575     uint64_t dma_bus_addr; /*0-3: desc-cmd, 4-7: pci-func, 8-15: desc-cmd*/
0576     uint8_t rsvd[24];
0577 } __packed;
0578
0579 #endif