scsi/qla2xxx/qla_mr.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * QLogic Fibre Channel HBA Driver
0004  * Copyright (c)  2003-2014 QLogic Corporation
0005  */
0006 #ifndef __QLA_MR_H
0007 #define __QLA_MR_H
0008
0009 #include "qla_dsd.h"
0010
0011 /*
0012  * The PCI VendorID and DeviceID for our board.
0013  */
0014 #define PCI_DEVICE_ID_QLOGIC_ISPF001        0xF001
0015
0016 /* FX00 specific definitions */
0017
0018 #define FX00_COMMAND_TYPE_7 0x07    /* Command Type 7 entry for 7XXX */
0019 struct cmd_type_7_fx00 {
0020     uint8_t entry_type;     /* Entry type. */
0021     uint8_t entry_count;        /* Entry count. */
0022     uint8_t sys_define;     /* System defined. */
0023     uint8_t entry_status;       /* Entry Status. */
0024
0025     uint32_t handle;        /* System handle. */
0026     uint8_t reserved_0;
0027     uint8_t port_path_ctrl;
0028     uint16_t reserved_1;
0029
0030     __le16 tgt_idx;     /* Target Idx. */
0031     uint16_t timeout;       /* Command timeout. */
0032
0033     __le16 dseg_count;      /* Data segment count. */
0034     uint8_t scsi_rsp_dsd_len;
0035     uint8_t reserved_2;
0036
0037     struct scsi_lun lun;        /* LUN (LE). */
0038
0039     uint8_t cntrl_flags;
0040
0041     uint8_t task_mgmt_flags;    /* Task management flags. */
0042
0043     uint8_t task;
0044
0045     uint8_t crn;
0046
0047     uint8_t fcp_cdb[MAX_CMDSZ]; /* SCSI command words. */
0048     __le32 byte_count;      /* Total byte count. */
0049
0050     struct dsd64 dsd;
0051 };
0052
0053 #define STATUS_TYPE_FX00    0x01        /* Status entry. */
0054 struct sts_entry_fx00 {
0055     uint8_t entry_type;     /* Entry type. */
0056     uint8_t entry_count;        /* Entry count. */
0057     uint8_t sys_define;     /* System defined. */
0058     uint8_t entry_status;       /* Entry Status. */
0059
0060     uint32_t handle;        /* System handle. */
0061     uint32_t reserved_3;        /* System handle. */
0062
0063     __le16 comp_status;     /* Completion status. */
0064     uint16_t reserved_0;        /* OX_ID used by the firmware. */
0065
0066     __le32 residual_len;        /* FW calc residual transfer length. */
0067
0068     uint16_t reserved_1;
0069     uint16_t state_flags;       /* State flags. */
0070
0071     uint16_t reserved_2;
0072     __le16 scsi_status;     /* SCSI status. */
0073
0074     uint32_t sense_len;     /* FCP SENSE length. */
0075     uint8_t data[32];       /* FCP response/sense information. */
0076 };
0077
0078
0079 #define MAX_HANDLE_COUNT    15
0080 #define MULTI_STATUS_TYPE_FX00  0x0D
0081
0082 struct multi_sts_entry_fx00 {
0083     uint8_t entry_type;     /* Entry type. */
0084     uint8_t entry_count;        /* Entry count. */
0085     uint8_t handle_count;
0086     uint8_t entry_status;
0087
0088     __le32 handles[MAX_HANDLE_COUNT];
0089 };
0090
0091 #define TSK_MGMT_IOCB_TYPE_FX00     0x05
0092 struct tsk_mgmt_entry_fx00 {
0093     uint8_t entry_type;     /* Entry type. */
0094     uint8_t entry_count;        /* Entry count. */
0095     uint8_t sys_define;
0096     uint8_t entry_status;       /* Entry Status. */
0097
0098     uint32_t handle;        /* System handle. */
0099
0100     uint32_t reserved_0;
0101
0102     __le16 tgt_id;      /* Target Idx. */
0103
0104     uint16_t reserved_1;
0105     uint16_t reserved_3;
0106     uint16_t reserved_4;
0107
0108     struct scsi_lun lun;        /* LUN (LE). */
0109
0110     __le32 control_flags;       /* Control Flags. */
0111
0112     uint8_t reserved_2[32];
0113 };
0114
0115
0116 #define ABORT_IOCB_TYPE_FX00    0x08        /* Abort IOCB status. */
0117 struct abort_iocb_entry_fx00 {
0118     uint8_t entry_type;     /* Entry type. */
0119     uint8_t entry_count;        /* Entry count. */
0120     uint8_t sys_define;     /* System defined. */
0121     uint8_t entry_status;       /* Entry Status. */
0122
0123     uint32_t handle;        /* System handle. */
0124     __le32 reserved_0;
0125
0126     __le16 tgt_id_sts;      /* Completion status. */
0127     __le16 options;
0128
0129     uint32_t abort_handle;      /* System handle. */
0130     __le32 reserved_2;
0131
0132     __le16 req_que_no;
0133     uint8_t reserved_1[38];
0134 };
0135
0136 #define IOCTL_IOSB_TYPE_FX00    0x0C
0137 struct ioctl_iocb_entry_fx00 {
0138     uint8_t entry_type;     /* Entry type. */
0139     uint8_t entry_count;        /* Entry count. */
0140     uint8_t sys_define;     /* System defined. */
0141     uint8_t entry_status;       /* Entry Status. */
0142
0143     uint32_t handle;        /* System handle. */
0144     uint32_t reserved_0;        /* System handle. */
0145
0146     uint16_t comp_func_num;
0147     __le16 fw_iotcl_flags;
0148
0149     __le32 dataword_r;      /* Data word returned */
0150     uint32_t adapid;        /* Adapter ID */
0151     uint32_t dataword_r_extra;
0152
0153     __le32 seq_no;
0154     uint8_t reserved_2[20];
0155     uint32_t residuallen;
0156     __le32 status;
0157 };
0158
0159 #define STATUS_CONT_TYPE_FX00 0x04
0160
0161 #define FX00_IOCB_TYPE      0x0B
0162 struct fxdisc_entry_fx00 {
0163     uint8_t entry_type;     /* Entry type. */
0164     uint8_t entry_count;        /* Entry count. */
0165     uint8_t sys_define;     /* System Defined. */
0166     uint8_t entry_status;       /* Entry Status. */
0167
0168     uint32_t handle;        /* System handle. */
0169     __le32 reserved_0;      /* System handle. */
0170
0171     __le16 func_num;
0172     __le16 req_xfrcnt;
0173     __le16 req_dsdcnt;
0174     __le16 rsp_xfrcnt;
0175     __le16 rsp_dsdcnt;
0176     uint8_t flags;
0177     uint8_t reserved_1;
0178
0179     /*
0180      * Use array size 1 below to prevent that Coverity complains about
0181      * the append_dsd64() calls for the two arrays below.
0182      */
0183     struct dsd64 dseg_rq[1];
0184     struct dsd64 dseg_rsp[1];
0185
0186     __le32 dataword;
0187     __le32 adapid;
0188     __le32 adapid_hi;
0189     __le32 dataword_extra;
0190 };
0191
0192 struct qlafx00_tgt_node_info {
0193     uint8_t tgt_node_wwpn[WWN_SIZE];
0194     uint8_t tgt_node_wwnn[WWN_SIZE];
0195     uint32_t tgt_node_state;
0196     uint8_t reserved[128];
0197     uint32_t reserved_1[8];
0198     uint64_t reserved_2[4];
0199 } __packed;
0200
0201 #define QLAFX00_TGT_NODE_INFO sizeof(struct qlafx00_tgt_node_info)
0202
0203 #define QLAFX00_LINK_STATUS_DOWN    0x10
0204 #define QLAFX00_LINK_STATUS_UP      0x11
0205
0206 #define QLAFX00_PORT_SPEED_2G   0x2
0207 #define QLAFX00_PORT_SPEED_4G   0x4
0208 #define QLAFX00_PORT_SPEED_8G   0x8
0209 #define QLAFX00_PORT_SPEED_10G  0xa
0210 struct port_info_data {
0211     uint8_t         port_state;
0212     uint8_t         port_type;
0213     uint16_t        port_identifier;
0214     uint32_t        up_port_state;
0215     uint8_t         fw_ver_num[32];
0216     uint8_t         portal_attrib;
0217     uint16_t        host_option;
0218     uint8_t         reset_delay;
0219     uint8_t         pdwn_retry_cnt;
0220     uint16_t        max_luns2tgt;
0221     uint8_t         risc_ver;
0222     uint8_t         pconn_option;
0223     uint16_t        risc_option;
0224     uint16_t        max_frame_len;
0225     uint16_t        max_iocb_alloc;
0226     uint16_t        exec_throttle;
0227     uint8_t         retry_cnt;
0228     uint8_t         retry_delay;
0229     uint8_t         port_name[8];
0230     uint8_t         port_id[3];
0231     uint8_t         link_status;
0232     uint8_t         plink_rate;
0233     uint32_t        link_config;
0234     uint16_t        adap_haddr;
0235     uint8_t         tgt_disc;
0236     uint8_t         log_tout;
0237     uint8_t         node_name[8];
0238     uint16_t        erisc_opt1;
0239     uint8_t         resp_acc_tmr;
0240     uint8_t         intr_del_tmr;
0241     uint8_t         erisc_opt2;
0242     uint8_t         alt_port_name[8];
0243     uint8_t         alt_node_name[8];
0244     uint8_t         link_down_tout;
0245     uint8_t         conn_type;
0246     uint8_t         fc_fw_mode;
0247     uint32_t        uiReserved[48];
0248 } __packed;
0249
0250 /* OS Type Designations */
0251 #define OS_TYPE_UNKNOWN             0
0252 #define OS_TYPE_LINUX               2
0253
0254 /* Linux Info */
0255 #define SYSNAME_LENGTH              128
0256 #define NODENAME_LENGTH             64
0257 #define RELEASE_LENGTH              64
0258 #define VERSION_LENGTH              64
0259 #define MACHINE_LENGTH              64
0260 #define DOMNAME_LENGTH              64
0261
0262 struct host_system_info {
0263     uint32_t os_type;
0264     char    sysname[SYSNAME_LENGTH];
0265     char    nodename[NODENAME_LENGTH];
0266     char    release[RELEASE_LENGTH];
0267     char    version[VERSION_LENGTH];
0268     char    machine[MACHINE_LENGTH];
0269     char    domainname[DOMNAME_LENGTH];
0270     char    hostdriver[VERSION_LENGTH];
0271     uint32_t reserved[64];
0272 } __packed;
0273
0274 struct register_host_info {
0275     struct host_system_info     hsi;    /* host system info */
0276     uint64_t        utc;            /* UTC (system time) */
0277     uint32_t        reserved[64];       /* future additions */
0278 } __packed;
0279
0280
0281 #define QLAFX00_PORT_DATA_INFO (sizeof(struct port_info_data))
0282 #define QLAFX00_TGT_NODE_LIST_SIZE (sizeof(uint32_t) * 32)
0283
0284 struct config_info_data {
0285     uint8_t     model_num[16];
0286     uint8_t     model_description[80];
0287     uint8_t     reserved0[160];
0288     uint8_t     symbolic_name[64];
0289     uint8_t     serial_num[32];
0290     uint8_t     hw_version[16];
0291     uint8_t     fw_version[16];
0292     uint8_t     uboot_version[16];
0293     uint8_t     fru_serial_num[32];
0294
0295     uint8_t     fc_port_count;
0296     uint8_t     iscsi_port_count;
0297     uint8_t     reserved1[2];
0298
0299     uint8_t     mode;
0300     uint8_t     log_level;
0301     uint8_t     reserved2[2];
0302
0303     uint32_t    log_size;
0304
0305     uint8_t     tgt_pres_mode;
0306     uint8_t     iqn_flags;
0307     uint8_t     lun_mapping;
0308
0309     uint64_t    adapter_id;
0310
0311     uint32_t    cluster_key_len;
0312     uint8_t     cluster_key[16];
0313
0314     uint64_t    cluster_master_id;
0315     uint64_t    cluster_slave_id;
0316     uint8_t     cluster_flags;
0317     uint32_t    enabled_capabilities;
0318     uint32_t    nominal_temp_value;
0319 } __packed;
0320
0321 #define FXDISC_GET_CONFIG_INFO      0x01
0322 #define FXDISC_GET_PORT_INFO        0x02
0323 #define FXDISC_GET_TGT_NODE_INFO    0x80
0324 #define FXDISC_GET_TGT_NODE_LIST    0x81
0325 #define FXDISC_REG_HOST_INFO        0x99
0326 #define FXDISC_ABORT_IOCTL      0xff
0327
0328 #define QLAFX00_HBA_ICNTRL_REG      0x20B08
0329 #define QLAFX00_ICR_ENB_MASK            0x80000000
0330 #define QLAFX00_ICR_DIS_MASK            0x7fffffff
0331 #define QLAFX00_HST_RST_REG     0x18264
0332 #define QLAFX00_SOC_TEMP_REG        0x184C4
0333 #define QLAFX00_HST_TO_HBA_REG      0x20A04
0334 #define QLAFX00_HBA_TO_HOST_REG     0x21B70
0335 #define QLAFX00_HST_INT_STS_BITS    0x7
0336 #define QLAFX00_BAR1_BASE_ADDR_REG  0x40018
0337 #define QLAFX00_PEX0_WIN0_BASE_ADDR_REG 0x41824
0338
0339 #define QLAFX00_INTR_MB_CMPLT       0x1
0340 #define QLAFX00_INTR_RSP_CMPLT      0x2
0341 #define QLAFX00_INTR_ASYNC_CMPLT    0x4
0342
0343 #define QLAFX00_MBA_SYSTEM_ERR      0x8002
0344 #define QLAFX00_MBA_TEMP_OVER       0x8005
0345 #define QLAFX00_MBA_TEMP_NORM       0x8006
0346 #define QLAFX00_MBA_TEMP_CRIT       0x8007
0347 #define QLAFX00_MBA_LINK_UP     0x8011
0348 #define QLAFX00_MBA_LINK_DOWN       0x8012
0349 #define QLAFX00_MBA_PORT_UPDATE     0x8014
0350 #define QLAFX00_MBA_SHUTDOWN_RQSTD  0x8062
0351
0352 #define SOC_SW_RST_CONTROL_REG_CORE0     0x0020800
0353 #define SOC_FABRIC_RST_CONTROL_REG       0x0020840
0354 #define SOC_FABRIC_CONTROL_REG           0x0020200
0355 #define SOC_FABRIC_CONFIG_REG            0x0020204
0356 #define SOC_PWR_MANAGEMENT_PWR_DOWN_REG  0x001820C
0357
0358 #define SOC_INTERRUPT_SOURCE_I_CONTROL_REG     0x0020B00
0359 #define SOC_CORE_TIMER_REG                     0x0021850
0360 #define SOC_IRQ_ACK_REG                        0x00218b4
0361
0362 #define CONTINUE_A64_TYPE_FX00  0x03    /* Continuation entry. */
0363
0364 #define QLAFX00_SET_HST_INTR(ha, value) \
0365     wrt_reg_dword((ha)->cregbase + QLAFX00_HST_TO_HBA_REG, \
0366     value)
0367
0368 #define QLAFX00_CLR_HST_INTR(ha, value) \
0369     wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
0370     ~value)
0371
0372 #define QLAFX00_RD_INTR_REG(ha) \
0373     rd_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG)
0374
0375 #define QLAFX00_CLR_INTR_REG(ha, value) \
0376     wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_TO_HOST_REG, \
0377     ~value)
0378
0379 #define QLAFX00_SET_HBA_SOC_REG(ha, off, val)\
0380     wrt_reg_dword((ha)->cregbase + off, val)
0381
0382 #define QLAFX00_GET_HBA_SOC_REG(ha, off)\
0383     rd_reg_dword((ha)->cregbase + off)
0384
0385 #define QLAFX00_HBA_RST_REG(ha, val)\
0386     wrt_reg_dword((ha)->cregbase + QLAFX00_HST_RST_REG, val)
0387
0388 #define QLAFX00_RD_ICNTRL_REG(ha) \
0389     rd_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG)
0390
0391 #define QLAFX00_ENABLE_ICNTRL_REG(ha) \
0392     wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
0393     (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) | \
0394      QLAFX00_ICR_ENB_MASK))
0395
0396 #define QLAFX00_DISABLE_ICNTRL_REG(ha) \
0397     wrt_reg_dword((ha)->cregbase + QLAFX00_HBA_ICNTRL_REG, \
0398     (QLAFX00_GET_HBA_SOC_REG(ha, QLAFX00_HBA_ICNTRL_REG) & \
0399      QLAFX00_ICR_DIS_MASK))
0400
0401 #define QLAFX00_RD_REG(ha, off) \
0402     rd_reg_dword((ha)->cregbase + off)
0403
0404 #define QLAFX00_WR_REG(ha, off, val) \
0405     wrt_reg_dword((ha)->cregbase + off, val)
0406
0407 struct qla_mt_iocb_rqst_fx00 {
0408     __le32 reserved_0;
0409
0410     __le16 func_type;
0411     uint8_t flags;
0412     uint8_t reserved_1;
0413
0414     __le32 dataword;
0415
0416     __le32 adapid;
0417     __le32 adapid_hi;
0418
0419     __le32 dataword_extra;
0420
0421     __le16 req_len;
0422     __le16 reserved_2;
0423
0424     __le16 rsp_len;
0425     __le16 reserved_3;
0426 };
0427
0428 struct qla_mt_iocb_rsp_fx00 {
0429     uint32_t reserved_1;
0430
0431     uint16_t func_type;
0432     __le16 ioctl_flags;
0433
0434     __le32 ioctl_data;
0435
0436     uint32_t adapid;
0437     uint32_t adapid_hi;
0438
0439     uint32_t reserved_2;
0440     __le32 seq_number;
0441
0442     uint8_t reserved_3[20];
0443
0444     int32_t res_count;
0445
0446     __le32 status;
0447 };
0448
0449
0450 #define MAILBOX_REGISTER_COUNT_FX00 16
0451 #define AEN_MAILBOX_REGISTER_COUNT_FX00 8
0452 #define MAX_FIBRE_DEVICES_FX00  512
0453 #define MAX_LUNS_FX00       0x1024
0454 #define MAX_TARGETS_FX00    MAX_ISA_DEVICES
0455 #define REQUEST_ENTRY_CNT_FX00      512 /* Number of request entries. */
0456 #define RESPONSE_ENTRY_CNT_FX00     256 /* Number of response entries.*/
0457
0458 /*
0459  * Firmware state codes for QLAFX00 adapters
0460  */
0461 #define FSTATE_FX00_CONFIG_WAIT     0x0000  /* Waiting for driver to issue
0462                          * Initialize FW Mbox cmd
0463                          */
0464 #define FSTATE_FX00_INITIALIZED     0x1000  /* FW has been initialized by
0465                          * the driver
0466                          */
0467
0468 #define FX00_DEF_RATOV  10
0469
0470 struct mr_data_fx00 {
0471     uint8_t symbolic_name[64];
0472     uint8_t serial_num[32];
0473     uint8_t hw_version[16];
0474     uint8_t fw_version[16];
0475     uint8_t uboot_version[16];
0476     uint8_t fru_serial_num[32];
0477     fc_port_t       fcport;     /* fcport used for requests
0478                      * that are not linked
0479                      * to a particular target
0480                      */
0481     uint8_t fw_hbt_en;
0482     uint8_t fw_hbt_cnt;
0483     uint8_t fw_hbt_miss_cnt;
0484     uint32_t old_fw_hbt_cnt;
0485     uint16_t fw_reset_timer_tick;
0486     uint8_t fw_reset_timer_exp;
0487     uint16_t fw_critemp_timer_tick;
0488     uint32_t old_aenmbx0_state;
0489     uint32_t critical_temperature;
0490     bool extended_io_enabled;
0491     bool host_info_resend;
0492     uint8_t hinfo_resend_timer_tick;
0493 };
0494
0495 #define QLAFX00_EXTENDED_IO_EN_MASK    0x20
0496
0497 /*
0498  * SoC Junction Temperature is stored in
0499  * bits 9:1 of SoC Junction Temperature Register
0500  * in a firmware specific format format.
0501  * To get the temperature in Celsius degrees
0502  * the value from this bitfiled should be converted
0503  * using this formula:
0504  * Temperature (degrees C) = ((3,153,000 - (10,000 * X)) / 13,825)
0505  * where X is the bit field value
0506  * this macro reads the register, extracts the bitfield value,
0507  * performs the calcualtions and returns temperature in Celsius
0508  */
0509 #define QLAFX00_GET_TEMPERATURE(ha) ((3153000 - (10000 * \
0510     ((QLAFX00_RD_REG(ha, QLAFX00_SOC_TEMP_REG) & 0x3FE) >> 1))) / 13825)
0511
0512
0513 #define QLAFX00_LOOP_DOWN_TIME      615     /* 600 */
0514 #define QLAFX00_HEARTBEAT_INTERVAL  6   /* number of seconds */
0515 #define QLAFX00_HEARTBEAT_MISS_CNT  3   /* number of miss */
0516 #define QLAFX00_RESET_INTERVAL      120 /* number of seconds */
0517 #define QLAFX00_MAX_RESET_INTERVAL  600 /* number of seconds */
0518 #define QLAFX00_CRITEMP_INTERVAL    60  /* number of seconds */
0519 #define QLAFX00_HINFO_RESEND_INTERVAL   60  /* number of seconds */
0520
0521 #define QLAFX00_CRITEMP_THRSHLD     80  /* Celsius degrees */
0522
0523 /* Max conncurrent IOs that can be queued */
0524 #define QLAFX00_MAX_CANQUEUE        1024
0525
0526 /* IOCTL IOCB abort success */
0527 #define QLAFX00_IOCTL_ICOB_ABORT_SUCCESS    0x68
0528
0529 #endif