scsi/qla2xxx/qla_edif.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Marvell Fibre Channel HBA Driver
0004  * Copyright (c)  2021    Marvell
0005  */
0006 #ifndef __QLA_EDIF_H
0007 #define __QLA_EDIF_H
0008
0009 struct qla_scsi_host;
0010 #define EDIF_APP_ID 0x73730001
0011
0012 #define EDIF_MAX_INDEX  2048
0013 struct edif_sa_ctl {
0014     struct list_head next;
0015     uint16_t    del_index;
0016     uint16_t    index;
0017     uint16_t    slot;
0018     uint16_t    flags;
0019 #define EDIF_SA_CTL_FLG_REPL        BIT_0
0020 #define EDIF_SA_CTL_FLG_DEL     BIT_1
0021 #define EDIF_SA_CTL_FLG_CLEANUP_DEL BIT_4
0022     // Invalidate Index bit and mirrors QLA_SA_UPDATE_FLAGS_DELETE
0023     unsigned long   state;
0024 #define EDIF_SA_CTL_USED    1   /* Active Sa update  */
0025 #define EDIF_SA_CTL_PEND    2   /* Waiting for slot */
0026 #define EDIF_SA_CTL_REPL    3   /* Active Replace and Delete */
0027 #define EDIF_SA_CTL_DEL     4   /* Delete Pending */
0028     struct fc_port  *fcport;
0029     struct bsg_job *bsg_job;
0030     struct qla_sa_update_frame sa_frame;
0031 };
0032
0033 enum enode_flags_t {
0034     ENODE_ACTIVE = 0x1,
0035 };
0036
0037 struct pur_core {
0038     enum enode_flags_t  enode_flags;
0039     spinlock_t      pur_lock;
0040     struct  list_head   head;
0041 };
0042
0043 enum db_flags_t {
0044     EDB_ACTIVE = BIT_0,
0045 };
0046
0047 #define DBELL_ACTIVE(_v) (_v->e_dbell.db_flags & EDB_ACTIVE)
0048 #define DBELL_INACTIVE(_v) (!(_v->e_dbell.db_flags & EDB_ACTIVE))
0049
0050 struct edif_dbell {
0051     enum db_flags_t     db_flags;
0052     spinlock_t      db_lock;
0053     struct  list_head   head;
0054     struct bsg_job *dbell_bsg_job;
0055     unsigned long bsg_expire;
0056 };
0057
0058 #define SA_UPDATE_IOCB_TYPE            0x71    /* Security Association Update IOCB entry */
0059 struct sa_update_28xx {
0060     uint8_t entry_type;             /* Entry type. */
0061     uint8_t entry_count;            /* Entry count. */
0062     uint8_t sys_define;             /* System Defined. */
0063     uint8_t entry_status;           /* Entry Status. */
0064
0065     uint32_t handle;                /* IOCB System handle. */
0066
0067     union {
0068         __le16 nport_handle;  /* in: N_PORT handle. */
0069         __le16 comp_sts;              /* out: completion status */
0070 #define CS_PORT_EDIF_UNAVAIL    0x28
0071 #define CS_PORT_EDIF_LOGOUT 0x29
0072 #define CS_PORT_EDIF_SUPP_NOT_RDY 0x64
0073 #define CS_PORT_EDIF_INV_REQ      0x66
0074     } u;
0075     uint8_t vp_index;
0076     uint8_t reserved_1;
0077     uint8_t port_id[3];
0078     uint8_t flags;
0079 #define SA_FLAG_INVALIDATE BIT_0
0080 #define SA_FLAG_TX     BIT_1 // 1=tx, 0=rx
0081
0082     uint8_t sa_key[32];     /* 256 bit key */
0083     __le32 salt;
0084     __le32 spi;
0085     uint8_t sa_control;
0086 #define SA_CNTL_ENC_FCSP        (1 << 3)
0087 #define SA_CNTL_ENC_OPD         (2 << 3)
0088 #define SA_CNTL_ENC_MSK         (3 << 3)  // mask bits 4,3
0089 #define SA_CNTL_AES_GMAC    (1 << 2)
0090 #define SA_CNTL_KEY256          (2 << 0)
0091 #define SA_CNTL_KEY128          0
0092
0093     uint8_t reserved_2;
0094     __le16 sa_index;   // reserve: bit 11-15
0095     __le16 old_sa_info;
0096     __le16 new_sa_info;
0097 };
0098
0099 #define        NUM_ENTRIES     256
0100 #define        PUR_GET         1
0101
0102 struct dinfo {
0103     int     nodecnt;
0104     int     lstate;
0105 };
0106
0107 struct pur_ninfo {
0108     port_id_t       pur_sid;
0109     port_id_t   pur_did;
0110     uint8_t     vp_idx;
0111     short           pur_bytes_rcvd;
0112     unsigned short  pur_nphdl;
0113     unsigned int    pur_rx_xchg_address;
0114 };
0115
0116 struct purexevent {
0117     struct  pur_ninfo   pur_info;
0118     unsigned char       *msgp;
0119     u32         msgp_len;
0120 };
0121
0122 #define N_UNDEF     0
0123 #define N_PUREX     1
0124 struct enode {
0125     struct list_head    list;
0126     struct dinfo        dinfo;
0127     uint32_t        ntype;
0128     union {
0129         struct purexevent   purexinfo;
0130     } u;
0131 };
0132
0133 #define RX_ELS_SIZE (roundup(sizeof(struct enode) + ELS_MAX_PAYLOAD, SMP_CACHE_BYTES))
0134
0135 #define EDIF_SESSION_DOWN(_s) \
0136     (qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
0137      _s->disc_state == DSC_DELETED || \
0138      !_s->edif.app_sess_online))
0139
0140 #define EDIF_NEGOTIATION_PENDING(_fcport) \
0141     (DBELL_ACTIVE(_fcport->vha) && \
0142      (_fcport->disc_state == DSC_LOGIN_AUTH_PEND))
0143
0144 #define EDIF_SESS_DELETE(_s) \
0145     (qla_ini_mode_enabled(_s->vha) && (_s->disc_state == DSC_DELETE_PEND || \
0146      _s->disc_state == DSC_DELETED))
0147
0148 #endif  /* __QLA_EDIF_H */