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0006 #ifndef __QLA_BSG_H
0007 #define __QLA_BSG_H
0008
0009
0010 #define QL_VND_LOOPBACK 0x01
0011 #define QL_VND_A84_RESET 0x02
0012 #define QL_VND_A84_UPDATE_FW 0x03
0013 #define QL_VND_A84_MGMT_CMD 0x04
0014 #define QL_VND_IIDMA 0x05
0015 #define QL_VND_FCP_PRIO_CFG_CMD 0x06
0016 #define QL_VND_READ_FLASH 0x07
0017 #define QL_VND_UPDATE_FLASH 0x08
0018 #define QL_VND_SET_FRU_VERSION 0x0B
0019 #define QL_VND_READ_FRU_STATUS 0x0C
0020 #define QL_VND_WRITE_FRU_STATUS 0x0D
0021 #define QL_VND_DIAG_IO_CMD 0x0A
0022 #define QL_VND_WRITE_I2C 0x10
0023 #define QL_VND_READ_I2C 0x11
0024 #define QL_VND_FX00_MGMT_CMD 0x12
0025 #define QL_VND_SERDES_OP 0x13
0026 #define QL_VND_SERDES_OP_EX 0x14
0027 #define QL_VND_GET_FLASH_UPDATE_CAPS 0x15
0028 #define QL_VND_SET_FLASH_UPDATE_CAPS 0x16
0029 #define QL_VND_GET_BBCR_DATA 0x17
0030 #define QL_VND_GET_PRIV_STATS 0x18
0031 #define QL_VND_DPORT_DIAGNOSTICS 0x19
0032 #define QL_VND_GET_PRIV_STATS_EX 0x1A
0033 #define QL_VND_SS_GET_FLASH_IMAGE_STATUS 0x1E
0034 #define QL_VND_EDIF_MGMT 0X1F
0035 #define QL_VND_MANAGE_HOST_STATS 0x23
0036 #define QL_VND_GET_HOST_STATS 0x24
0037 #define QL_VND_GET_TGT_STATS 0x25
0038 #define QL_VND_MANAGE_HOST_PORT 0x26
0039 #define QL_VND_MBX_PASSTHRU 0x2B
0040 #define QL_VND_DPORT_DIAGNOSTICS_V2 0x2C
0041
0042
0043 #define EXT_STATUS_OK 0
0044 #define EXT_STATUS_ERR 1
0045 #define EXT_STATUS_BUSY 2
0046 #define EXT_STATUS_INVALID_PARAM 6
0047 #define EXT_STATUS_DATA_OVERRUN 7
0048 #define EXT_STATUS_DATA_UNDERRUN 8
0049 #define EXT_STATUS_MAILBOX 11
0050 #define EXT_STATUS_BUFFER_TOO_SMALL 16
0051 #define EXT_STATUS_NO_MEMORY 17
0052 #define EXT_STATUS_DEVICE_OFFLINE 22
0053
0054
0055
0056
0057
0058 #define EXT_STATUS_NOT_SUPPORTED 27
0059 #define EXT_STATUS_INVALID_CFG 28
0060 #define EXT_STATUS_DMA_ERR 29
0061 #define EXT_STATUS_TIMEOUT 30
0062 #define EXT_STATUS_THREAD_FAILED 31
0063 #define EXT_STATUS_DATA_CMP_FAILED 32
0064 #define EXT_STATUS_DPORT_DIAG_ERR 40
0065 #define EXT_STATUS_DPORT_DIAG_IN_PROCESS 41
0066 #define EXT_STATUS_DPORT_DIAG_NOT_RUNNING 42
0067
0068
0069 #define INT_DEF_LB_LOOPBACK_CMD 0
0070 #define INT_DEF_LB_ECHO_CMD 1
0071
0072
0073 #define INTERNAL_LOOPBACK 0xF1
0074 #define EXTERNAL_LOOPBACK 0xF2
0075 #define ENABLE_INTERNAL_LOOPBACK 0x02
0076 #define ENABLE_EXTERNAL_LOOPBACK 0x04
0077 #define INTERNAL_LOOPBACK_MASK 0x000E
0078 #define MAX_ELS_FRAME_PAYLOAD 252
0079 #define ELS_OPCODE_BYTE 0x10
0080
0081
0082 #define A84_ISSUE_WRITE_TYPE_CMD 0
0083 #define A84_ISSUE_READ_TYPE_CMD 1
0084 #define A84_CLEANUP_CMD 2
0085 #define A84_ISSUE_RESET_OP_FW 3
0086 #define A84_ISSUE_RESET_DIAG_FW 4
0087 #define A84_ISSUE_UPDATE_OPFW_CMD 5
0088 #define A84_ISSUE_UPDATE_DIAGFW_CMD 6
0089
0090 struct qla84_mgmt_param {
0091 union {
0092 struct {
0093 uint32_t start_addr;
0094 } mem;
0095 struct {
0096 uint32_t id;
0097 #define QLA84_MGMT_CONFIG_ID_UIF 1
0098 #define QLA84_MGMT_CONFIG_ID_FCOE_COS 2
0099 #define QLA84_MGMT_CONFIG_ID_PAUSE 3
0100 #define QLA84_MGMT_CONFIG_ID_TIMEOUTS 4
0101
0102 uint32_t param0;
0103 uint32_t param1;
0104 } config;
0105
0106 struct {
0107 uint32_t type;
0108 #define QLA84_MGMT_INFO_CONFIG_LOG_DATA 1
0109 #define QLA84_MGMT_INFO_LOG_DATA 2
0110 #define QLA84_MGMT_INFO_PORT_STAT 3
0111 #define QLA84_MGMT_INFO_LIF_STAT 4
0112 #define QLA84_MGMT_INFO_ASIC_STAT 5
0113 #define QLA84_MGMT_INFO_CONFIG_PARAMS 6
0114 #define QLA84_MGMT_INFO_PANIC_LOG 7
0115
0116 uint32_t context;
0117
0118
0119
0120 #define IC_LOG_DATA_LOG_ID_DEBUG_LOG 0
0121 #define IC_LOG_DATA_LOG_ID_LEARN_LOG 1
0122 #define IC_LOG_DATA_LOG_ID_FC_ACL_INGRESS_LOG 2
0123 #define IC_LOG_DATA_LOG_ID_FC_ACL_EGRESS_LOG 3
0124 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_INGRESS_LOG 4
0125 #define IC_LOG_DATA_LOG_ID_ETHERNET_ACL_EGRESS_LOG 5
0126 #define IC_LOG_DATA_LOG_ID_MESSAGE_TRANSMIT_LOG 6
0127 #define IC_LOG_DATA_LOG_ID_MESSAGE_RECEIVE_LOG 7
0128 #define IC_LOG_DATA_LOG_ID_LINK_EVENT_LOG 8
0129 #define IC_LOG_DATA_LOG_ID_DCX_LOG 9
0130
0131
0132
0133
0134 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT0 0
0135 #define IC_PORT_STATISTICS_PORT_NUMBER_ETHERNET_PORT1 1
0136 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT0 2
0137 #define IC_PORT_STATISTICS_PORT_NUMBER_NSL_PORT1 3
0138 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT0 4
0139 #define IC_PORT_STATISTICS_PORT_NUMBER_FC_PORT1 5
0140
0141
0142
0143
0144
0145 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT0 0
0146 #define IC_LIF_STATISTICS_LIF_NUMBER_ETHERNET_PORT1 1
0147 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT0 2
0148 #define IC_LIF_STATISTICS_LIF_NUMBER_FC_PORT1 3
0149 #define IC_LIF_STATISTICS_LIF_NUMBER_CPU 6
0150
0151 } info;
0152 } u;
0153 };
0154
0155 struct qla84_msg_mgmt {
0156 uint16_t cmd;
0157 #define QLA84_MGMT_READ_MEM 0x00
0158 #define QLA84_MGMT_WRITE_MEM 0x01
0159 #define QLA84_MGMT_CHNG_CONFIG 0x02
0160 #define QLA84_MGMT_GET_INFO 0x03
0161 uint16_t rsrvd;
0162 struct qla84_mgmt_param mgmtp;
0163 uint32_t len;
0164 uint8_t payload[];
0165 };
0166
0167 struct qla_bsg_a84_mgmt {
0168 struct qla84_msg_mgmt mgmt;
0169 } __attribute__ ((packed));
0170
0171 struct qla_scsi_addr {
0172 uint16_t bus;
0173 uint16_t target;
0174 } __attribute__ ((packed));
0175
0176 struct qla_ext_dest_addr {
0177 union {
0178 uint8_t wwnn[8];
0179 uint8_t wwpn[8];
0180 uint8_t id[4];
0181 struct qla_scsi_addr scsi_addr;
0182 } dest_addr;
0183 uint16_t dest_type;
0184 #define EXT_DEF_TYPE_WWPN 2
0185 uint16_t lun;
0186 uint16_t padding[2];
0187 } __attribute__ ((packed));
0188
0189 struct qla_port_param {
0190 struct qla_ext_dest_addr fc_scsi_addr;
0191 uint16_t mode;
0192 uint16_t speed;
0193 } __attribute__ ((packed));
0194
0195 struct qla_mbx_passthru {
0196 uint16_t reserved1[2];
0197 uint16_t mbx_in[32];
0198 uint16_t mbx_out[32];
0199 uint32_t reserved2[16];
0200 } __packed;
0201
0202
0203
0204 #define MAX_FRU_SIZE 36
0205
0206 struct qla_field_address {
0207 uint16_t offset;
0208 uint16_t device;
0209 uint16_t option;
0210 } __packed;
0211
0212 struct qla_field_info {
0213 uint8_t version[MAX_FRU_SIZE];
0214 } __packed;
0215
0216 struct qla_image_version {
0217 struct qla_field_address field_address;
0218 struct qla_field_info field_info;
0219 } __packed;
0220
0221 struct qla_image_version_list {
0222 uint32_t count;
0223 struct qla_image_version version[];
0224 } __packed;
0225
0226 struct qla_status_reg {
0227 struct qla_field_address field_address;
0228 uint8_t status_reg;
0229 uint8_t reserved[7];
0230 } __packed;
0231
0232 struct qla_i2c_access {
0233 uint16_t device;
0234 uint16_t offset;
0235 uint16_t option;
0236 uint16_t length;
0237 uint8_t buffer[0x40];
0238 } __packed;
0239
0240
0241
0242
0243 #define INT_SC_SERDES_READ_REG 1
0244 #define INT_SC_SERDES_WRITE_REG 2
0245
0246 struct qla_serdes_reg {
0247 uint16_t cmd;
0248 uint16_t addr;
0249 uint16_t val;
0250 } __packed;
0251
0252 struct qla_serdes_reg_ex {
0253 uint16_t cmd;
0254 uint32_t addr;
0255 uint32_t val;
0256 } __packed;
0257
0258 struct qla_flash_update_caps {
0259 uint64_t capabilities;
0260 uint32_t outage_duration;
0261 uint8_t reserved[20];
0262 } __packed;
0263
0264
0265 #define QLA_BBCR_STATUS_DISABLED 0
0266 #define QLA_BBCR_STATUS_ENABLED 1
0267 #define QLA_BBCR_STATUS_UNKNOWN 2
0268
0269
0270 #define QLA_BBCR_STATE_OFFLINE 0
0271 #define QLA_BBCR_STATE_ONLINE 1
0272
0273
0274 #define QLA_BBCR_REASON_PORT_SPEED 1
0275 #define QLA_BBCR_REASON_PEER_PORT 2
0276 #define QLA_BBCR_REASON_SWITCH 3
0277 #define QLA_BBCR_REASON_LOGIN_REJECT 4
0278
0279 struct qla_bbcr_data {
0280 uint8_t status;
0281 uint8_t state;
0282 uint8_t configured_bbscn;
0283 uint8_t negotiated_bbscn;
0284 uint8_t offline_reason_code;
0285 uint16_t mbx1;
0286 uint8_t reserved[9];
0287 } __packed;
0288
0289 struct qla_dport_diag {
0290 uint16_t options;
0291 uint32_t buf[16];
0292 uint8_t unused[62];
0293 } __packed;
0294
0295 #define QLA_GET_DPORT_RESULT_V2 0
0296 #define QLA_RESTART_DPORT_TEST_V2 1
0297 #define QLA_START_DPORT_TEST_V2 2
0298 struct qla_dport_diag_v2 {
0299 uint16_t options;
0300 uint16_t mbx1;
0301 uint16_t mbx2;
0302 uint8_t unused[58];
0303 uint8_t buf[1024];
0304 } __packed;
0305
0306
0307 #define QLA_DPORT_RESULT 0x0
0308 #define QLA_DPORT_START 0x2
0309
0310
0311 struct qla_active_regions {
0312 uint8_t global_image;
0313 uint8_t board_config;
0314 uint8_t vpd_nvram;
0315 uint8_t npiv_config_0_1;
0316 uint8_t npiv_config_2_3;
0317 uint8_t reserved[32];
0318 } __packed;
0319
0320 #include "qla_edif_bsg.h"
0321
0322 #endif