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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /******************************************************************************
0003 *                  QLOGIC LINUX SOFTWARE
0004 *
0005 * QLogic ISP1280 (Ultra2) /12160 (Ultra3) SCSI driver
0006 * Copyright (C) 2000 Qlogic Corporation
0007 * (www.qlogic.com)
0008 *
0009 ******************************************************************************/
0010 
0011 #ifndef _QLA1280_H
0012 #define _QLA1280_H
0013 
0014 /*
0015  * Data bit definitions.
0016  */
0017 #define BIT_0   0x1
0018 #define BIT_1   0x2
0019 #define BIT_2   0x4
0020 #define BIT_3   0x8
0021 #define BIT_4   0x10
0022 #define BIT_5   0x20
0023 #define BIT_6   0x40
0024 #define BIT_7   0x80
0025 #define BIT_8   0x100
0026 #define BIT_9   0x200
0027 #define BIT_10  0x400
0028 #define BIT_11  0x800
0029 #define BIT_12  0x1000
0030 #define BIT_13  0x2000
0031 #define BIT_14  0x4000
0032 #define BIT_15  0x8000
0033 #define BIT_16  0x10000
0034 #define BIT_17  0x20000
0035 #define BIT_18  0x40000
0036 #define BIT_19  0x80000
0037 #define BIT_20  0x100000
0038 #define BIT_21  0x200000
0039 #define BIT_22  0x400000
0040 #define BIT_23  0x800000
0041 #define BIT_24  0x1000000
0042 #define BIT_25  0x2000000
0043 #define BIT_26  0x4000000
0044 #define BIT_27  0x8000000
0045 #define BIT_28  0x10000000
0046 #define BIT_29  0x20000000
0047 #define BIT_30  0x40000000
0048 #define BIT_31  0x80000000
0049 
0050 #if MEMORY_MAPPED_IO
0051 #define RD_REG_WORD(addr)       readw_relaxed(addr)
0052 #define RD_REG_WORD_dmasync(addr)   readw(addr)
0053 #define WRT_REG_WORD(addr, data)    writew(data, addr)
0054 #else               /* MEMORY_MAPPED_IO */
0055 #define RD_REG_WORD(addr)       inw((unsigned long)addr)
0056 #define RD_REG_WORD_dmasync(addr)   RD_REG_WORD(addr)
0057 #define WRT_REG_WORD(addr, data)    outw(data, (unsigned long)addr)
0058 #endif              /* MEMORY_MAPPED_IO */
0059 
0060 /*
0061  * Host adapter default definitions.
0062  */
0063 #define MAX_BUSES   2   /* 2 */
0064 #define MAX_B_BITS  1
0065 
0066 #define MAX_TARGETS 16  /* 16 */
0067 #define MAX_T_BITS  4   /* 4 */
0068 
0069 #define MAX_LUNS    8   /* 32 */
0070 #define MAX_L_BITS  3   /* 5 */
0071 
0072 /*
0073  * Watchdog time quantum
0074  */
0075 #define QLA1280_WDG_TIME_QUANTUM    5   /* In seconds */
0076 
0077 /* Command retry count (0-65535) */
0078 #define COMMAND_RETRY_COUNT     255
0079 
0080 /* Maximum outstanding commands in ISP queues */
0081 #define MAX_OUTSTANDING_COMMANDS    512
0082 #define COMPLETED_HANDLE        ((unsigned char *) \
0083                     (MAX_OUTSTANDING_COMMANDS + 2))
0084 
0085 /* ISP request and response entry counts (37-65535) */
0086 #define REQUEST_ENTRY_CNT       255 /* Number of request entries. */
0087 #define RESPONSE_ENTRY_CNT      63  /* Number of response entries. */
0088 
0089 /*
0090  * SCSI Request Block structure (sp) that occurs after each struct scsi_cmnd.
0091  */
0092 struct srb {
0093     struct list_head list;      /* (8/16) LU queue */
0094     struct scsi_cmnd *cmd;  /* (4/8) SCSI command block */
0095     /* NOTE: the sp->cmd will be NULL when this completion is
0096      * called, so you should know the scsi_cmnd when using this */
0097     struct completion *wait;
0098     dma_addr_t saved_dma_handle;    /* for unmap of single transfers */
0099     uint8_t flags;      /* (1) Status flags. */
0100     uint8_t dir;        /* direction of transfer */
0101 };
0102 
0103 /*
0104  * SRB flag definitions
0105  */
0106 #define SRB_TIMEOUT     (1 << 0)    /* Command timed out */
0107 #define SRB_SENT        (1 << 1)    /* Command sent to ISP */
0108 #define SRB_ABORT_PENDING   (1 << 2)    /* Command abort sent to device */
0109 #define SRB_ABORTED     (1 << 3)    /* Command aborted command already */
0110 
0111 /*
0112  *  ISP I/O Register Set structure definitions.
0113  */
0114 struct device_reg {
0115     uint16_t id_l;      /* ID low */
0116     uint16_t id_h;      /* ID high */
0117     uint16_t cfg_0;     /* Configuration 0 */
0118 #define ISP_CFG0_HWMSK   0x000f /* Hardware revision mask */
0119 #define ISP_CFG0_1020    BIT_0  /* ISP1020 */
0120 #define ISP_CFG0_1020A   BIT_1  /* ISP1020A */
0121 #define ISP_CFG0_1040    BIT_2  /* ISP1040 */
0122 #define ISP_CFG0_1040A   BIT_3  /* ISP1040A */
0123 #define ISP_CFG0_1040B   BIT_4  /* ISP1040B */
0124 #define ISP_CFG0_1040C   BIT_5  /* ISP1040C */
0125     uint16_t cfg_1;     /* Configuration 1 */
0126 #define ISP_CFG1_F128    BIT_6  /* 128-byte FIFO threshold */
0127 #define ISP_CFG1_F64     BIT_4|BIT_5 /* 128-byte FIFO threshold */
0128 #define ISP_CFG1_F32     BIT_5  /* 128-byte FIFO threshold */
0129 #define ISP_CFG1_F16     BIT_4  /* 128-byte FIFO threshold */
0130 #define ISP_CFG1_BENAB   BIT_2  /* Global Bus burst enable */
0131 #define ISP_CFG1_SXP     BIT_0  /* SXP register select */
0132     uint16_t ictrl;     /* Interface control */
0133 #define ISP_RESET        BIT_0  /* ISP soft reset */
0134 #define ISP_EN_INT       BIT_1  /* ISP enable interrupts. */
0135 #define ISP_EN_RISC      BIT_2  /* ISP enable RISC interrupts. */
0136 #define ISP_FLASH_ENABLE BIT_8  /* Flash BIOS Read/Write enable */
0137 #define ISP_FLASH_UPPER  BIT_9  /* Flash upper bank select */
0138     uint16_t istatus;   /* Interface status */
0139 #define PCI_64BIT_SLOT   BIT_14 /* PCI 64-bit slot indicator. */
0140 #define RISC_INT         BIT_2  /* RISC interrupt */
0141 #define PCI_INT          BIT_1  /* PCI interrupt */
0142     uint16_t semaphore; /* Semaphore */
0143     uint16_t nvram;     /* NVRAM register. */
0144 #define NV_DESELECT     0
0145 #define NV_CLOCK        BIT_0
0146 #define NV_SELECT       BIT_1
0147 #define NV_DATA_OUT     BIT_2
0148 #define NV_DATA_IN      BIT_3
0149     uint16_t flash_data;    /* Flash BIOS data */
0150     uint16_t flash_address; /* Flash BIOS address */
0151 
0152     uint16_t unused_1[0x06];
0153     
0154     /* cdma_* and ddma_* are 1040 only */
0155     uint16_t cdma_cfg;
0156 #define CDMA_CONF_SENAB  BIT_3  /* SXP to DMA Data enable */
0157 #define CDMA_CONF_RIRQ   BIT_2  /* RISC interrupt enable */
0158 #define CDMA_CONF_BENAB  BIT_1  /* Bus burst enable */
0159 #define CDMA_CONF_DIR    BIT_0  /* DMA direction (0=fifo->host 1=host->fifo) */
0160     uint16_t cdma_ctrl; 
0161     uint16_t cdma_status;   
0162     uint16_t cdma_fifo_status;
0163     uint16_t cdma_count;
0164     uint16_t cdma_reserved;
0165     uint16_t cdma_address_count_0;
0166     uint16_t cdma_address_count_1;
0167     uint16_t cdma_address_count_2;
0168     uint16_t cdma_address_count_3;
0169 
0170     uint16_t unused_2[0x06];
0171 
0172     uint16_t ddma_cfg;
0173 #define DDMA_CONF_SENAB  BIT_3  /* SXP to DMA Data enable */
0174 #define DDMA_CONF_RIRQ   BIT_2  /* RISC interrupt enable */
0175 #define DDMA_CONF_BENAB  BIT_1  /* Bus burst enable */
0176 #define DDMA_CONF_DIR    BIT_0  /* DMA direction (0=fifo->host 1=host->fifo) */
0177     uint16_t ddma_ctrl;
0178     uint16_t ddma_status; 
0179     uint16_t ddma_fifo_status;
0180     uint16_t ddma_xfer_count_low;
0181     uint16_t ddma_xfer_count_high;
0182     uint16_t ddma_addr_count_0;
0183     uint16_t ddma_addr_count_1;
0184     uint16_t ddma_addr_count_2;
0185     uint16_t ddma_addr_count_3; 
0186 
0187     uint16_t unused_3[0x0e];
0188 
0189     uint16_t mailbox0;  /* Mailbox 0 */
0190     uint16_t mailbox1;  /* Mailbox 1 */
0191     uint16_t mailbox2;  /* Mailbox 2 */
0192     uint16_t mailbox3;  /* Mailbox 3 */
0193     uint16_t mailbox4;  /* Mailbox 4 */
0194     uint16_t mailbox5;  /* Mailbox 5 */
0195     uint16_t mailbox6;  /* Mailbox 6 */
0196     uint16_t mailbox7;  /* Mailbox 7 */
0197 
0198     uint16_t unused_4[0x20];/* 0x80-0xbf Gap */
0199 
0200     uint16_t host_cmd;  /* Host command and control */
0201 #define HOST_INT      BIT_7 /* host interrupt bit */
0202 #define BIOS_ENABLE   BIT_0
0203 
0204     uint16_t unused_5[0x5]; /* 0xc2-0xcb Gap */
0205 
0206     uint16_t gpio_data;
0207     uint16_t gpio_enable;
0208 
0209     uint16_t unused_6[0x11];    /* d0-f0 */
0210     uint16_t scsiControlPins;   /* f2 */
0211 };
0212 
0213 #define MAILBOX_REGISTER_COUNT  8
0214 
0215 /*
0216  *  ISP product identification definitions in mailboxes after reset.
0217  */
0218 #define PROD_ID_1       0x4953
0219 #define PROD_ID_2       0x0000
0220 #define PROD_ID_2a      0x5020
0221 #define PROD_ID_3       0x2020
0222 #define PROD_ID_4       0x1
0223 
0224 /*
0225  * ISP host command and control register command definitions
0226  */
0227 #define HC_RESET_RISC       0x1000  /* Reset RISC */
0228 #define HC_PAUSE_RISC       0x2000  /* Pause RISC */
0229 #define HC_RELEASE_RISC     0x3000  /* Release RISC from reset. */
0230 #define HC_SET_HOST_INT     0x5000  /* Set host interrupt */
0231 #define HC_CLR_HOST_INT     0x6000  /* Clear HOST interrupt */
0232 #define HC_CLR_RISC_INT     0x7000  /* Clear RISC interrupt */
0233 #define HC_DISABLE_BIOS     0x9000  /* Disable BIOS. */
0234 
0235 /*
0236  * ISP mailbox Self-Test status codes
0237  */
0238 #define MBS_FRM_ALIVE       0   /* Firmware Alive. */
0239 #define MBS_CHKSUM_ERR      1   /* Checksum Error. */
0240 #define MBS_SHADOW_LD_ERR   2   /* Shadow Load Error. */
0241 #define MBS_BUSY        4   /* Busy. */
0242 
0243 /*
0244  * ISP mailbox command complete status codes
0245  */
0246 #define MBS_CMD_CMP     0x4000  /* Command Complete. */
0247 #define MBS_INV_CMD     0x4001  /* Invalid Command. */
0248 #define MBS_HOST_INF_ERR    0x4002  /* Host Interface Error. */
0249 #define MBS_TEST_FAILED     0x4003  /* Test Failed. */
0250 #define MBS_CMD_ERR     0x4005  /* Command Error. */
0251 #define MBS_CMD_PARAM_ERR   0x4006  /* Command Parameter Error. */
0252 
0253 /*
0254  * ISP mailbox asynchronous event status codes
0255  */
0256 #define MBA_ASYNC_EVENT     0x8000  /* Asynchronous event. */
0257 #define MBA_BUS_RESET       0x8001  /* SCSI Bus Reset. */
0258 #define MBA_SYSTEM_ERR      0x8002  /* System Error. */
0259 #define MBA_REQ_TRANSFER_ERR    0x8003  /* Request Transfer Error. */
0260 #define MBA_RSP_TRANSFER_ERR    0x8004  /* Response Transfer Error. */
0261 #define MBA_WAKEUP_THRES    0x8005  /* Request Queue Wake-up. */
0262 #define MBA_TIMEOUT_RESET   0x8006  /* Execution Timeout Reset. */
0263 #define MBA_DEVICE_RESET    0x8007  /* Bus Device Reset. */
0264 #define MBA_BUS_MODE_CHANGE 0x800E  /* SCSI bus mode transition. */
0265 #define MBA_SCSI_COMPLETION 0x8020  /* Completion response. */
0266 
0267 /*
0268  * ISP mailbox commands
0269  */
0270 #define MBC_NOP             0   /* No Operation */
0271 #define MBC_LOAD_RAM            1   /* Load RAM */
0272 #define MBC_EXECUTE_FIRMWARE        2   /* Execute firmware */
0273 #define MBC_DUMP_RAM            3   /* Dump RAM contents */
0274 #define MBC_WRITE_RAM_WORD      4   /* Write ram word */
0275 #define MBC_READ_RAM_WORD       5   /* Read ram word */
0276 #define MBC_MAILBOX_REGISTER_TEST   6   /* Wrap incoming mailboxes */
0277 #define MBC_VERIFY_CHECKSUM     7   /* Verify checksum */
0278 #define MBC_ABOUT_FIRMWARE      8   /* Get firmware revision */
0279 #define MBC_LOAD_RAM_A64_ROM        9   /* Load RAM 64bit ROM version */
0280 #define MBC_DUMP_RAM_A64_ROM        0x0a    /* Dump RAM 64bit ROM version */
0281 #define MBC_INIT_REQUEST_QUEUE      0x10    /* Initialize request queue */
0282 #define MBC_INIT_RESPONSE_QUEUE     0x11    /* Initialize response queue */
0283 #define MBC_EXECUTE_IOCB        0x12    /* Execute IOCB command */
0284 #define MBC_ABORT_COMMAND       0x15    /* Abort IOCB command */
0285 #define MBC_ABORT_DEVICE        0x16    /* Abort device (ID/LUN) */
0286 #define MBC_ABORT_TARGET        0x17    /* Abort target (ID) */
0287 #define MBC_BUS_RESET           0x18    /* SCSI bus reset */
0288 #define MBC_GET_RETRY_COUNT     0x22    /* Get retry count and delay */
0289 #define MBC_GET_TARGET_PARAMETERS   0x28    /* Get target parameters */
0290 #define MBC_SET_INITIATOR_ID        0x30    /* Set initiator SCSI ID */
0291 #define MBC_SET_SELECTION_TIMEOUT   0x31    /* Set selection timeout */
0292 #define MBC_SET_RETRY_COUNT     0x32    /* Set retry count and delay */
0293 #define MBC_SET_TAG_AGE_LIMIT       0x33    /* Set tag age limit */
0294 #define MBC_SET_CLOCK_RATE      0x34    /* Set clock rate */
0295 #define MBC_SET_ACTIVE_NEGATION     0x35    /* Set active negation state */
0296 #define MBC_SET_ASYNC_DATA_SETUP    0x36    /* Set async data setup time */
0297 #define MBC_SET_PCI_CONTROL     0x37    /* Set BUS control parameters */
0298 #define MBC_SET_TARGET_PARAMETERS   0x38    /* Set target parameters */
0299 #define MBC_SET_DEVICE_QUEUE        0x39    /* Set device queue parameters */
0300 #define MBC_SET_RESET_DELAY_PARAMETERS  0x3A    /* Set reset delay parameters */
0301 #define MBC_SET_SYSTEM_PARAMETER    0x45    /* Set system parameter word */
0302 #define MBC_SET_FIRMWARE_FEATURES   0x4A    /* Set firmware feature word */
0303 #define MBC_INIT_REQUEST_QUEUE_A64  0x52    /* Initialize request queue A64 */
0304 #define MBC_INIT_RESPONSE_QUEUE_A64 0x53    /* Initialize response q A64 */
0305 #define MBC_ENABLE_TARGET_MODE      0x55    /* Enable target mode */
0306 #define MBC_SET_DATA_OVERRUN_RECOVERY   0x5A    /* Set data overrun recovery mode */
0307 
0308 /*
0309  * ISP Get/Set Target Parameters mailbox command control flags.
0310  */
0311 #define TP_PPR          BIT_5   /* PPR */
0312 #define TP_RENEGOTIATE      BIT_8   /* Renegotiate on error. */
0313 #define TP_STOP_QUEUE           BIT_9   /* Stop que on check condition */
0314 #define TP_AUTO_REQUEST_SENSE   BIT_10  /* Automatic request sense. */
0315 #define TP_TAGGED_QUEUE         BIT_11  /* Tagged queuing. */
0316 #define TP_SYNC                 BIT_12  /* Synchronous data transfers. */
0317 #define TP_WIDE                 BIT_13  /* Wide data transfers. */
0318 #define TP_PARITY               BIT_14  /* Parity checking. */
0319 #define TP_DISCONNECT           BIT_15  /* Disconnect privilege. */
0320 
0321 /*
0322  * NVRAM Command values.
0323  */
0324 #define NV_START_BIT        BIT_2
0325 #define NV_WRITE_OP     (BIT_26 | BIT_24)
0326 #define NV_READ_OP      (BIT_26 | BIT_25)
0327 #define NV_ERASE_OP     (BIT_26 | BIT_25 | BIT_24)
0328 #define NV_MASK_OP      (BIT_26 | BIT_25 | BIT_24)
0329 #define NV_DELAY_COUNT      10
0330 
0331 /*
0332  *  QLogic ISP1280/ISP12160 NVRAM structure definition.
0333  */
0334 struct nvram {
0335     uint8_t id0;        /* 0 */
0336     uint8_t id1;        /* 1 */
0337     uint8_t id2;        /* 2 */
0338     uint8_t id3;        /* 3 */
0339     uint8_t version;    /* 4 */
0340 
0341     struct {
0342         uint8_t bios_configuration_mode:2;
0343         uint8_t bios_disable:1;
0344         uint8_t selectable_scsi_boot_enable:1;
0345         uint8_t cd_rom_boot_enable:1;
0346         uint8_t disable_loading_risc_code:1;
0347         uint8_t enable_64bit_addressing:1;
0348         uint8_t unused_7:1;
0349     } cntr_flags_1;     /* 5 */
0350 
0351     struct {
0352         uint8_t boot_lun_number:5;
0353         uint8_t scsi_bus_number:1;
0354         uint8_t unused_6:1;
0355         uint8_t unused_7:1;
0356     } cntr_flags_2l;    /* 7 */
0357 
0358     struct {
0359         uint8_t boot_target_number:4;
0360         uint8_t unused_12:1;
0361         uint8_t unused_13:1;
0362         uint8_t unused_14:1;
0363         uint8_t unused_15:1;
0364     } cntr_flags_2h;    /* 8 */
0365 
0366     uint16_t unused_8;  /* 8, 9 */
0367     uint16_t unused_10; /* 10, 11 */
0368     uint16_t unused_12; /* 12, 13 */
0369     uint16_t unused_14; /* 14, 15 */
0370 
0371     struct {
0372         uint8_t reserved:2;
0373         uint8_t burst_enable:1;
0374         uint8_t reserved_1:1;
0375         uint8_t fifo_threshold:4;
0376     } isp_config;       /* 16 */
0377 
0378     /* Termination
0379      * 0 = Disable, 1 = high only, 3 = Auto term
0380      */
0381     struct {
0382         uint8_t scsi_bus_1_control:2;
0383         uint8_t scsi_bus_0_control:2;
0384         uint8_t unused_0:1;
0385         uint8_t unused_1:1;
0386         uint8_t unused_2:1;
0387         uint8_t auto_term_support:1;
0388     } termination;      /* 17 */
0389 
0390     uint16_t isp_parameter; /* 18, 19 */
0391 
0392     union {
0393         uint16_t w;
0394         struct {
0395             uint16_t enable_fast_posting:1;
0396             uint16_t report_lvd_bus_transition:1;
0397             uint16_t unused_2:1;
0398             uint16_t unused_3:1;
0399             uint16_t disable_iosbs_with_bus_reset_status:1;
0400             uint16_t disable_synchronous_backoff:1;
0401             uint16_t unused_6:1;
0402             uint16_t synchronous_backoff_reporting:1;
0403             uint16_t disable_reselection_fairness:1;
0404             uint16_t unused_9:1;
0405             uint16_t unused_10:1;
0406             uint16_t unused_11:1;
0407             uint16_t unused_12:1;
0408             uint16_t unused_13:1;
0409             uint16_t unused_14:1;
0410             uint16_t unused_15:1;
0411         } f;
0412     } firmware_feature; /* 20, 21 */
0413 
0414     uint16_t unused_22; /* 22, 23 */
0415 
0416     struct {
0417         struct {
0418             uint8_t initiator_id:4;
0419             uint8_t scsi_reset_disable:1;
0420             uint8_t scsi_bus_size:1;
0421             uint8_t scsi_bus_type:1;
0422             uint8_t unused_7:1;
0423         } config_1; /* 24 */
0424 
0425         uint8_t bus_reset_delay;    /* 25 */
0426         uint8_t retry_count;    /* 26 */
0427         uint8_t retry_delay;    /* 27 */
0428 
0429         struct {
0430             uint8_t async_data_setup_time:4;
0431             uint8_t req_ack_active_negation:1;
0432             uint8_t data_line_active_negation:1;
0433             uint8_t unused_6:1;
0434             uint8_t unused_7:1;
0435         } config_2; /* 28 */
0436 
0437         uint8_t unused_29;  /* 29 */
0438 
0439         uint16_t selection_timeout; /* 30, 31 */
0440         uint16_t max_queue_depth;   /* 32, 33 */
0441 
0442         uint16_t unused_34; /* 34, 35 */
0443         uint16_t unused_36; /* 36, 37 */
0444         uint16_t unused_38; /* 38, 39 */
0445 
0446         struct {
0447             struct {
0448                 uint8_t renegotiate_on_error:1;
0449                 uint8_t stop_queue_on_check:1;
0450                 uint8_t auto_request_sense:1;
0451                 uint8_t tag_queuing:1;
0452                 uint8_t enable_sync:1;
0453                 uint8_t enable_wide:1;
0454                 uint8_t parity_checking:1;
0455                 uint8_t disconnect_allowed:1;
0456             } parameter;    /* 40 */
0457 
0458             uint8_t execution_throttle; /* 41 */
0459             uint8_t sync_period;    /* 42 */
0460 
0461             union {     /* 43 */
0462                 uint8_t flags_43;
0463                 struct {
0464                     uint8_t sync_offset:4;
0465                     uint8_t device_enable:1;
0466                     uint8_t lun_disable:1;
0467                     uint8_t unused_6:1;
0468                     uint8_t unused_7:1;
0469                 } flags1x80;
0470                 struct {
0471                     uint8_t sync_offset:5;
0472                     uint8_t device_enable:1;
0473                     uint8_t unused_6:1;
0474                     uint8_t unused_7:1;
0475                 } flags1x160;
0476             } flags;
0477             union { /* PPR flags for the 1x160 controllers */
0478                 uint8_t unused_44;
0479                 struct {
0480                     uint8_t ppr_options:4;
0481                     uint8_t ppr_bus_width:2;
0482                     uint8_t unused_8:1;
0483                     uint8_t enable_ppr:1;
0484                 } flags;    /* 44 */
0485             } ppr_1x160;
0486             uint8_t unused_45;  /* 45 */
0487         } target[MAX_TARGETS];
0488     } bus[MAX_BUSES];
0489 
0490     uint16_t unused_248;    /* 248, 249 */
0491 
0492     uint16_t subsystem_id[2];   /* 250, 251, 252, 253 */
0493 
0494     union {             /* 254 */
0495         uint8_t unused_254;
0496         uint8_t system_id_pointer;
0497     } sysid_1x160;
0498 
0499     uint8_t chksum;     /* 255 */
0500 };
0501 
0502 /*
0503  * ISP queue - command entry structure definition.
0504  */
0505 #define MAX_CMDSZ   12      /* SCSI maximum CDB size. */
0506 struct cmd_entry {
0507     uint8_t entry_type;     /* Entry type. */
0508 #define COMMAND_TYPE    1       /* Command entry */
0509     uint8_t entry_count;        /* Entry count. */
0510     uint8_t sys_define;     /* System defined. */
0511     uint8_t entry_status;       /* Entry Status. */
0512     __le32 handle;          /* System handle. */
0513     uint8_t lun;            /* SCSI LUN */
0514     uint8_t target;         /* SCSI ID */
0515     __le16 cdb_len;         /* SCSI command length. */
0516     __le16 control_flags;       /* Control flags. */
0517     __le16 reserved;
0518     __le16 timeout;         /* Command timeout. */
0519     __le16 dseg_count;      /* Data segment count. */
0520     uint8_t scsi_cdb[MAX_CMDSZ];    /* SCSI command words. */
0521     __le32 dseg_0_address;      /* Data segment 0 address. */
0522     __le32 dseg_0_length;       /* Data segment 0 length. */
0523     __le32 dseg_1_address;      /* Data segment 1 address. */
0524     __le32 dseg_1_length;       /* Data segment 1 length. */
0525     __le32 dseg_2_address;      /* Data segment 2 address. */
0526     __le32 dseg_2_length;       /* Data segment 2 length. */
0527     __le32 dseg_3_address;      /* Data segment 3 address. */
0528     __le32 dseg_3_length;       /* Data segment 3 length. */
0529 };
0530 
0531 /*
0532  * ISP queue - continuation entry structure definition.
0533  */
0534 struct cont_entry {
0535     uint8_t entry_type;     /* Entry type. */
0536 #define CONTINUE_TYPE   2       /* Continuation entry. */
0537     uint8_t entry_count;        /* Entry count. */
0538     uint8_t sys_define;     /* System defined. */
0539     uint8_t entry_status;       /* Entry Status. */
0540     __le32 reserved;        /* Reserved */
0541     __le32 dseg_0_address;      /* Data segment 0 address. */
0542     __le32 dseg_0_length;       /* Data segment 0 length. */
0543     __le32 dseg_1_address;      /* Data segment 1 address. */
0544     __le32 dseg_1_length;       /* Data segment 1 length. */
0545     __le32 dseg_2_address;      /* Data segment 2 address. */
0546     __le32 dseg_2_length;       /* Data segment 2 length. */
0547     __le32 dseg_3_address;      /* Data segment 3 address. */
0548     __le32 dseg_3_length;       /* Data segment 3 length. */
0549     __le32 dseg_4_address;      /* Data segment 4 address. */
0550     __le32 dseg_4_length;       /* Data segment 4 length. */
0551     __le32 dseg_5_address;      /* Data segment 5 address. */
0552     __le32 dseg_5_length;       /* Data segment 5 length. */
0553     __le32 dseg_6_address;      /* Data segment 6 address. */
0554     __le32 dseg_6_length;       /* Data segment 6 length. */
0555 };
0556 
0557 /*
0558  * ISP queue - status entry structure definition.
0559  */
0560 struct response {
0561     uint8_t entry_type; /* Entry type. */
0562 #define STATUS_TYPE     3   /* Status entry. */
0563     uint8_t entry_count;    /* Entry count. */
0564     uint8_t sys_define; /* System defined. */
0565     uint8_t entry_status;   /* Entry Status. */
0566 #define RF_CONT         BIT_0   /* Continuation. */
0567 #define RF_FULL         BIT_1   /* Full */
0568 #define RF_BAD_HEADER   BIT_2   /* Bad header. */
0569 #define RF_BAD_PAYLOAD  BIT_3   /* Bad payload. */
0570     __le32 handle;      /* System handle. */
0571     __le16 scsi_status; /* SCSI status. */
0572     __le16 comp_status; /* Completion status. */
0573     __le16 state_flags; /* State flags. */
0574 #define SF_TRANSFER_CMPL    BIT_14  /* Transfer Complete. */
0575 #define SF_GOT_SENSE        BIT_13  /* Got Sense */
0576 #define SF_GOT_STATUS       BIT_12  /* Got Status */
0577 #define SF_TRANSFERRED_DATA BIT_11  /* Transferred data */
0578 #define SF_SENT_CDB     BIT_10  /* Send CDB */
0579 #define SF_GOT_TARGET       BIT_9   /*  */
0580 #define SF_GOT_BUS      BIT_8   /*  */
0581     __le16 status_flags;    /* Status flags. */
0582     __le16 time;        /* Time. */
0583     __le16 req_sense_length;/* Request sense data length. */
0584     __le32 residual_length; /* Residual transfer length. */
0585     __le16 reserved[4];
0586     uint8_t req_sense_data[32]; /* Request sense data. */
0587 };
0588 
0589 /*
0590  * ISP queue - marker entry structure definition.
0591  */
0592 struct mrk_entry {
0593     uint8_t entry_type; /* Entry type. */
0594 #define MARKER_TYPE     4   /* Marker entry. */
0595     uint8_t entry_count;    /* Entry count. */
0596     uint8_t sys_define; /* System defined. */
0597     uint8_t entry_status;   /* Entry Status. */
0598     __le32 reserved;
0599     uint8_t lun;        /* SCSI LUN */
0600     uint8_t target;     /* SCSI ID */
0601     uint8_t modifier;   /* Modifier (7-0). */
0602 #define MK_SYNC_ID_LUN      0   /* Synchronize ID/LUN */
0603 #define MK_SYNC_ID          1   /* Synchronize ID */
0604 #define MK_SYNC_ALL         2   /* Synchronize all ID/LUN */
0605     uint8_t reserved_1[53];
0606 };
0607 
0608 /*
0609  * ISP queue - extended command entry structure definition.
0610  *
0611  * Unused by the driver!
0612  */
0613 struct ecmd_entry {
0614     uint8_t entry_type; /* Entry type. */
0615 #define EXTENDED_CMD_TYPE  5    /* Extended command entry. */
0616     uint8_t entry_count;    /* Entry count. */
0617     uint8_t sys_define; /* System defined. */
0618     uint8_t entry_status;   /* Entry Status. */
0619     uint32_t handle;    /* System handle. */
0620     uint8_t lun;        /* SCSI LUN */
0621     uint8_t target;     /* SCSI ID */
0622     __le16 cdb_len;     /* SCSI command length. */
0623     __le16 control_flags;   /* Control flags. */
0624     __le16 reserved;
0625     __le16 timeout;     /* Command timeout. */
0626     __le16 dseg_count;  /* Data segment count. */
0627     uint8_t scsi_cdb[88];   /* SCSI command words. */
0628 };
0629 
0630 /*
0631  * ISP queue - 64-Bit addressing, command entry structure definition.
0632  */
0633 typedef struct {
0634     uint8_t entry_type; /* Entry type. */
0635 #define COMMAND_A64_TYPE 9  /* Command A64 entry */
0636     uint8_t entry_count;    /* Entry count. */
0637     uint8_t sys_define; /* System defined. */
0638     uint8_t entry_status;   /* Entry Status. */
0639     __le32 handle;  /* System handle. */
0640     uint8_t lun;        /* SCSI LUN */
0641     uint8_t target;     /* SCSI ID */
0642     __le16 cdb_len; /* SCSI command length. */
0643     __le16 control_flags;   /* Control flags. */
0644     __le16 reserved;
0645     __le16 timeout; /* Command timeout. */
0646     __le16 dseg_count;  /* Data segment count. */
0647     uint8_t scsi_cdb[MAX_CMDSZ];    /* SCSI command words. */
0648     __le32 reserved_1[2];   /* unused */
0649     __le32 dseg_0_address[2];   /* Data segment 0 address. */
0650     __le32 dseg_0_length;   /* Data segment 0 length. */
0651     __le32 dseg_1_address[2];   /* Data segment 1 address. */
0652     __le32 dseg_1_length;   /* Data segment 1 length. */
0653 } cmd_a64_entry_t, request_t;
0654 
0655 /*
0656  * ISP queue - 64-Bit addressing, continuation entry structure definition.
0657  */
0658 struct cont_a64_entry {
0659     uint8_t entry_type; /* Entry type. */
0660 #define CONTINUE_A64_TYPE 0xA   /* Continuation A64 entry. */
0661     uint8_t entry_count;    /* Entry count. */
0662     uint8_t sys_define; /* System defined. */
0663     uint8_t entry_status;   /* Entry Status. */
0664     __le32 dseg_0_address[2];   /* Data segment 0 address. */
0665     __le32 dseg_0_length;       /* Data segment 0 length. */
0666     __le32 dseg_1_address[2];   /* Data segment 1 address. */
0667     __le32 dseg_1_length;       /* Data segment 1 length. */
0668     __le32 dseg_2_address[2];   /* Data segment 2 address. */
0669     __le32 dseg_2_length;       /* Data segment 2 length. */
0670     __le32 dseg_3_address[2];   /* Data segment 3 address. */
0671     __le32 dseg_3_length;       /* Data segment 3 length. */
0672     __le32 dseg_4_address[2];   /* Data segment 4 address. */
0673     __le32 dseg_4_length;       /* Data segment 4 length. */
0674 };
0675 
0676 /*
0677  * ISP queue - enable LUN entry structure definition.
0678  */
0679 struct elun_entry {
0680     uint8_t entry_type; /* Entry type. */
0681 #define ENABLE_LUN_TYPE 0xB /* Enable LUN entry. */
0682     uint8_t entry_count;    /* Entry count. */
0683     uint8_t reserved_1;
0684     uint8_t entry_status;   /* Entry Status not used. */
0685     __le32 reserved_2;
0686     __le16 lun;     /* Bit 15 is bus number. */
0687     __le16 reserved_4;
0688     __le32 option_flags;
0689     uint8_t status;
0690     uint8_t reserved_5;
0691     uint8_t command_count;  /* Number of ATIOs allocated. */
0692     uint8_t immed_notify_count; /* Number of Immediate Notify */
0693     /* entries allocated. */
0694     uint8_t group_6_length; /* SCSI CDB length for group 6 */
0695     /* commands (2-26). */
0696     uint8_t group_7_length; /* SCSI CDB length for group 7 */
0697     /* commands (2-26). */
0698     __le16 timeout;     /* 0 = 30 seconds, 0xFFFF = disable */
0699     __le16 reserved_6[20];
0700 };
0701 
0702 /*
0703  * ISP queue - modify LUN entry structure definition.
0704  *
0705  * Unused by the driver!
0706  */
0707 struct modify_lun_entry {
0708     uint8_t entry_type; /* Entry type. */
0709 #define MODIFY_LUN_TYPE 0xC /* Modify LUN entry. */
0710     uint8_t entry_count;    /* Entry count. */
0711     uint8_t reserved_1;
0712     uint8_t entry_status;   /* Entry Status. */
0713     __le32 reserved_2;
0714     uint8_t lun;        /* SCSI LUN */
0715     uint8_t reserved_3;
0716     uint8_t operators;
0717     uint8_t reserved_4;
0718     __le32 option_flags;
0719     uint8_t status;
0720     uint8_t reserved_5;
0721     uint8_t command_count;  /* Number of ATIOs allocated. */
0722     uint8_t immed_notify_count; /* Number of Immediate Notify */
0723     /* entries allocated. */
0724     __le16 reserved_6;
0725     __le16 timeout;     /* 0 = 30 seconds, 0xFFFF = disable */
0726     __le16 reserved_7[20];
0727 };
0728 
0729 /*
0730  * ISP queue - immediate notify entry structure definition.
0731  */
0732 struct notify_entry {
0733     uint8_t entry_type; /* Entry type. */
0734 #define IMMED_NOTIFY_TYPE 0xD   /* Immediate notify entry. */
0735     uint8_t entry_count;    /* Entry count. */
0736     uint8_t reserved_1;
0737     uint8_t entry_status;   /* Entry Status. */
0738     __le32 reserved_2;
0739     uint8_t lun;
0740     uint8_t initiator_id;
0741     uint8_t reserved_3;
0742     uint8_t target_id;
0743     __le32 option_flags;
0744     uint8_t status;
0745     uint8_t reserved_4;
0746     uint8_t tag_value;  /* Received queue tag message value */
0747     uint8_t tag_type;   /* Received queue tag message type */
0748     /* entries allocated. */
0749     __le16 seq_id;
0750     uint8_t scsi_msg[8];    /* SCSI message not handled by ISP */
0751     __le16 reserved_5[8];
0752     uint8_t sense_data[18];
0753 };
0754 
0755 /*
0756  * ISP queue - notify acknowledge entry structure definition.
0757  */
0758 struct nack_entry {
0759     uint8_t entry_type; /* Entry type. */
0760 #define NOTIFY_ACK_TYPE 0xE /* Notify acknowledge entry. */
0761     uint8_t entry_count;    /* Entry count. */
0762     uint8_t reserved_1;
0763     uint8_t entry_status;   /* Entry Status. */
0764     __le32 reserved_2;
0765     uint8_t lun;
0766     uint8_t initiator_id;
0767     uint8_t reserved_3;
0768     uint8_t target_id;
0769     __le32 option_flags;
0770     uint8_t status;
0771     uint8_t event;
0772     __le16 seq_id;
0773     __le16 reserved_4[22];
0774 };
0775 
0776 /*
0777  * ISP queue - Accept Target I/O (ATIO) entry structure definition.
0778  */
0779 struct atio_entry {
0780     uint8_t entry_type; /* Entry type. */
0781 #define ACCEPT_TGT_IO_TYPE 6    /* Accept target I/O entry. */
0782     uint8_t entry_count;    /* Entry count. */
0783     uint8_t reserved_1;
0784     uint8_t entry_status;   /* Entry Status. */
0785     __le32 reserved_2;
0786     uint8_t lun;
0787     uint8_t initiator_id;
0788     uint8_t cdb_len;
0789     uint8_t target_id;
0790     __le32 option_flags;
0791     uint8_t status;
0792     uint8_t scsi_status;
0793     uint8_t tag_value;  /* Received queue tag message value */
0794     uint8_t tag_type;   /* Received queue tag message type */
0795     uint8_t cdb[26];
0796     uint8_t sense_data[18];
0797 };
0798 
0799 /*
0800  * ISP queue - Continue Target I/O (CTIO) entry structure definition.
0801  */
0802 struct ctio_entry {
0803     uint8_t entry_type; /* Entry type. */
0804 #define CONTINUE_TGT_IO_TYPE 7  /* CTIO entry */
0805     uint8_t entry_count;    /* Entry count. */
0806     uint8_t reserved_1;
0807     uint8_t entry_status;   /* Entry Status. */
0808     __le32 reserved_2;
0809     uint8_t lun;        /* SCSI LUN */
0810     uint8_t initiator_id;
0811     uint8_t reserved_3;
0812     uint8_t target_id;
0813     __le32 option_flags;
0814     uint8_t status;
0815     uint8_t scsi_status;
0816     uint8_t tag_value;  /* Received queue tag message value */
0817     uint8_t tag_type;   /* Received queue tag message type */
0818     __le32 transfer_length;
0819     __le32 residual;
0820     __le16 timeout;     /* 0 = 30 seconds, 0xFFFF = disable */
0821     __le16 dseg_count;  /* Data segment count. */
0822     __le32 dseg_0_address;  /* Data segment 0 address. */
0823     __le32 dseg_0_length;   /* Data segment 0 length. */
0824     __le32 dseg_1_address;  /* Data segment 1 address. */
0825     __le32 dseg_1_length;   /* Data segment 1 length. */
0826     __le32 dseg_2_address;  /* Data segment 2 address. */
0827     __le32 dseg_2_length;   /* Data segment 2 length. */
0828     __le32 dseg_3_address;  /* Data segment 3 address. */
0829     __le32 dseg_3_length;   /* Data segment 3 length. */
0830 };
0831 
0832 /*
0833  * ISP queue - CTIO returned entry structure definition.
0834  */
0835 struct ctio_ret_entry {
0836     uint8_t entry_type; /* Entry type. */
0837 #define CTIO_RET_TYPE   7   /* CTIO return entry */
0838     uint8_t entry_count;    /* Entry count. */
0839     uint8_t reserved_1;
0840     uint8_t entry_status;   /* Entry Status. */
0841     __le32 reserved_2;
0842     uint8_t lun;        /* SCSI LUN */
0843     uint8_t initiator_id;
0844     uint8_t reserved_3;
0845     uint8_t target_id;
0846     __le32 option_flags;
0847     uint8_t status;
0848     uint8_t scsi_status;
0849     uint8_t tag_value;  /* Received queue tag message value */
0850     uint8_t tag_type;   /* Received queue tag message type */
0851     __le32 transfer_length;
0852     __le32 residual;
0853     __le16 timeout;     /* 0 = 30 seconds, 0xFFFF = disable */
0854     __le16 dseg_count;  /* Data segment count. */
0855     __le32 dseg_0_address;  /* Data segment 0 address. */
0856     __le32 dseg_0_length;   /* Data segment 0 length. */
0857     __le32 dseg_1_address;  /* Data segment 1 address. */
0858     __le16 dseg_1_length;   /* Data segment 1 length. */
0859     uint8_t sense_data[18];
0860 };
0861 
0862 /*
0863  * ISP queue - CTIO A64 entry structure definition.
0864  */
0865 struct ctio_a64_entry {
0866     uint8_t entry_type; /* Entry type. */
0867 #define CTIO_A64_TYPE 0xF   /* CTIO A64 entry */
0868     uint8_t entry_count;    /* Entry count. */
0869     uint8_t reserved_1;
0870     uint8_t entry_status;   /* Entry Status. */
0871     __le32 reserved_2;
0872     uint8_t lun;        /* SCSI LUN */
0873     uint8_t initiator_id;
0874     uint8_t reserved_3;
0875     uint8_t target_id;
0876     __le32 option_flags;
0877     uint8_t status;
0878     uint8_t scsi_status;
0879     uint8_t tag_value;  /* Received queue tag message value */
0880     uint8_t tag_type;   /* Received queue tag message type */
0881     __le32 transfer_length;
0882     __le32 residual;
0883     __le16 timeout;     /* 0 = 30 seconds, 0xFFFF = disable */
0884     __le16 dseg_count;  /* Data segment count. */
0885     __le32 reserved_4[2];
0886     __le32 dseg_0_address[2];/* Data segment 0 address. */
0887     __le32 dseg_0_length;   /* Data segment 0 length. */
0888     __le32 dseg_1_address[2];/* Data segment 1 address. */
0889     __le32 dseg_1_length;   /* Data segment 1 length. */
0890 };
0891 
0892 /*
0893  * ISP queue - CTIO returned entry structure definition.
0894  */
0895 struct ctio_a64_ret_entry {
0896     uint8_t entry_type; /* Entry type. */
0897 #define CTIO_A64_RET_TYPE 0xF   /* CTIO A64 returned entry */
0898     uint8_t entry_count;    /* Entry count. */
0899     uint8_t reserved_1;
0900     uint8_t entry_status;   /* Entry Status. */
0901     __le32 reserved_2;
0902     uint8_t lun;        /* SCSI LUN */
0903     uint8_t initiator_id;
0904     uint8_t reserved_3;
0905     uint8_t target_id;
0906     __le32 option_flags;
0907     uint8_t status;
0908     uint8_t scsi_status;
0909     uint8_t tag_value;  /* Received queue tag message value */
0910     uint8_t tag_type;   /* Received queue tag message type */
0911     __le32 transfer_length;
0912     __le32 residual;
0913     __le16 timeout;     /* 0 = 30 seconds, 0xFFFF = disable */
0914     __le16 dseg_count;  /* Data segment count. */
0915     __le16 reserved_4[7];
0916     uint8_t sense_data[18];
0917 };
0918 
0919 /*
0920  * ISP request and response queue entry sizes
0921  */
0922 #define RESPONSE_ENTRY_SIZE (sizeof(struct response))
0923 #define REQUEST_ENTRY_SIZE  (sizeof(request_t))
0924 
0925 /*
0926  * ISP status entry - completion status definitions.
0927  */
0928 #define CS_COMPLETE         0x0 /* No errors */
0929 #define CS_INCOMPLETE       0x1 /* Incomplete transfer of cmd. */
0930 #define CS_DMA              0x2 /* A DMA direction error. */
0931 #define CS_TRANSPORT        0x3 /* Transport error. */
0932 #define CS_RESET            0x4 /* SCSI bus reset occurred */
0933 #define CS_ABORTED          0x5 /* System aborted command. */
0934 #define CS_TIMEOUT          0x6 /* Timeout error. */
0935 #define CS_DATA_OVERRUN     0x7 /* Data overrun. */
0936 #define CS_COMMAND_OVERRUN  0x8 /* Command Overrun. */
0937 #define CS_STATUS_OVERRUN   0x9 /* Status Overrun. */
0938 #define CS_BAD_MSG          0xA /* Bad msg after status phase. */
0939 #define CS_NO_MSG_OUT       0xB /* No msg out after selection. */
0940 #define CS_EXTENDED_ID      0xC /* Extended ID failed. */
0941 #define CS_IDE_MSG          0xD /* Target rejected IDE msg. */
0942 #define CS_ABORT_MSG        0xE /* Target rejected abort msg. */
0943 #define CS_REJECT_MSG       0xF /* Target rejected reject msg. */
0944 #define CS_NOP_MSG          0x10    /* Target rejected NOP msg. */
0945 #define CS_PARITY_MSG       0x11    /* Target rejected parity msg. */
0946 #define CS_DEV_RESET_MSG    0x12    /* Target rejected dev rst msg. */
0947 #define CS_ID_MSG           0x13    /* Target rejected ID msg. */
0948 #define CS_FREE             0x14    /* Unexpected bus free. */
0949 #define CS_DATA_UNDERRUN    0x15    /* Data Underrun. */
0950 #define CS_TRANACTION_1     0x18    /* Transaction error 1 */
0951 #define CS_TRANACTION_2     0x19    /* Transaction error 2 */
0952 #define CS_TRANACTION_3     0x1a    /* Transaction error 3 */
0953 #define CS_INV_ENTRY_TYPE   0x1b    /* Invalid entry type */
0954 #define CS_DEV_QUEUE_FULL   0x1c    /* Device queue full */
0955 #define CS_PHASED_SKIPPED   0x1d    /* SCSI phase skipped */
0956 #define CS_ARS_FAILED       0x1e    /* ARS failed */
0957 #define CS_LVD_BUS_ERROR    0x21    /* LVD bus error */
0958 #define CS_BAD_PAYLOAD      0x80    /* Driver defined */
0959 #define CS_UNKNOWN          0x81    /* Driver defined */
0960 #define CS_RETRY            0x82    /* Driver defined */
0961 
0962 /*
0963  * ISP target entries - Option flags bit definitions.
0964  */
0965 #define OF_ENABLE_TAG       BIT_1   /* Tagged queue action enable */
0966 #define OF_DATA_IN          BIT_6   /* Data in to initiator */
0967                     /*  (data from target to initiator) */
0968 #define OF_DATA_OUT         BIT_7   /* Data out from initiator */
0969                     /*  (data from initiator to target) */
0970 #define OF_NO_DATA          (BIT_7 | BIT_6)
0971 #define OF_DISC_DISABLED    BIT_15  /* Disconnects disabled */
0972 #define OF_DISABLE_SDP      BIT_24  /* Disable sending save data ptr */
0973 #define OF_SEND_RDP         BIT_26  /* Send restore data pointers msg */
0974 #define OF_FORCE_DISC       BIT_30  /* Disconnects mandatory */
0975 #define OF_SSTS             BIT_31  /* Send SCSI status */
0976 
0977 
0978 /*
0979  * BUS parameters/settings structure - UNUSED
0980  */
0981 struct bus_param {
0982     uint8_t id;     /* Host adapter SCSI id */
0983     uint8_t bus_reset_delay;    /* SCSI bus reset delay. */
0984     uint8_t failed_reset_count; /* number of time reset failed */
0985     uint8_t unused;
0986     uint16_t device_enables;    /* Device enable bits. */
0987     uint16_t lun_disables;  /* LUN disable bits. */
0988     uint16_t qtag_enables;  /* Tag queue enables. */
0989     uint16_t hiwat;     /* High water mark per device. */
0990     uint8_t reset_marker:1;
0991     uint8_t disable_scsi_reset:1;
0992     uint8_t scsi_bus_dead:1;    /* SCSI Bus is Dead, when 5 back to back resets failed */
0993 };
0994 
0995 
0996 struct qla_driver_setup {
0997     uint32_t no_sync:1;
0998     uint32_t no_wide:1;
0999     uint32_t no_ppr:1;
1000     uint32_t no_nvram:1;
1001     uint16_t sync_mask;
1002     uint16_t wide_mask;
1003     uint16_t ppr_mask;
1004 };
1005 
1006 
1007 /*
1008  * Linux Host Adapter structure
1009  */
1010 struct scsi_qla_host {
1011     /* Linux adapter configuration data */
1012     struct Scsi_Host *host; /* pointer to host data */
1013     struct scsi_qla_host *next;
1014     struct device_reg __iomem *iobase;  /* Base Memory-mapped I/O address */
1015 
1016     unsigned char __iomem *mmpbase; /* memory mapped address */
1017     unsigned long host_no;
1018     struct pci_dev *pdev;
1019     uint8_t devnum;
1020     uint8_t revision;
1021     uint8_t ports;
1022 
1023     unsigned long actthreads;
1024     unsigned long isr_count;    /* Interrupt count */
1025     unsigned long spurious_int;
1026 
1027     /* Outstandings ISP commands. */
1028     struct srb *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
1029 
1030     /* BUS configuration data */
1031     struct bus_param bus_settings[MAX_BUSES];
1032 
1033     /* Received ISP mailbox data. */
1034     volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
1035 
1036     dma_addr_t request_dma;     /* Physical Address */
1037     request_t *request_ring;    /* Base virtual address */
1038     request_t *request_ring_ptr;    /* Current address. */
1039     uint16_t req_ring_index;    /* Current index. */
1040     uint16_t req_q_cnt;     /* Number of available entries. */
1041 
1042     dma_addr_t response_dma;    /* Physical address. */
1043     struct response *response_ring; /* Base virtual address */
1044     struct response *response_ring_ptr; /* Current address. */
1045     uint16_t rsp_ring_index;    /* Current index. */
1046 
1047     struct list_head done_q;    /* Done queue */
1048 
1049     struct completion *mailbox_wait;
1050     struct timer_list mailbox_timer;
1051 
1052     volatile struct {
1053         uint32_t online:1;          /* 0 */
1054         uint32_t reset_marker:1;        /* 1 */
1055         uint32_t disable_host_adapter:1;    /* 2 */
1056         uint32_t reset_active:1;        /* 3 */
1057         uint32_t abort_isp_active:1;        /* 4 */
1058         uint32_t disable_risc_code_load:1;  /* 5 */
1059     } flags;
1060 
1061     struct nvram nvram;
1062     int nvram_valid;
1063 
1064     /* Firmware Info */
1065     unsigned short fwstart; /* start address for F/W   */
1066     unsigned char fwver1;   /* F/W version first char  */
1067     unsigned char fwver2;   /* F/W version second char */
1068     unsigned char fwver3;   /* F/W version third char  */
1069 };
1070 
1071 #endif /* _QLA1280_H */
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