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0001 /*
0002  * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
0003  *
0004  * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
0005  * All rights reserved.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  * notice, this list of conditions, and the following disclaimer,
0012  * without modification.
0013  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
0014  * substantially similar to the "NO WARRANTY" disclaimer below
0015  * ("Disclaimer") and any redistribution must be conditioned upon
0016  * including a substantially similar Disclaimer requirement for further
0017  * binary redistribution.
0018  * 3. Neither the names of the above-listed copyright holders nor the names
0019  * of any contributors may be used to endorse or promote products derived
0020  * from this software without specific prior written permission.
0021  *
0022  * Alternatively, this software may be distributed under the terms of the
0023  * GNU General Public License ("GPL") version 2 as published by the Free
0024  * Software Foundation.
0025  *
0026  * NO WARRANTY
0027  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0028  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0029  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
0030  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0031  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0032  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0033  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0034  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0035  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0036  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGES.
0038  *
0039  */
0040  #include <linux/slab.h>
0041  #include "pm8001_sas.h"
0042  #include "pm80xx_hwi.h"
0043  #include "pm8001_chips.h"
0044  #include "pm8001_ctl.h"
0045 #include "pm80xx_tracepoints.h"
0046 
0047 #define SMP_DIRECT 1
0048 #define SMP_INDIRECT 2
0049 
0050 
0051 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
0052 {
0053     u32 reg_val;
0054     unsigned long start;
0055     pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
0056     /* confirm the setting is written */
0057     start = jiffies + HZ; /* 1 sec */
0058     do {
0059         reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
0060     } while ((reg_val != shift_value) && time_before(jiffies, start));
0061     if (reg_val != shift_value) {
0062         pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MEMBASE_II_SHIFT_REGISTER = 0x%x\n",
0063                reg_val);
0064         return -1;
0065     }
0066     return 0;
0067 }
0068 
0069 static void pm80xx_pci_mem_copy(struct pm8001_hba_info  *pm8001_ha, u32 soffset,
0070                 __le32 *destination,
0071                 u32 dw_count, u32 bus_base_number)
0072 {
0073     u32 index, value, offset;
0074 
0075     for (index = 0; index < dw_count; index += 4, destination++) {
0076         offset = (soffset + index);
0077         if (offset < (64 * 1024)) {
0078             value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
0079             *destination = cpu_to_le32(value);
0080         }
0081     }
0082     return;
0083 }
0084 
0085 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
0086     struct device_attribute *attr, char *buf)
0087 {
0088     struct Scsi_Host *shost = class_to_shost(cdev);
0089     struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
0090     struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
0091     void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
0092     u32 accum_len, reg_val, index, *temp;
0093     u32 status = 1;
0094     unsigned long start;
0095     u8 *direct_data;
0096     char *fatal_error_data = buf;
0097     u32 length_to_read;
0098     u32 offset;
0099 
0100     pm8001_ha->forensic_info.data_buf.direct_data = buf;
0101     if (pm8001_ha->chip_id == chip_8001) {
0102         pm8001_ha->forensic_info.data_buf.direct_data +=
0103             sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
0104             "Not supported for SPC controller");
0105         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
0106             (char *)buf;
0107     }
0108     /* initialize variables for very first call from host application */
0109     if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
0110         pm8001_dbg(pm8001_ha, IO,
0111                "forensic_info TYPE_NON_FATAL..............\n");
0112         direct_data = (u8 *)fatal_error_data;
0113         pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
0114         pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
0115         pm8001_ha->forensic_info.data_buf.direct_offset = 0;
0116         pm8001_ha->forensic_info.data_buf.read_len = 0;
0117         pm8001_ha->forensic_preserved_accumulated_transfer = 0;
0118 
0119         /* Write signature to fatal dump table */
0120         pm8001_mw32(fatal_table_address,
0121                 MPI_FATAL_EDUMP_TABLE_SIGNATURE, 0x1234abcd);
0122 
0123         pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
0124         pm8001_dbg(pm8001_ha, IO, "ossaHwCB: status1 %d\n", status);
0125         pm8001_dbg(pm8001_ha, IO, "ossaHwCB: read_len 0x%x\n",
0126                pm8001_ha->forensic_info.data_buf.read_len);
0127         pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_len 0x%x\n",
0128                pm8001_ha->forensic_info.data_buf.direct_len);
0129         pm8001_dbg(pm8001_ha, IO, "ossaHwCB: direct_offset 0x%x\n",
0130                pm8001_ha->forensic_info.data_buf.direct_offset);
0131     }
0132     if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
0133         /* start to get data */
0134         /* Program the MEMBASE II Shifting Register with 0x00.*/
0135         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
0136                 pm8001_ha->fatal_forensic_shift_offset);
0137         pm8001_ha->forensic_last_offset = 0;
0138         pm8001_ha->forensic_fatal_step = 0;
0139         pm8001_ha->fatal_bar_loc = 0;
0140     }
0141 
0142     /* Read until accum_len is retrieved */
0143     accum_len = pm8001_mr32(fatal_table_address,
0144                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
0145     /* Determine length of data between previously stored transfer length
0146      * and current accumulated transfer length
0147      */
0148     length_to_read =
0149         accum_len - pm8001_ha->forensic_preserved_accumulated_transfer;
0150     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: accum_len 0x%x\n",
0151            accum_len);
0152     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: length_to_read 0x%x\n",
0153            length_to_read);
0154     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: last_offset 0x%x\n",
0155            pm8001_ha->forensic_last_offset);
0156     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: read_len 0x%x\n",
0157            pm8001_ha->forensic_info.data_buf.read_len);
0158     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_len 0x%x\n",
0159            pm8001_ha->forensic_info.data_buf.direct_len);
0160     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv:: direct_offset 0x%x\n",
0161            pm8001_ha->forensic_info.data_buf.direct_offset);
0162 
0163     /* If accumulated length failed to read correctly fail the attempt.*/
0164     if (accum_len == 0xFFFFFFFF) {
0165         pm8001_dbg(pm8001_ha, IO,
0166                "Possible PCI issue 0x%x not expected\n",
0167                accum_len);
0168         return status;
0169     }
0170     /* If accumulated length is zero fail the attempt */
0171     if (accum_len == 0) {
0172         pm8001_ha->forensic_info.data_buf.direct_data +=
0173             sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
0174             "%08x ", 0xFFFFFFFF);
0175         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
0176             (char *)buf;
0177     }
0178     /* Accumulated length is good so start capturing the first data */
0179     temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
0180     if (pm8001_ha->forensic_fatal_step == 0) {
0181 moreData:
0182         /* If data to read is less than SYSFS_OFFSET then reduce the
0183          * length of dataLen
0184          */
0185         if (pm8001_ha->forensic_last_offset + SYSFS_OFFSET
0186                 > length_to_read) {
0187             pm8001_ha->forensic_info.data_buf.direct_len =
0188                 length_to_read -
0189                 pm8001_ha->forensic_last_offset;
0190         } else {
0191             pm8001_ha->forensic_info.data_buf.direct_len =
0192                 SYSFS_OFFSET;
0193         }
0194         if (pm8001_ha->forensic_info.data_buf.direct_data) {
0195             /* Data is in bar, copy to host memory */
0196             pm80xx_pci_mem_copy(pm8001_ha,
0197             pm8001_ha->fatal_bar_loc,
0198             pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
0199             pm8001_ha->forensic_info.data_buf.direct_len, 1);
0200         }
0201         pm8001_ha->fatal_bar_loc +=
0202             pm8001_ha->forensic_info.data_buf.direct_len;
0203         pm8001_ha->forensic_info.data_buf.direct_offset +=
0204             pm8001_ha->forensic_info.data_buf.direct_len;
0205         pm8001_ha->forensic_last_offset +=
0206             pm8001_ha->forensic_info.data_buf.direct_len;
0207         pm8001_ha->forensic_info.data_buf.read_len =
0208             pm8001_ha->forensic_info.data_buf.direct_len;
0209 
0210         if (pm8001_ha->forensic_last_offset  >= length_to_read) {
0211             pm8001_ha->forensic_info.data_buf.direct_data +=
0212             sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
0213                 "%08x ", 3);
0214             for (index = 0; index <
0215                 (pm8001_ha->forensic_info.data_buf.direct_len
0216                  / 4); index++) {
0217                 pm8001_ha->forensic_info.data_buf.direct_data +=
0218                 sprintf(
0219                 pm8001_ha->forensic_info.data_buf.direct_data,
0220                 "%08x ", *(temp + index));
0221             }
0222 
0223             pm8001_ha->fatal_bar_loc = 0;
0224             pm8001_ha->forensic_fatal_step = 1;
0225             pm8001_ha->fatal_forensic_shift_offset = 0;
0226             pm8001_ha->forensic_last_offset = 0;
0227             status = 0;
0228             offset = (int)
0229             ((char *)pm8001_ha->forensic_info.data_buf.direct_data
0230             - (char *)buf);
0231             pm8001_dbg(pm8001_ha, IO,
0232                    "get_fatal_spcv:return1 0x%x\n", offset);
0233             return (char *)pm8001_ha->
0234                 forensic_info.data_buf.direct_data -
0235                 (char *)buf;
0236         }
0237         if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
0238             pm8001_ha->forensic_info.data_buf.direct_data +=
0239                 sprintf(pm8001_ha->
0240                     forensic_info.data_buf.direct_data,
0241                     "%08x ", 2);
0242             for (index = 0; index <
0243                 (pm8001_ha->forensic_info.data_buf.direct_len
0244                  / 4); index++) {
0245                 pm8001_ha->forensic_info.data_buf.direct_data
0246                     += sprintf(pm8001_ha->
0247                     forensic_info.data_buf.direct_data,
0248                     "%08x ", *(temp + index));
0249             }
0250             status = 0;
0251             offset = (int)
0252             ((char *)pm8001_ha->forensic_info.data_buf.direct_data
0253             - (char *)buf);
0254             pm8001_dbg(pm8001_ha, IO,
0255                    "get_fatal_spcv:return2 0x%x\n", offset);
0256             return (char *)pm8001_ha->
0257                 forensic_info.data_buf.direct_data -
0258                 (char *)buf;
0259         }
0260 
0261         /* Increment the MEMBASE II Shifting Register value by 0x100.*/
0262         pm8001_ha->forensic_info.data_buf.direct_data +=
0263             sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
0264                 "%08x ", 2);
0265         for (index = 0; index <
0266             (pm8001_ha->forensic_info.data_buf.direct_len
0267              / 4) ; index++) {
0268             pm8001_ha->forensic_info.data_buf.direct_data +=
0269                 sprintf(pm8001_ha->
0270                 forensic_info.data_buf.direct_data,
0271                 "%08x ", *(temp + index));
0272         }
0273         pm8001_ha->fatal_forensic_shift_offset += 0x100;
0274         pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
0275             pm8001_ha->fatal_forensic_shift_offset);
0276         pm8001_ha->fatal_bar_loc = 0;
0277         status = 0;
0278         offset = (int)
0279             ((char *)pm8001_ha->forensic_info.data_buf.direct_data
0280             - (char *)buf);
0281         pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return3 0x%x\n",
0282                offset);
0283         return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
0284             (char *)buf;
0285     }
0286     if (pm8001_ha->forensic_fatal_step == 1) {
0287         /* store previous accumulated length before triggering next
0288          * accumulated length update
0289          */
0290         pm8001_ha->forensic_preserved_accumulated_transfer =
0291             pm8001_mr32(fatal_table_address,
0292             MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
0293 
0294         /* continue capturing the fatal log until Dump status is 0x3 */
0295         if (pm8001_mr32(fatal_table_address,
0296             MPI_FATAL_EDUMP_TABLE_STATUS) <
0297             MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
0298 
0299             /* reset fddstat bit by writing to zero*/
0300             pm8001_mw32(fatal_table_address,
0301                     MPI_FATAL_EDUMP_TABLE_STATUS, 0x0);
0302 
0303             /* set dump control value to '1' so that new data will
0304              * be transferred to shared memory
0305              */
0306             pm8001_mw32(fatal_table_address,
0307                 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
0308                 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
0309 
0310             /*Poll FDDHSHK  until clear */
0311             start = jiffies + (2 * HZ); /* 2 sec */
0312 
0313             do {
0314                 reg_val = pm8001_mr32(fatal_table_address,
0315                     MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
0316             } while ((reg_val) && time_before(jiffies, start));
0317 
0318             if (reg_val != 0) {
0319                 pm8001_dbg(pm8001_ha, FAIL,
0320                        "TIMEOUT:MPI_FATAL_EDUMP_TABLE_HDSHAKE 0x%x\n",
0321                        reg_val);
0322                    /* Fail the dump if a timeout occurs */
0323                 pm8001_ha->forensic_info.data_buf.direct_data +=
0324                 sprintf(
0325                 pm8001_ha->forensic_info.data_buf.direct_data,
0326                 "%08x ", 0xFFFFFFFF);
0327                 return((char *)
0328                 pm8001_ha->forensic_info.data_buf.direct_data
0329                 - (char *)buf);
0330             }
0331             /* Poll status register until set to 2 or
0332              * 3 for up to 2 seconds
0333              */
0334             start = jiffies + (2 * HZ); /* 2 sec */
0335 
0336             do {
0337                 reg_val = pm8001_mr32(fatal_table_address,
0338                     MPI_FATAL_EDUMP_TABLE_STATUS);
0339             } while (((reg_val != 2) && (reg_val != 3)) &&
0340                     time_before(jiffies, start));
0341 
0342             if (reg_val < 2) {
0343                 pm8001_dbg(pm8001_ha, FAIL,
0344                        "TIMEOUT:MPI_FATAL_EDUMP_TABLE_STATUS = 0x%x\n",
0345                        reg_val);
0346                 /* Fail the dump if a timeout occurs */
0347                 pm8001_ha->forensic_info.data_buf.direct_data +=
0348                 sprintf(
0349                 pm8001_ha->forensic_info.data_buf.direct_data,
0350                 "%08x ", 0xFFFFFFFF);
0351                 return((char *)pm8001_ha->forensic_info.data_buf.direct_data -
0352                         (char *)buf);
0353             }
0354     /* reset fatal_forensic_shift_offset back to zero and reset MEMBASE 2 register to zero */
0355             pm8001_ha->fatal_forensic_shift_offset = 0; /* location in 64k region */
0356             pm8001_cw32(pm8001_ha, 0,
0357                     MEMBASE_II_SHIFT_REGISTER,
0358                     pm8001_ha->fatal_forensic_shift_offset);
0359         }
0360         /* Read the next block of the debug data.*/
0361         length_to_read = pm8001_mr32(fatal_table_address,
0362         MPI_FATAL_EDUMP_TABLE_ACCUM_LEN) -
0363         pm8001_ha->forensic_preserved_accumulated_transfer;
0364         if (length_to_read != 0x0) {
0365             pm8001_ha->forensic_fatal_step = 0;
0366             goto moreData;
0367         } else {
0368             pm8001_ha->forensic_info.data_buf.direct_data +=
0369             sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
0370                 "%08x ", 4);
0371             pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
0372             pm8001_ha->forensic_info.data_buf.direct_len =  0;
0373             pm8001_ha->forensic_info.data_buf.direct_offset = 0;
0374             pm8001_ha->forensic_info.data_buf.read_len = 0;
0375         }
0376     }
0377     offset = (int)((char *)pm8001_ha->forensic_info.data_buf.direct_data
0378             - (char *)buf);
0379     pm8001_dbg(pm8001_ha, IO, "get_fatal_spcv: return4 0x%x\n", offset);
0380     return ((char *)pm8001_ha->forensic_info.data_buf.direct_data -
0381         (char *)buf);
0382 }
0383 
0384 /* pm80xx_get_non_fatal_dump - dump the nonfatal data from the dma
0385  * location by the firmware.
0386  */
0387 ssize_t pm80xx_get_non_fatal_dump(struct device *cdev,
0388     struct device_attribute *attr, char *buf)
0389 {
0390     struct Scsi_Host *shost = class_to_shost(cdev);
0391     struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
0392     struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
0393     void __iomem *nonfatal_table_address = pm8001_ha->fatal_tbl_addr;
0394     u32 accum_len = 0;
0395     u32 total_len = 0;
0396     u32 reg_val = 0;
0397     u32 *temp = NULL;
0398     u32 index = 0;
0399     u32 output_length;
0400     unsigned long start = 0;
0401     char *buf_copy = buf;
0402 
0403     temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
0404     if (++pm8001_ha->non_fatal_count == 1) {
0405         if (pm8001_ha->chip_id == chip_8001) {
0406             snprintf(pm8001_ha->forensic_info.data_buf.direct_data,
0407                 PAGE_SIZE, "Not supported for SPC controller");
0408             return 0;
0409         }
0410         pm8001_dbg(pm8001_ha, IO, "forensic_info TYPE_NON_FATAL...\n");
0411         /*
0412          * Step 1: Write the host buffer parameters in the MPI Fatal and
0413          * Non-Fatal Error Dump Capture Table.This is the buffer
0414          * where debug data will be DMAed to.
0415          */
0416         pm8001_mw32(nonfatal_table_address,
0417         MPI_FATAL_EDUMP_TABLE_LO_OFFSET,
0418         pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_lo);
0419 
0420         pm8001_mw32(nonfatal_table_address,
0421         MPI_FATAL_EDUMP_TABLE_HI_OFFSET,
0422         pm8001_ha->memoryMap.region[FORENSIC_MEM].phys_addr_hi);
0423 
0424         pm8001_mw32(nonfatal_table_address,
0425         MPI_FATAL_EDUMP_TABLE_LENGTH, SYSFS_OFFSET);
0426 
0427         /* Optionally, set the DUMPCTRL bit to 1 if the host
0428          * keeps sending active I/Os while capturing the non-fatal
0429          * debug data. Otherwise, leave this bit set to zero
0430          */
0431         pm8001_mw32(nonfatal_table_address,
0432         MPI_FATAL_EDUMP_TABLE_HANDSHAKE, MPI_FATAL_EDUMP_HANDSHAKE_RDY);
0433 
0434         /*
0435          * Step 2: Clear Accumulative Length of Debug Data Transferred
0436          * [ACCDDLEN] field in the MPI Fatal and Non-Fatal Error Dump
0437          * Capture Table to zero.
0438          */
0439         pm8001_mw32(nonfatal_table_address,
0440                 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN, 0);
0441 
0442         /* initiallize previous accumulated length to 0 */
0443         pm8001_ha->forensic_preserved_accumulated_transfer = 0;
0444         pm8001_ha->non_fatal_read_length = 0;
0445     }
0446 
0447     total_len = pm8001_mr32(nonfatal_table_address,
0448             MPI_FATAL_EDUMP_TABLE_TOTAL_LEN);
0449     /*
0450      * Step 3:Clear Fatal/Non-Fatal Debug Data Transfer Status [FDDTSTAT]
0451      * field and then request that the SPCv controller transfer the debug
0452      * data by setting bit 7 of the Inbound Doorbell Set Register.
0453      */
0454     pm8001_mw32(nonfatal_table_address, MPI_FATAL_EDUMP_TABLE_STATUS, 0);
0455     pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET,
0456             SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP);
0457 
0458     /*
0459      * Step 4.1: Read back the Inbound Doorbell Set Register (by polling for
0460      * 2 seconds) until register bit 7 is cleared.
0461      * This step only indicates the request is accepted by the controller.
0462      */
0463     start = jiffies + (2 * HZ); /* 2 sec */
0464     do {
0465         reg_val = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET) &
0466             SPCv_MSGU_CFG_TABLE_NONFATAL_DUMP;
0467     } while ((reg_val != 0) && time_before(jiffies, start));
0468 
0469     /* Step 4.2: To check the completion of the transfer, poll the Fatal/Non
0470      * Fatal Debug Data Transfer Status [FDDTSTAT] field for 2 seconds in
0471      * the MPI Fatal and Non-Fatal Error Dump Capture Table.
0472      */
0473     start = jiffies + (2 * HZ); /* 2 sec */
0474     do {
0475         reg_val = pm8001_mr32(nonfatal_table_address,
0476                 MPI_FATAL_EDUMP_TABLE_STATUS);
0477     } while ((!reg_val) && time_before(jiffies, start));
0478 
0479     if ((reg_val == 0x00) ||
0480         (reg_val == MPI_FATAL_EDUMP_TABLE_STAT_DMA_FAILED) ||
0481         (reg_val > MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE)) {
0482         pm8001_ha->non_fatal_read_length = 0;
0483         buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 0xFFFFFFFF);
0484         pm8001_ha->non_fatal_count = 0;
0485         return (buf_copy - buf);
0486     } else if (reg_val ==
0487             MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_MORE_DATA) {
0488         buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 2);
0489     } else if ((reg_val == MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) ||
0490         (pm8001_ha->non_fatal_read_length >= total_len)) {
0491         pm8001_ha->non_fatal_read_length = 0;
0492         buf_copy += snprintf(buf_copy, PAGE_SIZE, "%08x ", 4);
0493         pm8001_ha->non_fatal_count = 0;
0494     }
0495     accum_len = pm8001_mr32(nonfatal_table_address,
0496             MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
0497     output_length = accum_len -
0498         pm8001_ha->forensic_preserved_accumulated_transfer;
0499 
0500     for (index = 0; index < output_length/4; index++)
0501         buf_copy += snprintf(buf_copy, PAGE_SIZE,
0502                 "%08x ", *(temp+index));
0503 
0504     pm8001_ha->non_fatal_read_length += output_length;
0505 
0506     /* store current accumulated length to use in next iteration as
0507      * the previous accumulated length
0508      */
0509     pm8001_ha->forensic_preserved_accumulated_transfer = accum_len;
0510     return (buf_copy - buf);
0511 }
0512 
0513 /**
0514  * read_main_config_table - read the configure table and save it.
0515  * @pm8001_ha: our hba card information
0516  */
0517 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
0518 {
0519     void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
0520 
0521     pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature    =
0522         pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
0523     pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
0524         pm8001_mr32(address, MAIN_INTERFACE_REVISION);
0525     pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
0526         pm8001_mr32(address, MAIN_FW_REVISION);
0527     pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io   =
0528         pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
0529     pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl  =
0530         pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
0531     pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
0532         pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
0533     pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset   =
0534         pm8001_mr32(address, MAIN_GST_OFFSET);
0535     pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
0536         pm8001_mr32(address, MAIN_IBQ_OFFSET);
0537     pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
0538         pm8001_mr32(address, MAIN_OBQ_OFFSET);
0539 
0540     /* read Error Dump Offset and Length */
0541     pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
0542         pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
0543     pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
0544         pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
0545     pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
0546         pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
0547     pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
0548         pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
0549 
0550     /* read GPIO LED settings from the configuration table */
0551     pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
0552         pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
0553 
0554     /* read analog Setting offset from the configuration table */
0555     pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
0556         pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
0557 
0558     pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
0559         pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
0560     pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
0561         pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
0562     /* read port recover and reset timeout */
0563     pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
0564         pm8001_mr32(address, MAIN_PORT_RECOVERY_TIMER);
0565     /* read ILA and inactive firmware version */
0566     pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
0567         pm8001_mr32(address, MAIN_MPI_ILA_RELEASE_TYPE);
0568     pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
0569         pm8001_mr32(address, MAIN_MPI_INACTIVE_FW_VERSION);
0570 
0571     pm8001_dbg(pm8001_ha, DEV,
0572            "Main cfg table: sign:%x interface rev:%x fw_rev:%x\n",
0573            pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
0574            pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
0575            pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
0576 
0577     pm8001_dbg(pm8001_ha, DEV,
0578            "table offset: gst:%x iq:%x oq:%x int vec:%x phy attr:%x\n",
0579            pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
0580            pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
0581            pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
0582            pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
0583            pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
0584 
0585     pm8001_dbg(pm8001_ha, DEV,
0586            "Main cfg table; ila rev:%x Inactive fw rev:%x\n",
0587            pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
0588            pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
0589 }
0590 
0591 /**
0592  * read_general_status_table - read the general status table and save it.
0593  * @pm8001_ha: our hba card information
0594  */
0595 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
0596 {
0597     void __iomem *address = pm8001_ha->general_stat_tbl_addr;
0598     pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate   =
0599             pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
0600     pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0   =
0601             pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
0602     pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1   =
0603             pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
0604     pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt      =
0605             pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
0606     pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt       =
0607             pm8001_mr32(address, GST_IOPTCNT_OFFSET);
0608     pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
0609             pm8001_mr32(address, GST_GPIO_INPUT_VAL);
0610     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
0611             pm8001_mr32(address, GST_RERRINFO_OFFSET0);
0612     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
0613             pm8001_mr32(address, GST_RERRINFO_OFFSET1);
0614     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
0615             pm8001_mr32(address, GST_RERRINFO_OFFSET2);
0616     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
0617             pm8001_mr32(address, GST_RERRINFO_OFFSET3);
0618     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
0619             pm8001_mr32(address, GST_RERRINFO_OFFSET4);
0620     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
0621             pm8001_mr32(address, GST_RERRINFO_OFFSET5);
0622     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
0623             pm8001_mr32(address, GST_RERRINFO_OFFSET6);
0624     pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
0625              pm8001_mr32(address, GST_RERRINFO_OFFSET7);
0626 }
0627 /**
0628  * read_phy_attr_table - read the phy attribute table and save it.
0629  * @pm8001_ha: our hba card information
0630  */
0631 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
0632 {
0633     void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
0634     pm8001_ha->phy_attr_table.phystart1_16[0] =
0635             pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
0636     pm8001_ha->phy_attr_table.phystart1_16[1] =
0637             pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
0638     pm8001_ha->phy_attr_table.phystart1_16[2] =
0639             pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
0640     pm8001_ha->phy_attr_table.phystart1_16[3] =
0641             pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
0642     pm8001_ha->phy_attr_table.phystart1_16[4] =
0643             pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
0644     pm8001_ha->phy_attr_table.phystart1_16[5] =
0645             pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
0646     pm8001_ha->phy_attr_table.phystart1_16[6] =
0647             pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
0648     pm8001_ha->phy_attr_table.phystart1_16[7] =
0649             pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
0650     pm8001_ha->phy_attr_table.phystart1_16[8] =
0651             pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
0652     pm8001_ha->phy_attr_table.phystart1_16[9] =
0653             pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
0654     pm8001_ha->phy_attr_table.phystart1_16[10] =
0655             pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
0656     pm8001_ha->phy_attr_table.phystart1_16[11] =
0657             pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
0658     pm8001_ha->phy_attr_table.phystart1_16[12] =
0659             pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
0660     pm8001_ha->phy_attr_table.phystart1_16[13] =
0661             pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
0662     pm8001_ha->phy_attr_table.phystart1_16[14] =
0663             pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
0664     pm8001_ha->phy_attr_table.phystart1_16[15] =
0665             pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
0666 
0667     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
0668             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
0669     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
0670             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
0671     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
0672             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
0673     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
0674             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
0675     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
0676             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
0677     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
0678             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
0679     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
0680             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
0681     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
0682             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
0683     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
0684             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
0685     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
0686             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
0687     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
0688             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
0689     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
0690             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
0691     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
0692             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
0693     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
0694             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
0695     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
0696             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
0697     pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
0698             pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
0699 
0700 }
0701 
0702 /**
0703  * read_inbnd_queue_table - read the inbound queue table and save it.
0704  * @pm8001_ha: our hba card information
0705  */
0706 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
0707 {
0708     int i;
0709     void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
0710     for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
0711         u32 offset = i * 0x20;
0712         pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
0713             get_pci_bar_index(pm8001_mr32(address,
0714                 (offset + IB_PIPCI_BAR)));
0715         pm8001_ha->inbnd_q_tbl[i].pi_offset =
0716             pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
0717     }
0718 }
0719 
0720 /**
0721  * read_outbnd_queue_table - read the outbound queue table and save it.
0722  * @pm8001_ha: our hba card information
0723  */
0724 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
0725 {
0726     int i;
0727     void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
0728     for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
0729         u32 offset = i * 0x24;
0730         pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
0731             get_pci_bar_index(pm8001_mr32(address,
0732                 (offset + OB_CIPCI_BAR)));
0733         pm8001_ha->outbnd_q_tbl[i].ci_offset =
0734             pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
0735     }
0736 }
0737 
0738 /**
0739  * init_default_table_values - init the default table.
0740  * @pm8001_ha: our hba card information
0741  */
0742 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
0743 {
0744     int i;
0745     u32 offsetib, offsetob;
0746     void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
0747     void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
0748     u32 ib_offset = pm8001_ha->ib_offset;
0749     u32 ob_offset = pm8001_ha->ob_offset;
0750     u32 ci_offset = pm8001_ha->ci_offset;
0751     u32 pi_offset = pm8001_ha->pi_offset;
0752 
0753     pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr     =
0754         pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
0755     pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr     =
0756         pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
0757     pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size       =
0758                             PM8001_EVENT_LOG_SIZE;
0759     pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity       = 0x01;
0760     pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
0761         pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
0762     pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
0763         pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
0764     pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size       =
0765                             PM8001_EVENT_LOG_SIZE;
0766     pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity   = 0x01;
0767     pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt      = 0x01;
0768 
0769     /* Enable higher IQs and OQs, 32 to 63, bit 16 */
0770     if (pm8001_ha->max_q_num > 32)
0771         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
0772                             1 << 16;
0773     /* Disable end to end CRC checking */
0774     pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
0775 
0776     for (i = 0; i < pm8001_ha->max_q_num; i++) {
0777         pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
0778             PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
0779         pm8001_ha->inbnd_q_tbl[i].upper_base_addr   =
0780             pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
0781         pm8001_ha->inbnd_q_tbl[i].lower_base_addr   =
0782         pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
0783         pm8001_ha->inbnd_q_tbl[i].base_virt     =
0784           (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
0785         pm8001_ha->inbnd_q_tbl[i].total_length      =
0786             pm8001_ha->memoryMap.region[ib_offset + i].total_len;
0787         pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
0788             pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
0789         pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
0790             pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
0791         pm8001_ha->inbnd_q_tbl[i].ci_virt       =
0792             pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
0793         pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
0794         offsetib = i * 0x20;
0795         pm8001_ha->inbnd_q_tbl[i].pi_pci_bar        =
0796             get_pci_bar_index(pm8001_mr32(addressib,
0797                 (offsetib + 0x14)));
0798         pm8001_ha->inbnd_q_tbl[i].pi_offset     =
0799             pm8001_mr32(addressib, (offsetib + 0x18));
0800         pm8001_ha->inbnd_q_tbl[i].producer_idx      = 0;
0801         pm8001_ha->inbnd_q_tbl[i].consumer_index    = 0;
0802 
0803         pm8001_dbg(pm8001_ha, DEV,
0804                "IQ %d pi_bar 0x%x pi_offset 0x%x\n", i,
0805                pm8001_ha->inbnd_q_tbl[i].pi_pci_bar,
0806                pm8001_ha->inbnd_q_tbl[i].pi_offset);
0807     }
0808     for (i = 0; i < pm8001_ha->max_q_num; i++) {
0809         pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
0810             PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
0811         pm8001_ha->outbnd_q_tbl[i].upper_base_addr  =
0812             pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
0813         pm8001_ha->outbnd_q_tbl[i].lower_base_addr  =
0814             pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
0815         pm8001_ha->outbnd_q_tbl[i].base_virt        =
0816           (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
0817         pm8001_ha->outbnd_q_tbl[i].total_length     =
0818             pm8001_ha->memoryMap.region[ob_offset + i].total_len;
0819         pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
0820             pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
0821         pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
0822             pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
0823         /* interrupt vector based on oq */
0824         pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
0825         pm8001_ha->outbnd_q_tbl[i].pi_virt      =
0826             pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
0827         pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
0828         offsetob = i * 0x24;
0829         pm8001_ha->outbnd_q_tbl[i].ci_pci_bar       =
0830             get_pci_bar_index(pm8001_mr32(addressob,
0831             offsetob + 0x14));
0832         pm8001_ha->outbnd_q_tbl[i].ci_offset        =
0833             pm8001_mr32(addressob, (offsetob + 0x18));
0834         pm8001_ha->outbnd_q_tbl[i].consumer_idx     = 0;
0835         pm8001_ha->outbnd_q_tbl[i].producer_index   = 0;
0836 
0837         pm8001_dbg(pm8001_ha, DEV,
0838                "OQ %d ci_bar 0x%x ci_offset 0x%x\n", i,
0839                pm8001_ha->outbnd_q_tbl[i].ci_pci_bar,
0840                pm8001_ha->outbnd_q_tbl[i].ci_offset);
0841     }
0842 }
0843 
0844 /**
0845  * update_main_config_table - update the main default table to the HBA.
0846  * @pm8001_ha: our hba card information
0847  */
0848 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
0849 {
0850     void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
0851     pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
0852         pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
0853     pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
0854         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
0855     pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
0856         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
0857     pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
0858         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
0859     pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
0860         pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
0861     pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
0862         pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
0863     pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
0864         pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
0865     pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
0866         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
0867     pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
0868         pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
0869     /* Update Fatal error interrupt vector */
0870     pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
0871                     ((pm8001_ha->max_q_num - 1) << 8);
0872     pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
0873         pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
0874     pm8001_dbg(pm8001_ha, DEV,
0875            "Updated Fatal error interrupt vector 0x%x\n",
0876            pm8001_mr32(address, MAIN_FATAL_ERROR_INTERRUPT));
0877 
0878     pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
0879         pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
0880 
0881     /* SPCv specific */
0882     pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
0883     /* Set GPIOLED to 0x2 for LED indicator */
0884     pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
0885     pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
0886         pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
0887     pm8001_dbg(pm8001_ha, DEV,
0888            "Programming DW 0x21 in main cfg table with 0x%x\n",
0889            pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET));
0890 
0891     pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
0892         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
0893     pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
0894         pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
0895 
0896     pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
0897     pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
0898                             PORT_RECOVERY_TIMEOUT;
0899     if (pm8001_ha->chip_id == chip_8006) {
0900         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
0901                     0x0000ffff;
0902         pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
0903                     CHIP_8006_PORT_RECOVERY_TIMEOUT;
0904     }
0905     pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
0906             pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
0907 }
0908 
0909 /**
0910  * update_inbnd_queue_table - update the inbound queue table to the HBA.
0911  * @pm8001_ha: our hba card information
0912  * @number: entry in the queue
0913  */
0914 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
0915                      int number)
0916 {
0917     void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
0918     u16 offset = number * 0x20;
0919     pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
0920         pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
0921     pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
0922         pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
0923     pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
0924         pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
0925     pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
0926         pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
0927     pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
0928         pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
0929 
0930     pm8001_dbg(pm8001_ha, DEV,
0931            "IQ %d: Element pri size 0x%x\n",
0932            number,
0933            pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
0934 
0935     pm8001_dbg(pm8001_ha, DEV,
0936            "IQ upr base addr 0x%x IQ lwr base addr 0x%x\n",
0937            pm8001_ha->inbnd_q_tbl[number].upper_base_addr,
0938            pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
0939 
0940     pm8001_dbg(pm8001_ha, DEV,
0941            "CI upper base addr 0x%x CI lower base addr 0x%x\n",
0942            pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr,
0943            pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
0944 }
0945 
0946 /**
0947  * update_outbnd_queue_table - update the outbound queue table to the HBA.
0948  * @pm8001_ha: our hba card information
0949  * @number: entry in the queue
0950  */
0951 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
0952                          int number)
0953 {
0954     void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
0955     u16 offset = number * 0x24;
0956     pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
0957         pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
0958     pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
0959         pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
0960     pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
0961         pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
0962     pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
0963         pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
0964     pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
0965         pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
0966     pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
0967         pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
0968 
0969     pm8001_dbg(pm8001_ha, DEV,
0970            "OQ %d: Element pri size 0x%x\n",
0971            number,
0972            pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
0973 
0974     pm8001_dbg(pm8001_ha, DEV,
0975            "OQ upr base addr 0x%x OQ lwr base addr 0x%x\n",
0976            pm8001_ha->outbnd_q_tbl[number].upper_base_addr,
0977            pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
0978 
0979     pm8001_dbg(pm8001_ha, DEV,
0980            "PI upper base addr 0x%x PI lower base addr 0x%x\n",
0981            pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr,
0982            pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
0983 }
0984 
0985 /**
0986  * mpi_init_check - check firmware initialization status.
0987  * @pm8001_ha: our hba card information
0988  */
0989 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
0990 {
0991     u32 max_wait_count;
0992     u32 value;
0993     u32 gst_len_mpistate;
0994 
0995     /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
0996     table is updated */
0997     pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
0998     /* wait until Inbound DoorBell Clear Register toggled */
0999     if (IS_SPCV_12G(pm8001_ha->pdev)) {
1000         max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1001     } else {
1002         max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1003     }
1004     do {
1005         msleep(FW_READY_INTERVAL);
1006         value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1007         value &= SPCv_MSGU_CFG_TABLE_UPDATE;
1008     } while ((value != 0) && (--max_wait_count));
1009 
1010     if (!max_wait_count) {
1011         /* additional check */
1012         pm8001_dbg(pm8001_ha, FAIL,
1013                "Inb doorbell clear not toggled[value:%x]\n",
1014                value);
1015         return -EBUSY;
1016     }
1017     /* check the MPI-State for initialization up to 100ms*/
1018     max_wait_count = 5;/* 100 msec */
1019     do {
1020         msleep(FW_READY_INTERVAL);
1021         gst_len_mpistate =
1022             pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1023                     GST_GSTLEN_MPIS_OFFSET);
1024     } while ((GST_MPI_STATE_INIT !=
1025         (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
1026     if (!max_wait_count)
1027         return -EBUSY;
1028 
1029     /* check MPI Initialization error */
1030     gst_len_mpistate = gst_len_mpistate >> 16;
1031     if (0x0000 != gst_len_mpistate)
1032         return -EBUSY;
1033 
1034     /*
1035      *  As per controller datasheet, after successful MPI
1036      *  initialization minimum 500ms delay is required before
1037      *  issuing commands.
1038      */
1039     msleep(500);
1040 
1041     return 0;
1042 }
1043 
1044 /**
1045  * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
1046  * This function sleeps hence it must not be used in atomic context.
1047  * @pm8001_ha: our hba card information
1048  */
1049 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
1050 {
1051     u32 value;
1052     u32 max_wait_count;
1053     u32 max_wait_time;
1054     u32 expected_mask;
1055     int ret = 0;
1056 
1057     /* reset / PCIe ready */
1058     max_wait_time = max_wait_count = 5; /* 100 milli sec */
1059     do {
1060         msleep(FW_READY_INTERVAL);
1061         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1062     } while ((value == 0xFFFFFFFF) && (--max_wait_count));
1063 
1064     /* check ila, RAAE and iops status */
1065     if ((pm8001_ha->chip_id != chip_8008) &&
1066             (pm8001_ha->chip_id != chip_8009)) {
1067         max_wait_time = max_wait_count = 180;   /* 3600 milli sec */
1068         expected_mask = SCRATCH_PAD_ILA_READY |
1069             SCRATCH_PAD_RAAE_READY |
1070             SCRATCH_PAD_IOP0_READY |
1071             SCRATCH_PAD_IOP1_READY;
1072     } else {
1073         max_wait_time = max_wait_count = 170;   /* 3400 milli sec */
1074         expected_mask = SCRATCH_PAD_ILA_READY |
1075             SCRATCH_PAD_RAAE_READY |
1076             SCRATCH_PAD_IOP0_READY;
1077     }
1078     do {
1079         msleep(FW_READY_INTERVAL);
1080         value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1081     } while (((value & expected_mask) !=
1082                  expected_mask) && (--max_wait_count));
1083     if (!max_wait_count) {
1084         pm8001_dbg(pm8001_ha, INIT,
1085         "At least one FW component failed to load within %d millisec: Scratchpad1: 0x%x\n",
1086             max_wait_time * FW_READY_INTERVAL, value);
1087         ret = -1;
1088     } else {
1089         pm8001_dbg(pm8001_ha, MSG,
1090             "All FW components ready by %d ms\n",
1091             (max_wait_time - max_wait_count) * FW_READY_INTERVAL);
1092     }
1093     return ret;
1094 }
1095 
1096 static int init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
1097 {
1098     void __iomem *base_addr;
1099     u32 value;
1100     u32 offset;
1101     u32 pcibar;
1102     u32 pcilogic;
1103 
1104     value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1105 
1106     /*
1107      * lower 26 bits of SCRATCHPAD0 register describes offset within the
1108      * PCIe BAR where the MPI configuration table is present
1109      */
1110     offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
1111 
1112     pm8001_dbg(pm8001_ha, DEV, "Scratchpad 0 Offset: 0x%x value 0x%x\n",
1113            offset, value);
1114     /*
1115      * Upper 6 bits describe the offset within PCI config space where BAR
1116      * is located.
1117      */
1118     pcilogic = (value & 0xFC000000) >> 26;
1119     pcibar = get_pci_bar_index(pcilogic);
1120     pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
1121 
1122     /*
1123      * Make sure the offset falls inside the ioremapped PCI BAR
1124      */
1125     if (offset > pm8001_ha->io_mem[pcibar].memsize) {
1126         pm8001_dbg(pm8001_ha, FAIL,
1127             "Main cfg tbl offset outside %u > %u\n",
1128                 offset, pm8001_ha->io_mem[pcibar].memsize);
1129         return -EBUSY;
1130     }
1131     pm8001_ha->main_cfg_tbl_addr = base_addr =
1132         pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
1133 
1134     /*
1135      * Validate main configuration table address: first DWord should read
1136      * "PMCS"
1137      */
1138     value = pm8001_mr32(pm8001_ha->main_cfg_tbl_addr, 0);
1139     if (memcmp(&value, "PMCS", 4) != 0) {
1140         pm8001_dbg(pm8001_ha, FAIL,
1141             "BAD main config signature 0x%x\n",
1142                 value);
1143         return -EBUSY;
1144     }
1145     pm8001_dbg(pm8001_ha, INIT,
1146             "VALID main config signature 0x%x\n", value);
1147     pm8001_ha->general_stat_tbl_addr =
1148         base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
1149                     0xFFFFFF);
1150     pm8001_ha->inbnd_q_tbl_addr =
1151         base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
1152                     0xFFFFFF);
1153     pm8001_ha->outbnd_q_tbl_addr =
1154         base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
1155                     0xFFFFFF);
1156     pm8001_ha->ivt_tbl_addr =
1157         base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
1158                     0xFFFFFF);
1159     pm8001_ha->pspa_q_tbl_addr =
1160         base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
1161                     0xFFFFFF);
1162     pm8001_ha->fatal_tbl_addr =
1163         base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
1164                     0xFFFFFF);
1165 
1166     pm8001_dbg(pm8001_ha, INIT, "GST OFFSET 0x%x\n",
1167            pm8001_cr32(pm8001_ha, pcibar, offset + 0x18));
1168     pm8001_dbg(pm8001_ha, INIT, "INBND OFFSET 0x%x\n",
1169            pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C));
1170     pm8001_dbg(pm8001_ha, INIT, "OBND OFFSET 0x%x\n",
1171            pm8001_cr32(pm8001_ha, pcibar, offset + 0x20));
1172     pm8001_dbg(pm8001_ha, INIT, "IVT OFFSET 0x%x\n",
1173            pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C));
1174     pm8001_dbg(pm8001_ha, INIT, "PSPA OFFSET 0x%x\n",
1175            pm8001_cr32(pm8001_ha, pcibar, offset + 0x90));
1176     pm8001_dbg(pm8001_ha, INIT, "addr - main cfg %p general status %p\n",
1177            pm8001_ha->main_cfg_tbl_addr,
1178            pm8001_ha->general_stat_tbl_addr);
1179     pm8001_dbg(pm8001_ha, INIT, "addr - inbnd %p obnd %p\n",
1180            pm8001_ha->inbnd_q_tbl_addr,
1181            pm8001_ha->outbnd_q_tbl_addr);
1182     pm8001_dbg(pm8001_ha, INIT, "addr - pspa %p ivt %p\n",
1183            pm8001_ha->pspa_q_tbl_addr,
1184            pm8001_ha->ivt_tbl_addr);
1185     return 0;
1186 }
1187 
1188 /**
1189  * pm80xx_set_thermal_config - support the thermal configuration
1190  * @pm8001_ha: our hba card information.
1191  */
1192 int
1193 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
1194 {
1195     struct set_ctrl_cfg_req payload;
1196     int rc;
1197     u32 tag;
1198     u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1199     u32 page_code;
1200 
1201     memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1202     rc = pm8001_tag_alloc(pm8001_ha, &tag);
1203     if (rc)
1204         return rc;
1205 
1206     payload.tag = cpu_to_le32(tag);
1207 
1208     if (IS_SPCV_12G(pm8001_ha->pdev))
1209         page_code = THERMAL_PAGE_CODE_7H;
1210     else
1211         page_code = THERMAL_PAGE_CODE_8H;
1212 
1213     payload.cfg_pg[0] =
1214         cpu_to_le32((THERMAL_LOG_ENABLE << 9) |
1215                 (THERMAL_ENABLE << 8) | page_code);
1216     payload.cfg_pg[1] =
1217         cpu_to_le32((LTEMPHIL << 24) | (RTEMPHIL << 8));
1218 
1219     pm8001_dbg(pm8001_ha, DEV,
1220            "Setting up thermal config. cfg_pg 0 0x%x cfg_pg 1 0x%x\n",
1221            payload.cfg_pg[0], payload.cfg_pg[1]);
1222 
1223     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1224             sizeof(payload), 0);
1225     if (rc)
1226         pm8001_tag_free(pm8001_ha, tag);
1227     return rc;
1228 
1229 }
1230 
1231 /**
1232 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
1233 * Timer configuration page
1234 * @pm8001_ha: our hba card information.
1235 */
1236 static int
1237 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
1238 {
1239     struct set_ctrl_cfg_req payload;
1240     SASProtocolTimerConfig_t SASConfigPage;
1241     int rc;
1242     u32 tag;
1243     u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
1244 
1245     memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
1246     memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
1247 
1248     rc = pm8001_tag_alloc(pm8001_ha, &tag);
1249     if (rc)
1250         return rc;
1251 
1252     payload.tag = cpu_to_le32(tag);
1253 
1254     SASConfigPage.pageCode = cpu_to_le32(SAS_PROTOCOL_TIMER_CONFIG_PAGE);
1255     SASConfigPage.MST_MSI = cpu_to_le32(3 << 15);
1256     SASConfigPage.STP_SSP_MCT_TMO =
1257         cpu_to_le32((STP_MCT_TMO << 16) | SSP_MCT_TMO);
1258     SASConfigPage.STP_FRM_TMO =
1259         cpu_to_le32((SAS_MAX_OPEN_TIME << 24) |
1260                 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER);
1261     SASConfigPage.STP_IDLE_TMO = cpu_to_le32(STP_IDLE_TIME);
1262 
1263     SASConfigPage.OPNRJT_RTRY_INTVL =
1264         cpu_to_le32((SAS_MFD << 16) | SAS_OPNRJT_RTRY_INTVL);
1265     SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO =
1266         cpu_to_le32((SAS_DOPNRJT_RTRY_TMO << 16) | SAS_COPNRJT_RTRY_TMO);
1267     SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR =
1268         cpu_to_le32((SAS_DOPNRJT_RTRY_THR << 16) | SAS_COPNRJT_RTRY_THR);
1269     SASConfigPage.MAX_AIP = cpu_to_le32(SAS_MAX_AIP);
1270 
1271     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.pageCode 0x%08x\n",
1272            le32_to_cpu(SASConfigPage.pageCode));
1273     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MST_MSI  0x%08x\n",
1274            le32_to_cpu(SASConfigPage.MST_MSI));
1275     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_SSP_MCT_TMO  0x%08x\n",
1276            le32_to_cpu(SASConfigPage.STP_SSP_MCT_TMO));
1277     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_FRM_TMO  0x%08x\n",
1278            le32_to_cpu(SASConfigPage.STP_FRM_TMO));
1279     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.STP_IDLE_TMO  0x%08x\n",
1280            le32_to_cpu(SASConfigPage.STP_IDLE_TMO));
1281     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.OPNRJT_RTRY_INTVL  0x%08x\n",
1282            le32_to_cpu(SASConfigPage.OPNRJT_RTRY_INTVL));
1283     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO  0x%08x\n",
1284            le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
1285     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR  0x%08x\n",
1286            le32_to_cpu(SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
1287     pm8001_dbg(pm8001_ha, INIT, "SASConfigPage.MAX_AIP  0x%08x\n",
1288            le32_to_cpu(SASConfigPage.MAX_AIP));
1289 
1290     memcpy(&payload.cfg_pg, &SASConfigPage,
1291              sizeof(SASProtocolTimerConfig_t));
1292 
1293     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1294             sizeof(payload), 0);
1295     if (rc)
1296         pm8001_tag_free(pm8001_ha, tag);
1297 
1298     return rc;
1299 }
1300 
1301 /**
1302  * pm80xx_get_encrypt_info - Check for encryption
1303  * @pm8001_ha: our hba card information.
1304  */
1305 static int
1306 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
1307 {
1308     u32 scratch3_value;
1309     int ret = -1;
1310 
1311     /* Read encryption status from SCRATCH PAD 3 */
1312     scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1313 
1314     if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1315                     SCRATCH_PAD3_ENC_READY) {
1316         if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1317             pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1318         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1319                         SCRATCH_PAD3_SMF_ENABLED)
1320             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1321         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1322                         SCRATCH_PAD3_SMA_ENABLED)
1323             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1324         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1325                         SCRATCH_PAD3_SMB_ENABLED)
1326             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1327         pm8001_ha->encrypt_info.status = 0;
1328         pm8001_dbg(pm8001_ha, INIT,
1329                "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X.Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
1330                scratch3_value,
1331                pm8001_ha->encrypt_info.cipher_mode,
1332                pm8001_ha->encrypt_info.sec_mode,
1333                pm8001_ha->encrypt_info.status);
1334         ret = 0;
1335     } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
1336                     SCRATCH_PAD3_ENC_DISABLED) {
1337         pm8001_dbg(pm8001_ha, INIT,
1338                "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
1339                scratch3_value);
1340         pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
1341         pm8001_ha->encrypt_info.cipher_mode = 0;
1342         pm8001_ha->encrypt_info.sec_mode = 0;
1343         ret = 0;
1344     } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1345                 SCRATCH_PAD3_ENC_DIS_ERR) {
1346         pm8001_ha->encrypt_info.status =
1347             (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1348         if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1349             pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1350         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1351                     SCRATCH_PAD3_SMF_ENABLED)
1352             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1353         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1354                     SCRATCH_PAD3_SMA_ENABLED)
1355             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1356         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1357                     SCRATCH_PAD3_SMB_ENABLED)
1358             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1359         pm8001_dbg(pm8001_ha, INIT,
1360                "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1361                scratch3_value,
1362                pm8001_ha->encrypt_info.cipher_mode,
1363                pm8001_ha->encrypt_info.sec_mode,
1364                pm8001_ha->encrypt_info.status);
1365     } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1366                  SCRATCH_PAD3_ENC_ENA_ERR) {
1367 
1368         pm8001_ha->encrypt_info.status =
1369             (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1370         if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1371             pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1372         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1373                     SCRATCH_PAD3_SMF_ENABLED)
1374             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1375         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1376                     SCRATCH_PAD3_SMA_ENABLED)
1377             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1378         if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1379                     SCRATCH_PAD3_SMB_ENABLED)
1380             pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1381 
1382         pm8001_dbg(pm8001_ha, INIT,
1383                "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X.Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1384                scratch3_value,
1385                pm8001_ha->encrypt_info.cipher_mode,
1386                pm8001_ha->encrypt_info.sec_mode,
1387                pm8001_ha->encrypt_info.status);
1388     }
1389     return ret;
1390 }
1391 
1392 /**
1393  * pm80xx_encrypt_update - update flash with encryption information
1394  * @pm8001_ha: our hba card information.
1395  */
1396 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1397 {
1398     struct kek_mgmt_req payload;
1399     int rc;
1400     u32 tag;
1401     u32 opc = OPC_INB_KEK_MANAGEMENT;
1402 
1403     memset(&payload, 0, sizeof(struct kek_mgmt_req));
1404     rc = pm8001_tag_alloc(pm8001_ha, &tag);
1405     if (rc)
1406         return rc;
1407 
1408     payload.tag = cpu_to_le32(tag);
1409     /* Currently only one key is used. New KEK index is 1.
1410      * Current KEK index is 1. Store KEK to NVRAM is 1.
1411      */
1412     payload.new_curidx_ksop =
1413         cpu_to_le32(((1 << 24) | (1 << 16) | (1 << 8) |
1414                  KEK_MGMT_SUBOP_KEYCARDUPDATE));
1415 
1416     pm8001_dbg(pm8001_ha, DEV,
1417            "Saving Encryption info to flash. payload 0x%x\n",
1418            le32_to_cpu(payload.new_curidx_ksop));
1419 
1420     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
1421             sizeof(payload), 0);
1422     if (rc)
1423         pm8001_tag_free(pm8001_ha, tag);
1424 
1425     return rc;
1426 }
1427 
1428 /**
1429  * pm80xx_chip_init - the main init function that initializes whole PM8001 chip.
1430  * @pm8001_ha: our hba card information
1431  */
1432 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1433 {
1434     int ret;
1435     u8 i = 0;
1436 
1437     /* check the firmware status */
1438     if (-1 == check_fw_ready(pm8001_ha)) {
1439         pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1440         return -EBUSY;
1441     }
1442 
1443     /* Initialize the controller fatal error flag */
1444     pm8001_ha->controller_fatal_error = false;
1445 
1446     /* Initialize pci space address eg: mpi offset */
1447     ret = init_pci_device_addresses(pm8001_ha);
1448     if (ret) {
1449         pm8001_dbg(pm8001_ha, FAIL,
1450             "Failed to init pci addresses");
1451         return ret;
1452     }
1453     init_default_table_values(pm8001_ha);
1454     read_main_config_table(pm8001_ha);
1455     read_general_status_table(pm8001_ha);
1456     read_inbnd_queue_table(pm8001_ha);
1457     read_outbnd_queue_table(pm8001_ha);
1458     read_phy_attr_table(pm8001_ha);
1459 
1460     /* update main config table ,inbound table and outbound table */
1461     update_main_config_table(pm8001_ha);
1462     for (i = 0; i < pm8001_ha->max_q_num; i++) {
1463         update_inbnd_queue_table(pm8001_ha, i);
1464         update_outbnd_queue_table(pm8001_ha, i);
1465     }
1466     /* notify firmware update finished and check initialization status */
1467     if (0 == mpi_init_check(pm8001_ha)) {
1468         pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
1469     } else
1470         return -EBUSY;
1471 
1472     return 0;
1473 }
1474 
1475 static void pm80xx_chip_post_init(struct pm8001_hba_info *pm8001_ha)
1476 {
1477     /* send SAS protocol timer configuration page to FW */
1478     pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1479 
1480     /* Check for encryption */
1481     if (pm8001_ha->chip->encrypt) {
1482         int ret;
1483 
1484         pm8001_dbg(pm8001_ha, INIT, "Checking for encryption\n");
1485         ret = pm80xx_get_encrypt_info(pm8001_ha);
1486         if (ret == -1) {
1487             pm8001_dbg(pm8001_ha, INIT, "Encryption error !!\n");
1488             if (pm8001_ha->encrypt_info.status == 0x81) {
1489                 pm8001_dbg(pm8001_ha, INIT,
1490                        "Encryption enabled with error.Saving encryption key to flash\n");
1491                 pm80xx_encrypt_update(pm8001_ha);
1492             }
1493         }
1494     }
1495 }
1496 
1497 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1498 {
1499     u32 max_wait_count;
1500     u32 value;
1501     u32 gst_len_mpistate;
1502     int ret;
1503 
1504     ret = init_pci_device_addresses(pm8001_ha);
1505     if (ret) {
1506         pm8001_dbg(pm8001_ha, FAIL,
1507             "Failed to init pci addresses");
1508         return ret;
1509     }
1510 
1511     /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1512     table is stop */
1513     pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1514 
1515     /* wait until Inbound DoorBell Clear Register toggled */
1516     if (IS_SPCV_12G(pm8001_ha->pdev)) {
1517         max_wait_count = SPCV_DOORBELL_CLEAR_TIMEOUT;
1518     } else {
1519         max_wait_count = SPC_DOORBELL_CLEAR_TIMEOUT;
1520     }
1521     do {
1522         msleep(FW_READY_INTERVAL);
1523         value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1524         value &= SPCv_MSGU_CFG_TABLE_RESET;
1525     } while ((value != 0) && (--max_wait_count));
1526 
1527     if (!max_wait_count) {
1528         pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=%x\n", value);
1529         return -1;
1530     }
1531 
1532     /* check the MPI-State for termination in progress */
1533     /* wait until Inbound DoorBell Clear Register toggled */
1534     max_wait_count = 100; /* 2 sec for spcv/ve */
1535     do {
1536         msleep(FW_READY_INTERVAL);
1537         gst_len_mpistate =
1538             pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1539             GST_GSTLEN_MPIS_OFFSET);
1540         if (GST_MPI_STATE_UNINIT ==
1541             (gst_len_mpistate & GST_MPI_STATE_MASK))
1542             break;
1543     } while (--max_wait_count);
1544     if (!max_wait_count) {
1545         pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
1546                gst_len_mpistate & GST_MPI_STATE_MASK);
1547         return -1;
1548     }
1549 
1550     return 0;
1551 }
1552 
1553 /**
1554  * pm80xx_fatal_errors - returns non-zero *ONLY* when fatal errors
1555  * @pm8001_ha: our hba card information
1556  *
1557  * Fatal errors are recoverable only after a host reboot.
1558  */
1559 int
1560 pm80xx_fatal_errors(struct pm8001_hba_info *pm8001_ha)
1561 {
1562     int ret = 0;
1563     u32 scratch_pad_rsvd0 = pm8001_cr32(pm8001_ha, 0,
1564                         MSGU_SCRATCH_PAD_RSVD_0);
1565     u32 scratch_pad_rsvd1 = pm8001_cr32(pm8001_ha, 0,
1566                         MSGU_SCRATCH_PAD_RSVD_1);
1567     u32 scratch_pad1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1568     u32 scratch_pad2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1569     u32 scratch_pad3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1570 
1571     if (pm8001_ha->chip_id != chip_8006 &&
1572             pm8001_ha->chip_id != chip_8074 &&
1573             pm8001_ha->chip_id != chip_8076) {
1574         return 0;
1575     }
1576 
1577     if (MSGU_SCRATCHPAD1_STATE_FATAL_ERROR(scratch_pad1)) {
1578         pm8001_dbg(pm8001_ha, FAIL,
1579             "Fatal error SCRATCHPAD1 = 0x%x SCRATCHPAD2 = 0x%x SCRATCHPAD3 = 0x%x SCRATCHPAD_RSVD0 = 0x%x SCRATCHPAD_RSVD1 = 0x%x\n",
1580                 scratch_pad1, scratch_pad2, scratch_pad3,
1581                 scratch_pad_rsvd0, scratch_pad_rsvd1);
1582         ret = 1;
1583     }
1584 
1585     return ret;
1586 }
1587 
1588 /**
1589  * pm80xx_chip_soft_rst - soft reset the PM8001 chip, so that all
1590  * FW register status are reset to the originated status.
1591  * @pm8001_ha: our hba card information
1592  */
1593 
1594 static int
1595 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1596 {
1597     u32 regval;
1598     u32 bootloader_state;
1599     u32 ibutton0, ibutton1;
1600 
1601     /* Process MPI table uninitialization only if FW is ready */
1602     if (!pm8001_ha->controller_fatal_error) {
1603         /* Check if MPI is in ready state to reset */
1604         if (mpi_uninit_check(pm8001_ha) != 0) {
1605             u32 r0 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
1606             u32 r1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1607             u32 r2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1608             u32 r3 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
1609             pm8001_dbg(pm8001_ha, FAIL,
1610                    "MPI state is not ready scratch: %x:%x:%x:%x\n",
1611                    r0, r1, r2, r3);
1612             /* if things aren't ready but the bootloader is ok then
1613              * try the reset anyway.
1614              */
1615             if (r1 & SCRATCH_PAD1_BOOTSTATE_MASK)
1616                 return -1;
1617         }
1618     }
1619     /* checked for reset register normal state; 0x0 */
1620     regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1621     pm8001_dbg(pm8001_ha, INIT, "reset register before write : 0x%x\n",
1622            regval);
1623 
1624     pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1625     msleep(500);
1626 
1627     regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1628     pm8001_dbg(pm8001_ha, INIT, "reset register after write 0x%x\n",
1629            regval);
1630 
1631     if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1632             SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1633         pm8001_dbg(pm8001_ha, MSG,
1634                " soft reset successful [regval: 0x%x]\n",
1635                regval);
1636     } else {
1637         pm8001_dbg(pm8001_ha, MSG,
1638                " soft reset failed [regval: 0x%x]\n",
1639                regval);
1640 
1641         /* check bootloader is successfully executed or in HDA mode */
1642         bootloader_state =
1643             pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1644             SCRATCH_PAD1_BOOTSTATE_MASK;
1645 
1646         if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1647             pm8001_dbg(pm8001_ha, MSG,
1648                    "Bootloader state - HDA mode SEEPROM\n");
1649         } else if (bootloader_state ==
1650                 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1651             pm8001_dbg(pm8001_ha, MSG,
1652                    "Bootloader state - HDA mode Bootstrap Pin\n");
1653         } else if (bootloader_state ==
1654                 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1655             pm8001_dbg(pm8001_ha, MSG,
1656                    "Bootloader state - HDA mode soft reset\n");
1657         } else if (bootloader_state ==
1658                     SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1659             pm8001_dbg(pm8001_ha, MSG,
1660                    "Bootloader state-HDA mode critical error\n");
1661         }
1662         return -EBUSY;
1663     }
1664 
1665     /* check the firmware status after reset */
1666     if (-1 == check_fw_ready(pm8001_ha)) {
1667         pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
1668         /* check iButton feature support for motherboard controller */
1669         if (pm8001_ha->pdev->subsystem_vendor !=
1670             PCI_VENDOR_ID_ADAPTEC2 &&
1671             pm8001_ha->pdev->subsystem_vendor !=
1672             PCI_VENDOR_ID_ATTO &&
1673             pm8001_ha->pdev->subsystem_vendor != 0) {
1674             ibutton0 = pm8001_cr32(pm8001_ha, 0,
1675                            MSGU_SCRATCH_PAD_RSVD_0);
1676             ibutton1 = pm8001_cr32(pm8001_ha, 0,
1677                            MSGU_SCRATCH_PAD_RSVD_1);
1678             if (!ibutton0 && !ibutton1) {
1679                 pm8001_dbg(pm8001_ha, FAIL,
1680                        "iButton Feature is not Available!!!\n");
1681                 return -EBUSY;
1682             }
1683             if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1684                 pm8001_dbg(pm8001_ha, FAIL,
1685                        "CRC Check for iButton Feature Failed!!!\n");
1686                 return -EBUSY;
1687             }
1688         }
1689     }
1690     pm8001_dbg(pm8001_ha, INIT, "SPCv soft reset Complete\n");
1691     return 0;
1692 }
1693 
1694 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1695 {
1696     u32 i;
1697 
1698     pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1699 
1700     /* do SPCv chip reset. */
1701     pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1702     pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1703 
1704     /* Check this ..whether delay is required or no */
1705     /* delay 10 usec */
1706     udelay(10);
1707 
1708     /* wait for 20 msec until the firmware gets reloaded */
1709     i = 20;
1710     do {
1711         mdelay(1);
1712     } while ((--i) != 0);
1713 
1714     pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1715 }
1716 
1717 /**
1718  * pm80xx_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1719  * @pm8001_ha: our hba card information
1720  */
1721 static void
1722 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1723 {
1724     pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1725     pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1726 }
1727 
1728 /**
1729  * pm80xx_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1730  * @pm8001_ha: our hba card information
1731  */
1732 static void
1733 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1734 {
1735     pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1736 }
1737 
1738 /**
1739  * pm80xx_chip_interrupt_enable - enable PM8001 chip interrupt
1740  * @pm8001_ha: our hba card information
1741  * @vec: interrupt number to enable
1742  */
1743 static void
1744 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1745 {
1746 #ifdef PM8001_USE_MSIX
1747     if (vec < 32)
1748         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, 1U << vec);
1749     else
1750         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR_U,
1751                 1U << (vec - 32));
1752     return;
1753 #endif
1754     pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1755 
1756 }
1757 
1758 /**
1759  * pm80xx_chip_interrupt_disable - disable PM8001 chip interrupt
1760  * @pm8001_ha: our hba card information
1761  * @vec: interrupt number to disable
1762  */
1763 static void
1764 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1765 {
1766 #ifdef PM8001_USE_MSIX
1767     if (vec == 0xFF) {
1768         /* disable all vectors 0-31, 32-63 */
1769         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 0xFFFFFFFF);
1770         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U, 0xFFFFFFFF);
1771     } else if (vec < 32)
1772         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, 1U << vec);
1773     else
1774         pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_U,
1775                 1U << (vec - 32));
1776     return;
1777 #endif
1778     pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1779 }
1780 
1781 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1782         struct pm8001_device *pm8001_ha_dev)
1783 {
1784     struct pm8001_ccb_info *ccb;
1785     struct sas_task *task;
1786     struct task_abort_req task_abort;
1787     u32 opc = OPC_INB_SATA_ABORT;
1788     int ret;
1789 
1790     pm8001_ha_dev->id |= NCQ_ABORT_ALL_FLAG;
1791     pm8001_ha_dev->id &= ~NCQ_READ_LOG_FLAG;
1792 
1793     task = sas_alloc_slow_task(GFP_ATOMIC);
1794     if (!task) {
1795         pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1796         return;
1797     }
1798     task->task_done = pm8001_task_done;
1799 
1800     ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1801     if (!ccb) {
1802         sas_free_task(task);
1803         return;
1804     }
1805 
1806     memset(&task_abort, 0, sizeof(task_abort));
1807     task_abort.abort_all = cpu_to_le32(1);
1808     task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1809     task_abort.tag = cpu_to_le32(ccb->ccb_tag);
1810 
1811     ret = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &task_abort,
1812                    sizeof(task_abort), 0);
1813     pm8001_dbg(pm8001_ha, FAIL, "Executing abort task end\n");
1814     if (ret) {
1815         sas_free_task(task);
1816         pm8001_ccb_free(pm8001_ha, ccb);
1817     }
1818 }
1819 
1820 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1821         struct pm8001_device *pm8001_ha_dev)
1822 {
1823     struct sata_start_req sata_cmd;
1824     int res;
1825     struct pm8001_ccb_info *ccb;
1826     struct sas_task *task = NULL;
1827     struct host_to_dev_fis fis;
1828     struct domain_device *dev;
1829     u32 opc = OPC_INB_SATA_HOST_OPSTART;
1830 
1831     task = sas_alloc_slow_task(GFP_ATOMIC);
1832     if (!task) {
1833         pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1834         return;
1835     }
1836     task->task_done = pm8001_task_done;
1837 
1838     /*
1839      * Allocate domain device by ourselves as libsas is not going to
1840      * provide any.
1841      */
1842     dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1843     if (!dev) {
1844         sas_free_task(task);
1845         pm8001_dbg(pm8001_ha, FAIL,
1846                "Domain device cannot be allocated\n");
1847         return;
1848     }
1849 
1850     task->dev = dev;
1851     task->dev->lldd_dev = pm8001_ha_dev;
1852 
1853     ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_ha_dev, task);
1854     if (!ccb) {
1855         sas_free_task(task);
1856         kfree(dev);
1857         return;
1858     }
1859 
1860     pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1861     pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1862 
1863     memset(&sata_cmd, 0, sizeof(sata_cmd));
1864 
1865     /* construct read log FIS */
1866     memset(&fis, 0, sizeof(struct host_to_dev_fis));
1867     fis.fis_type = 0x27;
1868     fis.flags = 0x80;
1869     fis.command = ATA_CMD_READ_LOG_EXT;
1870     fis.lbal = 0x10;
1871     fis.sector_count = 0x1;
1872 
1873     sata_cmd.tag = cpu_to_le32(ccb->ccb_tag);
1874     sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1875     sata_cmd.ncqtag_atap_dir_m_dad = cpu_to_le32(((0x1 << 7) | (0x5 << 9)));
1876     memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1877 
1878     res = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &sata_cmd,
1879                    sizeof(sata_cmd), 0);
1880     pm8001_dbg(pm8001_ha, FAIL, "Executing read log end\n");
1881     if (res) {
1882         sas_free_task(task);
1883         pm8001_ccb_free(pm8001_ha, ccb);
1884         kfree(dev);
1885     }
1886 }
1887 
1888 /**
1889  * mpi_ssp_completion - process the event that FW response to the SSP request.
1890  * @pm8001_ha: our hba card information
1891  * @piomb: the message contents of this outbound message.
1892  *
1893  * When FW has completed a ssp request for example a IO request, after it has
1894  * filled the SG data with the data, it will trigger this event representing
1895  * that he has finished the job; please check the corresponding buffer.
1896  * So we will tell the caller who maybe waiting the result to tell upper layer
1897  * that the task has been finished.
1898  */
1899 static void
1900 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1901 {
1902     struct sas_task *t;
1903     struct pm8001_ccb_info *ccb;
1904     unsigned long flags;
1905     u32 status;
1906     u32 param;
1907     u32 tag;
1908     struct ssp_completion_resp *psspPayload;
1909     struct task_status_struct *ts;
1910     struct ssp_response_iu *iu;
1911     struct pm8001_device *pm8001_dev;
1912     psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1913     status = le32_to_cpu(psspPayload->status);
1914     tag = le32_to_cpu(psspPayload->tag);
1915     ccb = &pm8001_ha->ccb_info[tag];
1916     if ((status == IO_ABORTED) && ccb->open_retry) {
1917         /* Being completed by another */
1918         ccb->open_retry = 0;
1919         return;
1920     }
1921     pm8001_dev = ccb->device;
1922     param = le32_to_cpu(psspPayload->param);
1923     t = ccb->task;
1924 
1925     if (status && status != IO_UNDERFLOW)
1926         pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1927     if (unlikely(!t || !t->lldd_task || !t->dev))
1928         return;
1929     ts = &t->task_status;
1930 
1931     pm8001_dbg(pm8001_ha, DEV,
1932            "tag::0x%x, status::0x%x task::0x%p\n", tag, status, t);
1933 
1934     /* Print sas address of IO failed device */
1935     if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1936         (status != IO_UNDERFLOW))
1937         pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1938                SAS_ADDR(t->dev->sas_addr));
1939 
1940     switch (status) {
1941     case IO_SUCCESS:
1942         pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS ,param = 0x%x\n",
1943                param);
1944         if (param == 0) {
1945             ts->resp = SAS_TASK_COMPLETE;
1946             ts->stat = SAS_SAM_STAT_GOOD;
1947         } else {
1948             ts->resp = SAS_TASK_COMPLETE;
1949             ts->stat = SAS_PROTO_RESPONSE;
1950             ts->residual = param;
1951             iu = &psspPayload->ssp_resp_iu;
1952             sas_ssp_task_response(pm8001_ha->dev, t, iu);
1953         }
1954         if (pm8001_dev)
1955             atomic_dec(&pm8001_dev->running_req);
1956         break;
1957     case IO_ABORTED:
1958         pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1959         ts->resp = SAS_TASK_COMPLETE;
1960         ts->stat = SAS_ABORTED_TASK;
1961         if (pm8001_dev)
1962             atomic_dec(&pm8001_dev->running_req);
1963         break;
1964     case IO_UNDERFLOW:
1965         /* SSP Completion with error */
1966         pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW ,param = 0x%x\n",
1967                param);
1968         ts->resp = SAS_TASK_COMPLETE;
1969         ts->stat = SAS_DATA_UNDERRUN;
1970         ts->residual = param;
1971         if (pm8001_dev)
1972             atomic_dec(&pm8001_dev->running_req);
1973         break;
1974     case IO_NO_DEVICE:
1975         pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1976         ts->resp = SAS_TASK_UNDELIVERED;
1977         ts->stat = SAS_PHY_DOWN;
1978         if (pm8001_dev)
1979             atomic_dec(&pm8001_dev->running_req);
1980         break;
1981     case IO_XFER_ERROR_BREAK:
1982         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1983         ts->resp = SAS_TASK_COMPLETE;
1984         ts->stat = SAS_OPEN_REJECT;
1985         /* Force the midlayer to retry */
1986         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1987         if (pm8001_dev)
1988             atomic_dec(&pm8001_dev->running_req);
1989         break;
1990     case IO_XFER_ERROR_PHY_NOT_READY:
1991         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1992         ts->resp = SAS_TASK_COMPLETE;
1993         ts->stat = SAS_OPEN_REJECT;
1994         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1995         if (pm8001_dev)
1996             atomic_dec(&pm8001_dev->running_req);
1997         break;
1998     case IO_XFER_ERROR_INVALID_SSP_RSP_FRAME:
1999         pm8001_dbg(pm8001_ha, IO,
2000                "IO_XFER_ERROR_INVALID_SSP_RSP_FRAME\n");
2001         ts->resp = SAS_TASK_COMPLETE;
2002         ts->stat = SAS_OPEN_REJECT;
2003         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2004         if (pm8001_dev)
2005             atomic_dec(&pm8001_dev->running_req);
2006         break;
2007     case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2008         pm8001_dbg(pm8001_ha, IO,
2009                "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2010         ts->resp = SAS_TASK_COMPLETE;
2011         ts->stat = SAS_OPEN_REJECT;
2012         ts->open_rej_reason = SAS_OREJ_EPROTO;
2013         if (pm8001_dev)
2014             atomic_dec(&pm8001_dev->running_req);
2015         break;
2016     case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2017         pm8001_dbg(pm8001_ha, IO,
2018                "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2019         ts->resp = SAS_TASK_COMPLETE;
2020         ts->stat = SAS_OPEN_REJECT;
2021         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2022         if (pm8001_dev)
2023             atomic_dec(&pm8001_dev->running_req);
2024         break;
2025     case IO_OPEN_CNX_ERROR_BREAK:
2026         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2027         ts->resp = SAS_TASK_COMPLETE;
2028         ts->stat = SAS_OPEN_REJECT;
2029         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2030         if (pm8001_dev)
2031             atomic_dec(&pm8001_dev->running_req);
2032         break;
2033     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2034     case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2035     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2036     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2037     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2038     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2039         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2040         ts->resp = SAS_TASK_COMPLETE;
2041         ts->stat = SAS_OPEN_REJECT;
2042         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2043         if (!t->uldd_task)
2044             pm8001_handle_event(pm8001_ha,
2045                 pm8001_dev,
2046                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2047         break;
2048     case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2049         pm8001_dbg(pm8001_ha, IO,
2050                "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2051         ts->resp = SAS_TASK_COMPLETE;
2052         ts->stat = SAS_OPEN_REJECT;
2053         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2054         if (pm8001_dev)
2055             atomic_dec(&pm8001_dev->running_req);
2056         break;
2057     case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2058         pm8001_dbg(pm8001_ha, IO,
2059                "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2060         ts->resp = SAS_TASK_COMPLETE;
2061         ts->stat = SAS_OPEN_REJECT;
2062         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2063         if (pm8001_dev)
2064             atomic_dec(&pm8001_dev->running_req);
2065         break;
2066     case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2067         pm8001_dbg(pm8001_ha, IO,
2068                "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2069         ts->resp = SAS_TASK_UNDELIVERED;
2070         ts->stat = SAS_OPEN_REJECT;
2071         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2072         if (pm8001_dev)
2073             atomic_dec(&pm8001_dev->running_req);
2074         break;
2075     case IO_XFER_ERROR_NAK_RECEIVED:
2076         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2077         ts->resp = SAS_TASK_COMPLETE;
2078         ts->stat = SAS_OPEN_REJECT;
2079         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2080         if (pm8001_dev)
2081             atomic_dec(&pm8001_dev->running_req);
2082         break;
2083     case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2084         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2085         ts->resp = SAS_TASK_COMPLETE;
2086         ts->stat = SAS_NAK_R_ERR;
2087         if (pm8001_dev)
2088             atomic_dec(&pm8001_dev->running_req);
2089         break;
2090     case IO_XFER_ERROR_DMA:
2091         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2092         ts->resp = SAS_TASK_COMPLETE;
2093         ts->stat = SAS_OPEN_REJECT;
2094         if (pm8001_dev)
2095             atomic_dec(&pm8001_dev->running_req);
2096         break;
2097     case IO_XFER_OPEN_RETRY_TIMEOUT:
2098         pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2099         ts->resp = SAS_TASK_COMPLETE;
2100         ts->stat = SAS_OPEN_REJECT;
2101         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2102         if (pm8001_dev)
2103             atomic_dec(&pm8001_dev->running_req);
2104         break;
2105     case IO_XFER_ERROR_OFFSET_MISMATCH:
2106         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2107         ts->resp = SAS_TASK_COMPLETE;
2108         ts->stat = SAS_OPEN_REJECT;
2109         if (pm8001_dev)
2110             atomic_dec(&pm8001_dev->running_req);
2111         break;
2112     case IO_PORT_IN_RESET:
2113         pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2114         ts->resp = SAS_TASK_COMPLETE;
2115         ts->stat = SAS_OPEN_REJECT;
2116         if (pm8001_dev)
2117             atomic_dec(&pm8001_dev->running_req);
2118         break;
2119     case IO_DS_NON_OPERATIONAL:
2120         pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2121         ts->resp = SAS_TASK_COMPLETE;
2122         ts->stat = SAS_OPEN_REJECT;
2123         if (!t->uldd_task)
2124             pm8001_handle_event(pm8001_ha,
2125                 pm8001_dev,
2126                 IO_DS_NON_OPERATIONAL);
2127         break;
2128     case IO_DS_IN_RECOVERY:
2129         pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2130         ts->resp = SAS_TASK_COMPLETE;
2131         ts->stat = SAS_OPEN_REJECT;
2132         if (pm8001_dev)
2133             atomic_dec(&pm8001_dev->running_req);
2134         break;
2135     case IO_TM_TAG_NOT_FOUND:
2136         pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2137         ts->resp = SAS_TASK_COMPLETE;
2138         ts->stat = SAS_OPEN_REJECT;
2139         if (pm8001_dev)
2140             atomic_dec(&pm8001_dev->running_req);
2141         break;
2142     case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2143         pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2144         ts->resp = SAS_TASK_COMPLETE;
2145         ts->stat = SAS_OPEN_REJECT;
2146         if (pm8001_dev)
2147             atomic_dec(&pm8001_dev->running_req);
2148         break;
2149     case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2150         pm8001_dbg(pm8001_ha, IO,
2151                "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2152         ts->resp = SAS_TASK_COMPLETE;
2153         ts->stat = SAS_OPEN_REJECT;
2154         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2155         if (pm8001_dev)
2156             atomic_dec(&pm8001_dev->running_req);
2157         break;
2158     default:
2159         pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2160         /* not allowed case. Therefore, return failed status */
2161         ts->resp = SAS_TASK_COMPLETE;
2162         ts->stat = SAS_OPEN_REJECT;
2163         if (pm8001_dev)
2164             atomic_dec(&pm8001_dev->running_req);
2165         break;
2166     }
2167     pm8001_dbg(pm8001_ha, IO, "scsi_status = 0x%x\n ",
2168            psspPayload->ssp_resp_iu.status);
2169     spin_lock_irqsave(&t->task_state_lock, flags);
2170     t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2171     t->task_state_flags |= SAS_TASK_STATE_DONE;
2172     if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2173         spin_unlock_irqrestore(&t->task_state_lock, flags);
2174         pm8001_dbg(pm8001_ha, FAIL,
2175                "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2176                t, status, ts->resp, ts->stat);
2177         pm8001_ccb_task_free(pm8001_ha, ccb);
2178         if (t->slow_task)
2179             complete(&t->slow_task->completion);
2180     } else {
2181         spin_unlock_irqrestore(&t->task_state_lock, flags);
2182         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2183     }
2184 }
2185 
2186 /*See the comments for mpi_ssp_completion */
2187 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2188 {
2189     struct sas_task *t;
2190     unsigned long flags;
2191     struct task_status_struct *ts;
2192     struct pm8001_ccb_info *ccb;
2193     struct pm8001_device *pm8001_dev;
2194     struct ssp_event_resp *psspPayload =
2195         (struct ssp_event_resp *)(piomb + 4);
2196     u32 event = le32_to_cpu(psspPayload->event);
2197     u32 tag = le32_to_cpu(psspPayload->tag);
2198     u32 port_id = le32_to_cpu(psspPayload->port_id);
2199 
2200     ccb = &pm8001_ha->ccb_info[tag];
2201     t = ccb->task;
2202     pm8001_dev = ccb->device;
2203     if (event)
2204         pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2205     if (unlikely(!t || !t->lldd_task || !t->dev))
2206         return;
2207     ts = &t->task_status;
2208     pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2209            port_id, tag, event);
2210     switch (event) {
2211     case IO_OVERFLOW:
2212         pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2213         ts->resp = SAS_TASK_COMPLETE;
2214         ts->stat = SAS_DATA_OVERRUN;
2215         ts->residual = 0;
2216         if (pm8001_dev)
2217             atomic_dec(&pm8001_dev->running_req);
2218         break;
2219     case IO_XFER_ERROR_BREAK:
2220         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2221         pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2222         return;
2223     case IO_XFER_ERROR_PHY_NOT_READY:
2224         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2225         ts->resp = SAS_TASK_COMPLETE;
2226         ts->stat = SAS_OPEN_REJECT;
2227         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2228         break;
2229     case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2230         pm8001_dbg(pm8001_ha, IO,
2231                "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2232         ts->resp = SAS_TASK_COMPLETE;
2233         ts->stat = SAS_OPEN_REJECT;
2234         ts->open_rej_reason = SAS_OREJ_EPROTO;
2235         break;
2236     case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2237         pm8001_dbg(pm8001_ha, IO,
2238                "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2239         ts->resp = SAS_TASK_COMPLETE;
2240         ts->stat = SAS_OPEN_REJECT;
2241         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2242         break;
2243     case IO_OPEN_CNX_ERROR_BREAK:
2244         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2245         ts->resp = SAS_TASK_COMPLETE;
2246         ts->stat = SAS_OPEN_REJECT;
2247         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2248         break;
2249     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2250     case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2251     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2252     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2253     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2254     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2255         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2256         ts->resp = SAS_TASK_COMPLETE;
2257         ts->stat = SAS_OPEN_REJECT;
2258         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2259         if (!t->uldd_task)
2260             pm8001_handle_event(pm8001_ha,
2261                 pm8001_dev,
2262                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2263         break;
2264     case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2265         pm8001_dbg(pm8001_ha, IO,
2266                "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2267         ts->resp = SAS_TASK_COMPLETE;
2268         ts->stat = SAS_OPEN_REJECT;
2269         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2270         break;
2271     case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2272         pm8001_dbg(pm8001_ha, IO,
2273                "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2274         ts->resp = SAS_TASK_COMPLETE;
2275         ts->stat = SAS_OPEN_REJECT;
2276         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2277         break;
2278     case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2279         pm8001_dbg(pm8001_ha, IO,
2280                "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2281         ts->resp = SAS_TASK_COMPLETE;
2282         ts->stat = SAS_OPEN_REJECT;
2283         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2284         break;
2285     case IO_XFER_ERROR_NAK_RECEIVED:
2286         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2287         ts->resp = SAS_TASK_COMPLETE;
2288         ts->stat = SAS_OPEN_REJECT;
2289         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2290         break;
2291     case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2292         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2293         ts->resp = SAS_TASK_COMPLETE;
2294         ts->stat = SAS_NAK_R_ERR;
2295         break;
2296     case IO_XFER_OPEN_RETRY_TIMEOUT:
2297         pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2298         pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2299         return;
2300     case IO_XFER_ERROR_UNEXPECTED_PHASE:
2301         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2302         ts->resp = SAS_TASK_COMPLETE;
2303         ts->stat = SAS_DATA_OVERRUN;
2304         break;
2305     case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2306         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2307         ts->resp = SAS_TASK_COMPLETE;
2308         ts->stat = SAS_DATA_OVERRUN;
2309         break;
2310     case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2311         pm8001_dbg(pm8001_ha, IO,
2312                "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2313         ts->resp = SAS_TASK_COMPLETE;
2314         ts->stat = SAS_DATA_OVERRUN;
2315         break;
2316     case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2317         pm8001_dbg(pm8001_ha, IO,
2318                "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2319         ts->resp = SAS_TASK_COMPLETE;
2320         ts->stat = SAS_DATA_OVERRUN;
2321         break;
2322     case IO_XFER_ERROR_OFFSET_MISMATCH:
2323         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2324         ts->resp = SAS_TASK_COMPLETE;
2325         ts->stat = SAS_DATA_OVERRUN;
2326         break;
2327     case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2328         pm8001_dbg(pm8001_ha, IO,
2329                "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2330         ts->resp = SAS_TASK_COMPLETE;
2331         ts->stat = SAS_DATA_OVERRUN;
2332         break;
2333     case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2334         pm8001_dbg(pm8001_ha, IOERR,
2335                "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2336         /* TBC: used default set values */
2337         ts->resp = SAS_TASK_COMPLETE;
2338         ts->stat = SAS_DATA_OVERRUN;
2339         break;
2340     case IO_XFER_CMD_FRAME_ISSUED:
2341         pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2342         return;
2343     default:
2344         pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2345         /* not allowed case. Therefore, return failed status */
2346         ts->resp = SAS_TASK_COMPLETE;
2347         ts->stat = SAS_DATA_OVERRUN;
2348         break;
2349     }
2350     spin_lock_irqsave(&t->task_state_lock, flags);
2351     t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2352     t->task_state_flags |= SAS_TASK_STATE_DONE;
2353     if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2354         spin_unlock_irqrestore(&t->task_state_lock, flags);
2355         pm8001_dbg(pm8001_ha, FAIL,
2356                "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2357                t, event, ts->resp, ts->stat);
2358         pm8001_ccb_task_free(pm8001_ha, ccb);
2359     } else {
2360         spin_unlock_irqrestore(&t->task_state_lock, flags);
2361         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2362     }
2363 }
2364 
2365 /*See the comments for mpi_ssp_completion */
2366 static void
2367 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha,
2368         struct outbound_queue_table *circularQ, void *piomb)
2369 {
2370     struct sas_task *t;
2371     struct pm8001_ccb_info *ccb;
2372     u32 param;
2373     u32 status;
2374     u32 tag;
2375     int i, j;
2376     u8 sata_addr_low[4];
2377     u32 temp_sata_addr_low, temp_sata_addr_hi;
2378     u8 sata_addr_hi[4];
2379     struct sata_completion_resp *psataPayload;
2380     struct task_status_struct *ts;
2381     struct ata_task_resp *resp ;
2382     u32 *sata_resp;
2383     struct pm8001_device *pm8001_dev;
2384     unsigned long flags;
2385 
2386     psataPayload = (struct sata_completion_resp *)(piomb + 4);
2387     status = le32_to_cpu(psataPayload->status);
2388     param = le32_to_cpu(psataPayload->param);
2389     tag = le32_to_cpu(psataPayload->tag);
2390 
2391     ccb = &pm8001_ha->ccb_info[tag];
2392     t = ccb->task;
2393     pm8001_dev = ccb->device;
2394 
2395     if (t) {
2396         if (t->dev && (t->dev->lldd_dev))
2397             pm8001_dev = t->dev->lldd_dev;
2398     } else {
2399         pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2400         return;
2401     }
2402 
2403     if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2404         && unlikely(!t || !t->lldd_task || !t->dev)) {
2405         pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2406         return;
2407     }
2408 
2409     ts = &t->task_status;
2410 
2411     if (status != IO_SUCCESS) {
2412         pm8001_dbg(pm8001_ha, FAIL,
2413             "IO failed device_id %u status 0x%x tag %d\n",
2414             pm8001_dev->device_id, status, tag);
2415     }
2416 
2417     /* Print sas address of IO failed device */
2418     if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2419         (status != IO_UNDERFLOW)) {
2420         if (!((t->dev->parent) &&
2421             (dev_is_expander(t->dev->parent->dev_type)))) {
2422             for (i = 0, j = 4; i <= 3 && j <= 7; i++, j++)
2423                 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2424             for (i = 0, j = 0; i <= 3 && j <= 3; i++, j++)
2425                 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2426             memcpy(&temp_sata_addr_low, sata_addr_low,
2427                 sizeof(sata_addr_low));
2428             memcpy(&temp_sata_addr_hi, sata_addr_hi,
2429                 sizeof(sata_addr_hi));
2430             temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2431                         |((temp_sata_addr_hi << 8) &
2432                         0xff0000) |
2433                         ((temp_sata_addr_hi >> 8)
2434                         & 0xff00) |
2435                         ((temp_sata_addr_hi << 24) &
2436                         0xff000000));
2437             temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2438                         & 0xff) |
2439                         ((temp_sata_addr_low << 8)
2440                         & 0xff0000) |
2441                         ((temp_sata_addr_low >> 8)
2442                         & 0xff00) |
2443                         ((temp_sata_addr_low << 24)
2444                         & 0xff000000)) +
2445                         pm8001_dev->attached_phy +
2446                         0x10);
2447             pm8001_dbg(pm8001_ha, FAIL,
2448                    "SAS Address of IO Failure Drive:%08x%08x\n",
2449                    temp_sata_addr_hi,
2450                    temp_sata_addr_low);
2451 
2452         } else {
2453             pm8001_dbg(pm8001_ha, FAIL,
2454                    "SAS Address of IO Failure Drive:%016llx\n",
2455                    SAS_ADDR(t->dev->sas_addr));
2456         }
2457     }
2458     switch (status) {
2459     case IO_SUCCESS:
2460         pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2461         if (param == 0) {
2462             ts->resp = SAS_TASK_COMPLETE;
2463             ts->stat = SAS_SAM_STAT_GOOD;
2464             /* check if response is for SEND READ LOG */
2465             if (pm8001_dev &&
2466                 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2467                 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2468                 /* Free the tag */
2469                 pm8001_tag_free(pm8001_ha, tag);
2470                 sas_free_task(t);
2471                 return;
2472             }
2473         } else {
2474             u8 len;
2475             ts->resp = SAS_TASK_COMPLETE;
2476             ts->stat = SAS_PROTO_RESPONSE;
2477             ts->residual = param;
2478             pm8001_dbg(pm8001_ha, IO,
2479                    "SAS_PROTO_RESPONSE len = %d\n",
2480                    param);
2481             sata_resp = &psataPayload->sata_resp[0];
2482             resp = (struct ata_task_resp *)ts->buf;
2483             if (t->ata_task.dma_xfer == 0 &&
2484                 t->data_dir == DMA_FROM_DEVICE) {
2485                 len = sizeof(struct pio_setup_fis);
2486                 pm8001_dbg(pm8001_ha, IO,
2487                        "PIO read len = %d\n", len);
2488             } else if (t->ata_task.use_ncq &&
2489                    t->data_dir != DMA_NONE) {
2490                 len = sizeof(struct set_dev_bits_fis);
2491                 pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2492                        len);
2493             } else {
2494                 len = sizeof(struct dev_to_host_fis);
2495                 pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2496                        len);
2497             }
2498             if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2499                 resp->frame_len = len;
2500                 memcpy(&resp->ending_fis[0], sata_resp, len);
2501                 ts->buf_valid_size = sizeof(*resp);
2502             } else
2503                 pm8001_dbg(pm8001_ha, IO,
2504                        "response too large\n");
2505         }
2506         if (pm8001_dev)
2507             atomic_dec(&pm8001_dev->running_req);
2508         break;
2509     case IO_ABORTED:
2510         pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2511         ts->resp = SAS_TASK_COMPLETE;
2512         ts->stat = SAS_ABORTED_TASK;
2513         if (pm8001_dev)
2514             atomic_dec(&pm8001_dev->running_req);
2515         break;
2516         /* following cases are to do cases */
2517     case IO_UNDERFLOW:
2518         /* SATA Completion with error */
2519         pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2520         ts->resp = SAS_TASK_COMPLETE;
2521         ts->stat = SAS_DATA_UNDERRUN;
2522         ts->residual = param;
2523         if (pm8001_dev)
2524             atomic_dec(&pm8001_dev->running_req);
2525         break;
2526     case IO_NO_DEVICE:
2527         pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2528         ts->resp = SAS_TASK_UNDELIVERED;
2529         ts->stat = SAS_PHY_DOWN;
2530         if (pm8001_dev)
2531             atomic_dec(&pm8001_dev->running_req);
2532         break;
2533     case IO_XFER_ERROR_BREAK:
2534         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2535         ts->resp = SAS_TASK_COMPLETE;
2536         ts->stat = SAS_INTERRUPTED;
2537         if (pm8001_dev)
2538             atomic_dec(&pm8001_dev->running_req);
2539         break;
2540     case IO_XFER_ERROR_PHY_NOT_READY:
2541         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2542         ts->resp = SAS_TASK_COMPLETE;
2543         ts->stat = SAS_OPEN_REJECT;
2544         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2545         if (pm8001_dev)
2546             atomic_dec(&pm8001_dev->running_req);
2547         break;
2548     case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2549         pm8001_dbg(pm8001_ha, IO,
2550                "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2551         ts->resp = SAS_TASK_COMPLETE;
2552         ts->stat = SAS_OPEN_REJECT;
2553         ts->open_rej_reason = SAS_OREJ_EPROTO;
2554         if (pm8001_dev)
2555             atomic_dec(&pm8001_dev->running_req);
2556         break;
2557     case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2558         pm8001_dbg(pm8001_ha, IO,
2559                "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2560         ts->resp = SAS_TASK_COMPLETE;
2561         ts->stat = SAS_OPEN_REJECT;
2562         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2563         if (pm8001_dev)
2564             atomic_dec(&pm8001_dev->running_req);
2565         break;
2566     case IO_OPEN_CNX_ERROR_BREAK:
2567         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2568         ts->resp = SAS_TASK_COMPLETE;
2569         ts->stat = SAS_OPEN_REJECT;
2570         ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2571         if (pm8001_dev)
2572             atomic_dec(&pm8001_dev->running_req);
2573         break;
2574     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2575     case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2576     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2577     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2578     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2579     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2580         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2581         ts->resp = SAS_TASK_COMPLETE;
2582         ts->stat = SAS_DEV_NO_RESPONSE;
2583         if (!t->uldd_task) {
2584             pm8001_handle_event(pm8001_ha,
2585                 pm8001_dev,
2586                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2587             ts->resp = SAS_TASK_UNDELIVERED;
2588             ts->stat = SAS_QUEUE_FULL;
2589             spin_unlock_irqrestore(&circularQ->oq_lock,
2590                     circularQ->lock_flags);
2591             pm8001_ccb_task_free_done(pm8001_ha, ccb);
2592             spin_lock_irqsave(&circularQ->oq_lock,
2593                     circularQ->lock_flags);
2594             return;
2595         }
2596         break;
2597     case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2598         pm8001_dbg(pm8001_ha, IO,
2599                "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2600         ts->resp = SAS_TASK_UNDELIVERED;
2601         ts->stat = SAS_OPEN_REJECT;
2602         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2603         if (!t->uldd_task) {
2604             pm8001_handle_event(pm8001_ha,
2605                 pm8001_dev,
2606                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2607             ts->resp = SAS_TASK_UNDELIVERED;
2608             ts->stat = SAS_QUEUE_FULL;
2609             spin_unlock_irqrestore(&circularQ->oq_lock,
2610                     circularQ->lock_flags);
2611             pm8001_ccb_task_free_done(pm8001_ha, ccb);
2612             spin_lock_irqsave(&circularQ->oq_lock,
2613                     circularQ->lock_flags);
2614             return;
2615         }
2616         break;
2617     case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2618         pm8001_dbg(pm8001_ha, IO,
2619                "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2620         ts->resp = SAS_TASK_COMPLETE;
2621         ts->stat = SAS_OPEN_REJECT;
2622         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2623         if (pm8001_dev)
2624             atomic_dec(&pm8001_dev->running_req);
2625         break;
2626     case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2627         pm8001_dbg(pm8001_ha, IO,
2628                "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2629         ts->resp = SAS_TASK_COMPLETE;
2630         ts->stat = SAS_DEV_NO_RESPONSE;
2631         if (!t->uldd_task) {
2632             pm8001_handle_event(pm8001_ha,
2633                 pm8001_dev,
2634                 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2635             ts->resp = SAS_TASK_UNDELIVERED;
2636             ts->stat = SAS_QUEUE_FULL;
2637             spin_unlock_irqrestore(&circularQ->oq_lock,
2638                     circularQ->lock_flags);
2639             pm8001_ccb_task_free_done(pm8001_ha, ccb);
2640             spin_lock_irqsave(&circularQ->oq_lock,
2641                     circularQ->lock_flags);
2642             return;
2643         }
2644         break;
2645     case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2646         pm8001_dbg(pm8001_ha, IO,
2647                "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2648         ts->resp = SAS_TASK_COMPLETE;
2649         ts->stat = SAS_OPEN_REJECT;
2650         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2651         if (pm8001_dev)
2652             atomic_dec(&pm8001_dev->running_req);
2653         break;
2654     case IO_XFER_ERROR_NAK_RECEIVED:
2655         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2656         ts->resp = SAS_TASK_COMPLETE;
2657         ts->stat = SAS_NAK_R_ERR;
2658         if (pm8001_dev)
2659             atomic_dec(&pm8001_dev->running_req);
2660         break;
2661     case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2662         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2663         ts->resp = SAS_TASK_COMPLETE;
2664         ts->stat = SAS_NAK_R_ERR;
2665         if (pm8001_dev)
2666             atomic_dec(&pm8001_dev->running_req);
2667         break;
2668     case IO_XFER_ERROR_DMA:
2669         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2670         ts->resp = SAS_TASK_COMPLETE;
2671         ts->stat = SAS_ABORTED_TASK;
2672         if (pm8001_dev)
2673             atomic_dec(&pm8001_dev->running_req);
2674         break;
2675     case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2676         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2677         ts->resp = SAS_TASK_UNDELIVERED;
2678         ts->stat = SAS_DEV_NO_RESPONSE;
2679         if (pm8001_dev)
2680             atomic_dec(&pm8001_dev->running_req);
2681         break;
2682     case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2683         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2684         ts->resp = SAS_TASK_COMPLETE;
2685         ts->stat = SAS_DATA_UNDERRUN;
2686         if (pm8001_dev)
2687             atomic_dec(&pm8001_dev->running_req);
2688         break;
2689     case IO_XFER_OPEN_RETRY_TIMEOUT:
2690         pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2691         ts->resp = SAS_TASK_COMPLETE;
2692         ts->stat = SAS_OPEN_TO;
2693         if (pm8001_dev)
2694             atomic_dec(&pm8001_dev->running_req);
2695         break;
2696     case IO_PORT_IN_RESET:
2697         pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2698         ts->resp = SAS_TASK_COMPLETE;
2699         ts->stat = SAS_DEV_NO_RESPONSE;
2700         if (pm8001_dev)
2701             atomic_dec(&pm8001_dev->running_req);
2702         break;
2703     case IO_DS_NON_OPERATIONAL:
2704         pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2705         ts->resp = SAS_TASK_COMPLETE;
2706         ts->stat = SAS_DEV_NO_RESPONSE;
2707         if (!t->uldd_task) {
2708             pm8001_handle_event(pm8001_ha, pm8001_dev,
2709                     IO_DS_NON_OPERATIONAL);
2710             ts->resp = SAS_TASK_UNDELIVERED;
2711             ts->stat = SAS_QUEUE_FULL;
2712             spin_unlock_irqrestore(&circularQ->oq_lock,
2713                     circularQ->lock_flags);
2714             pm8001_ccb_task_free_done(pm8001_ha, ccb);
2715             spin_lock_irqsave(&circularQ->oq_lock,
2716                     circularQ->lock_flags);
2717             return;
2718         }
2719         break;
2720     case IO_DS_IN_RECOVERY:
2721         pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2722         ts->resp = SAS_TASK_COMPLETE;
2723         ts->stat = SAS_DEV_NO_RESPONSE;
2724         if (pm8001_dev)
2725             atomic_dec(&pm8001_dev->running_req);
2726         break;
2727     case IO_DS_IN_ERROR:
2728         pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2729         ts->resp = SAS_TASK_COMPLETE;
2730         ts->stat = SAS_DEV_NO_RESPONSE;
2731         if (!t->uldd_task) {
2732             pm8001_handle_event(pm8001_ha, pm8001_dev,
2733                     IO_DS_IN_ERROR);
2734             ts->resp = SAS_TASK_UNDELIVERED;
2735             ts->stat = SAS_QUEUE_FULL;
2736             spin_unlock_irqrestore(&circularQ->oq_lock,
2737                     circularQ->lock_flags);
2738             pm8001_ccb_task_free_done(pm8001_ha, ccb);
2739             spin_lock_irqsave(&circularQ->oq_lock,
2740                     circularQ->lock_flags);
2741             return;
2742         }
2743         break;
2744     case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2745         pm8001_dbg(pm8001_ha, IO,
2746                "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2747         ts->resp = SAS_TASK_COMPLETE;
2748         ts->stat = SAS_OPEN_REJECT;
2749         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2750         if (pm8001_dev)
2751             atomic_dec(&pm8001_dev->running_req);
2752         break;
2753     default:
2754         pm8001_dbg(pm8001_ha, DEVIO,
2755                 "Unknown status device_id %u status 0x%x tag %d\n",
2756             pm8001_dev->device_id, status, tag);
2757         /* not allowed case. Therefore, return failed status */
2758         ts->resp = SAS_TASK_COMPLETE;
2759         ts->stat = SAS_DEV_NO_RESPONSE;
2760         if (pm8001_dev)
2761             atomic_dec(&pm8001_dev->running_req);
2762         break;
2763     }
2764     spin_lock_irqsave(&t->task_state_lock, flags);
2765     t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2766     t->task_state_flags |= SAS_TASK_STATE_DONE;
2767     if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2768         spin_unlock_irqrestore(&t->task_state_lock, flags);
2769         pm8001_dbg(pm8001_ha, FAIL,
2770                "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2771                t, status, ts->resp, ts->stat);
2772         pm8001_ccb_task_free(pm8001_ha, ccb);
2773         if (t->slow_task)
2774             complete(&t->slow_task->completion);
2775     } else {
2776         spin_unlock_irqrestore(&t->task_state_lock, flags);
2777         spin_unlock_irqrestore(&circularQ->oq_lock,
2778                 circularQ->lock_flags);
2779         pm8001_ccb_task_free_done(pm8001_ha, ccb);
2780         spin_lock_irqsave(&circularQ->oq_lock,
2781                 circularQ->lock_flags);
2782     }
2783 }
2784 
2785 /*See the comments for mpi_ssp_completion */
2786 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha,
2787         struct outbound_queue_table *circularQ, void *piomb)
2788 {
2789     struct sas_task *t;
2790     struct task_status_struct *ts;
2791     struct pm8001_ccb_info *ccb;
2792     struct pm8001_device *pm8001_dev;
2793     struct sata_event_resp *psataPayload =
2794         (struct sata_event_resp *)(piomb + 4);
2795     u32 event = le32_to_cpu(psataPayload->event);
2796     u32 tag = le32_to_cpu(psataPayload->tag);
2797     u32 port_id = le32_to_cpu(psataPayload->port_id);
2798     u32 dev_id = le32_to_cpu(psataPayload->device_id);
2799 
2800     if (event)
2801         pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2802 
2803     /* Check if this is NCQ error */
2804     if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2805         /* find device using device id */
2806         pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2807         /* send read log extension */
2808         if (pm8001_dev)
2809             pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2810         return;
2811     }
2812 
2813     ccb = &pm8001_ha->ccb_info[tag];
2814     t = ccb->task;
2815     pm8001_dev = ccb->device;
2816 
2817     if (unlikely(!t || !t->lldd_task || !t->dev)) {
2818         pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2819         return;
2820     }
2821 
2822     ts = &t->task_status;
2823     pm8001_dbg(pm8001_ha, IOERR, "port_id:0x%x, tag:0x%x, event:0x%x\n",
2824            port_id, tag, event);
2825     switch (event) {
2826     case IO_OVERFLOW:
2827         pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2828         ts->resp = SAS_TASK_COMPLETE;
2829         ts->stat = SAS_DATA_OVERRUN;
2830         ts->residual = 0;
2831         break;
2832     case IO_XFER_ERROR_BREAK:
2833         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2834         ts->resp = SAS_TASK_COMPLETE;
2835         ts->stat = SAS_INTERRUPTED;
2836         break;
2837     case IO_XFER_ERROR_PHY_NOT_READY:
2838         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2839         ts->resp = SAS_TASK_COMPLETE;
2840         ts->stat = SAS_OPEN_REJECT;
2841         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2842         break;
2843     case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2844         pm8001_dbg(pm8001_ha, IO,
2845                "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2846         ts->resp = SAS_TASK_COMPLETE;
2847         ts->stat = SAS_OPEN_REJECT;
2848         ts->open_rej_reason = SAS_OREJ_EPROTO;
2849         break;
2850     case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2851         pm8001_dbg(pm8001_ha, IO,
2852                "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2853         ts->resp = SAS_TASK_COMPLETE;
2854         ts->stat = SAS_OPEN_REJECT;
2855         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2856         break;
2857     case IO_OPEN_CNX_ERROR_BREAK:
2858         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2859         ts->resp = SAS_TASK_COMPLETE;
2860         ts->stat = SAS_OPEN_REJECT;
2861         ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2862         break;
2863     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2864     case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2865     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2866     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2867     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2868     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2869         pm8001_dbg(pm8001_ha, FAIL,
2870                "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2871         ts->resp = SAS_TASK_UNDELIVERED;
2872         ts->stat = SAS_DEV_NO_RESPONSE;
2873         if (!t->uldd_task) {
2874             pm8001_handle_event(pm8001_ha,
2875                 pm8001_dev,
2876                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2877             ts->resp = SAS_TASK_COMPLETE;
2878             ts->stat = SAS_QUEUE_FULL;
2879             return;
2880         }
2881         break;
2882     case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2883         pm8001_dbg(pm8001_ha, IO,
2884                "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2885         ts->resp = SAS_TASK_UNDELIVERED;
2886         ts->stat = SAS_OPEN_REJECT;
2887         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2888         break;
2889     case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2890         pm8001_dbg(pm8001_ha, IO,
2891                "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2892         ts->resp = SAS_TASK_COMPLETE;
2893         ts->stat = SAS_OPEN_REJECT;
2894         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2895         break;
2896     case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2897         pm8001_dbg(pm8001_ha, IO,
2898                "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2899         ts->resp = SAS_TASK_COMPLETE;
2900         ts->stat = SAS_OPEN_REJECT;
2901         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2902         break;
2903     case IO_XFER_ERROR_NAK_RECEIVED:
2904         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2905         ts->resp = SAS_TASK_COMPLETE;
2906         ts->stat = SAS_NAK_R_ERR;
2907         break;
2908     case IO_XFER_ERROR_PEER_ABORTED:
2909         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2910         ts->resp = SAS_TASK_COMPLETE;
2911         ts->stat = SAS_NAK_R_ERR;
2912         break;
2913     case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2914         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2915         ts->resp = SAS_TASK_COMPLETE;
2916         ts->stat = SAS_DATA_UNDERRUN;
2917         break;
2918     case IO_XFER_OPEN_RETRY_TIMEOUT:
2919         pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2920         ts->resp = SAS_TASK_COMPLETE;
2921         ts->stat = SAS_OPEN_TO;
2922         break;
2923     case IO_XFER_ERROR_UNEXPECTED_PHASE:
2924         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2925         ts->resp = SAS_TASK_COMPLETE;
2926         ts->stat = SAS_OPEN_TO;
2927         break;
2928     case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2929         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2930         ts->resp = SAS_TASK_COMPLETE;
2931         ts->stat = SAS_OPEN_TO;
2932         break;
2933     case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2934         pm8001_dbg(pm8001_ha, IO,
2935                "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2936         ts->resp = SAS_TASK_COMPLETE;
2937         ts->stat = SAS_OPEN_TO;
2938         break;
2939     case IO_XFER_ERROR_OFFSET_MISMATCH:
2940         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2941         ts->resp = SAS_TASK_COMPLETE;
2942         ts->stat = SAS_OPEN_TO;
2943         break;
2944     case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2945         pm8001_dbg(pm8001_ha, IO,
2946                "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2947         ts->resp = SAS_TASK_COMPLETE;
2948         ts->stat = SAS_OPEN_TO;
2949         break;
2950     case IO_XFER_CMD_FRAME_ISSUED:
2951         pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2952         break;
2953     case IO_XFER_PIO_SETUP_ERROR:
2954         pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2955         ts->resp = SAS_TASK_COMPLETE;
2956         ts->stat = SAS_OPEN_TO;
2957         break;
2958     case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2959         pm8001_dbg(pm8001_ha, FAIL,
2960                "IO_XFR_ERROR_INTERNAL_CRC_ERROR\n");
2961         /* TBC: used default set values */
2962         ts->resp = SAS_TASK_COMPLETE;
2963         ts->stat = SAS_OPEN_TO;
2964         break;
2965     case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2966         pm8001_dbg(pm8001_ha, FAIL, "IO_XFR_DMA_ACTIVATE_TIMEOUT\n");
2967         /* TBC: used default set values */
2968         ts->resp = SAS_TASK_COMPLETE;
2969         ts->stat = SAS_OPEN_TO;
2970         break;
2971     default:
2972         pm8001_dbg(pm8001_ha, IO, "Unknown status 0x%x\n", event);
2973         /* not allowed case. Therefore, return failed status */
2974         ts->resp = SAS_TASK_COMPLETE;
2975         ts->stat = SAS_OPEN_TO;
2976         break;
2977     }
2978 }
2979 
2980 /*See the comments for mpi_ssp_completion */
2981 static void
2982 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2983 {
2984     u32 param, i;
2985     struct sas_task *t;
2986     struct pm8001_ccb_info *ccb;
2987     unsigned long flags;
2988     u32 status;
2989     u32 tag;
2990     struct smp_completion_resp *psmpPayload;
2991     struct task_status_struct *ts;
2992     struct pm8001_device *pm8001_dev;
2993 
2994     psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2995     status = le32_to_cpu(psmpPayload->status);
2996     tag = le32_to_cpu(psmpPayload->tag);
2997 
2998     ccb = &pm8001_ha->ccb_info[tag];
2999     param = le32_to_cpu(psmpPayload->param);
3000     t = ccb->task;
3001     ts = &t->task_status;
3002     pm8001_dev = ccb->device;
3003     if (status)
3004         pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
3005     if (unlikely(!t || !t->lldd_task || !t->dev))
3006         return;
3007 
3008     pm8001_dbg(pm8001_ha, DEV, "tag::0x%x status::0x%x\n", tag, status);
3009 
3010     switch (status) {
3011 
3012     case IO_SUCCESS:
3013         pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
3014         ts->resp = SAS_TASK_COMPLETE;
3015         ts->stat = SAS_SAM_STAT_GOOD;
3016         if (pm8001_dev)
3017             atomic_dec(&pm8001_dev->running_req);
3018         if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3019             struct scatterlist *sg_resp = &t->smp_task.smp_resp;
3020             u8 *payload;
3021             void *to;
3022 
3023             pm8001_dbg(pm8001_ha, IO,
3024                    "DIRECT RESPONSE Length:%d\n",
3025                    param);
3026             to = kmap_atomic(sg_page(sg_resp));
3027             payload = to + sg_resp->offset;
3028             for (i = 0; i < param; i++) {
3029                 *(payload + i) = psmpPayload->_r_a[i];
3030                 pm8001_dbg(pm8001_ha, IO,
3031                        "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
3032                        i, *(payload + i),
3033                        psmpPayload->_r_a[i]);
3034             }
3035             kunmap_atomic(to);
3036         }
3037         break;
3038     case IO_ABORTED:
3039         pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
3040         ts->resp = SAS_TASK_COMPLETE;
3041         ts->stat = SAS_ABORTED_TASK;
3042         if (pm8001_dev)
3043             atomic_dec(&pm8001_dev->running_req);
3044         break;
3045     case IO_OVERFLOW:
3046         pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
3047         ts->resp = SAS_TASK_COMPLETE;
3048         ts->stat = SAS_DATA_OVERRUN;
3049         ts->residual = 0;
3050         if (pm8001_dev)
3051             atomic_dec(&pm8001_dev->running_req);
3052         break;
3053     case IO_NO_DEVICE:
3054         pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
3055         ts->resp = SAS_TASK_COMPLETE;
3056         ts->stat = SAS_PHY_DOWN;
3057         break;
3058     case IO_ERROR_HW_TIMEOUT:
3059         pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
3060         ts->resp = SAS_TASK_COMPLETE;
3061         ts->stat = SAS_SAM_STAT_BUSY;
3062         break;
3063     case IO_XFER_ERROR_BREAK:
3064         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
3065         ts->resp = SAS_TASK_COMPLETE;
3066         ts->stat = SAS_SAM_STAT_BUSY;
3067         break;
3068     case IO_XFER_ERROR_PHY_NOT_READY:
3069         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
3070         ts->resp = SAS_TASK_COMPLETE;
3071         ts->stat = SAS_SAM_STAT_BUSY;
3072         break;
3073     case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
3074         pm8001_dbg(pm8001_ha, IO,
3075                "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
3076         ts->resp = SAS_TASK_COMPLETE;
3077         ts->stat = SAS_OPEN_REJECT;
3078         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3079         break;
3080     case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
3081         pm8001_dbg(pm8001_ha, IO,
3082                "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
3083         ts->resp = SAS_TASK_COMPLETE;
3084         ts->stat = SAS_OPEN_REJECT;
3085         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3086         break;
3087     case IO_OPEN_CNX_ERROR_BREAK:
3088         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
3089         ts->resp = SAS_TASK_COMPLETE;
3090         ts->stat = SAS_OPEN_REJECT;
3091         ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
3092         break;
3093     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
3094     case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
3095     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
3096     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
3097     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
3098     case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
3099         pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
3100         ts->resp = SAS_TASK_COMPLETE;
3101         ts->stat = SAS_OPEN_REJECT;
3102         ts->open_rej_reason = SAS_OREJ_UNKNOWN;
3103         pm8001_handle_event(pm8001_ha,
3104                 pm8001_dev,
3105                 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
3106         break;
3107     case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
3108         pm8001_dbg(pm8001_ha, IO,
3109                "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
3110         ts->resp = SAS_TASK_COMPLETE;
3111         ts->stat = SAS_OPEN_REJECT;
3112         ts->open_rej_reason = SAS_OREJ_BAD_DEST;
3113         break;
3114     case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
3115         pm8001_dbg(pm8001_ha, IO,
3116                "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
3117         ts->resp = SAS_TASK_COMPLETE;
3118         ts->stat = SAS_OPEN_REJECT;
3119         ts->open_rej_reason = SAS_OREJ_CONN_RATE;
3120         break;
3121     case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
3122         pm8001_dbg(pm8001_ha, IO,
3123                "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
3124         ts->resp = SAS_TASK_COMPLETE;
3125         ts->stat = SAS_OPEN_REJECT;
3126         ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3127         break;
3128     case IO_XFER_ERROR_RX_FRAME:
3129         pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3130         ts->resp = SAS_TASK_COMPLETE;
3131         ts->stat = SAS_DEV_NO_RESPONSE;
3132         break;
3133     case IO_XFER_OPEN_RETRY_TIMEOUT:
3134         pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3135         ts->resp = SAS_TASK_COMPLETE;
3136         ts->stat = SAS_OPEN_REJECT;
3137         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3138         break;
3139     case IO_ERROR_INTERNAL_SMP_RESOURCE:
3140         pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3141         ts->resp = SAS_TASK_COMPLETE;
3142         ts->stat = SAS_QUEUE_FULL;
3143         break;
3144     case IO_PORT_IN_RESET:
3145         pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3146         ts->resp = SAS_TASK_COMPLETE;
3147         ts->stat = SAS_OPEN_REJECT;
3148         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3149         break;
3150     case IO_DS_NON_OPERATIONAL:
3151         pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3152         ts->resp = SAS_TASK_COMPLETE;
3153         ts->stat = SAS_DEV_NO_RESPONSE;
3154         break;
3155     case IO_DS_IN_RECOVERY:
3156         pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3157         ts->resp = SAS_TASK_COMPLETE;
3158         ts->stat = SAS_OPEN_REJECT;
3159         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3160         break;
3161     case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3162         pm8001_dbg(pm8001_ha, IO,
3163                "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3164         ts->resp = SAS_TASK_COMPLETE;
3165         ts->stat = SAS_OPEN_REJECT;
3166         ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3167         break;
3168     default:
3169         pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3170         ts->resp = SAS_TASK_COMPLETE;
3171         ts->stat = SAS_DEV_NO_RESPONSE;
3172         /* not allowed case. Therefore, return failed status */
3173         break;
3174     }
3175     spin_lock_irqsave(&t->task_state_lock, flags);
3176     t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3177     t->task_state_flags |= SAS_TASK_STATE_DONE;
3178     if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3179         spin_unlock_irqrestore(&t->task_state_lock, flags);
3180         pm8001_dbg(pm8001_ha, FAIL,
3181                "task 0x%p done with io_status 0x%x resp 0x%xstat 0x%x but aborted by upper layer!\n",
3182                t, status, ts->resp, ts->stat);
3183         pm8001_ccb_task_free(pm8001_ha, ccb);
3184     } else {
3185         spin_unlock_irqrestore(&t->task_state_lock, flags);
3186         pm8001_ccb_task_free(pm8001_ha, ccb);
3187         mb();/* in order to force CPU ordering */
3188         t->task_done(t);
3189     }
3190 }
3191 
3192 /**
3193  * pm80xx_hw_event_ack_req- For PM8001, some events need to acknowledge to FW.
3194  * @pm8001_ha: our hba card information
3195  * @Qnum: the outbound queue message number.
3196  * @SEA: source of event to ack
3197  * @port_id: port id.
3198  * @phyId: phy id.
3199  * @param0: parameter 0.
3200  * @param1: parameter 1.
3201  */
3202 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3203     u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3204 {
3205     struct hw_event_ack_req  payload;
3206     u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3207 
3208     memset((u8 *)&payload, 0, sizeof(payload));
3209     payload.tag = cpu_to_le32(1);
3210     payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3211         ((phyId & 0xFF) << 24) | (port_id & 0xFF));
3212     payload.param0 = cpu_to_le32(param0);
3213     payload.param1 = cpu_to_le32(param1);
3214 
3215     pm8001_mpi_build_cmd(pm8001_ha, Qnum, opc, &payload,
3216                  sizeof(payload), 0);
3217 }
3218 
3219 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3220     u32 phyId, u32 phy_op);
3221 
3222 static void hw_event_port_recover(struct pm8001_hba_info *pm8001_ha,
3223                     void *piomb)
3224 {
3225     struct hw_event_resp *pPayload = (struct hw_event_resp *)(piomb + 4);
3226     u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3227     u8 phy_id = (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3228     u32 lr_status_evt_portid =
3229         le32_to_cpu(pPayload->lr_status_evt_portid);
3230     u8 deviceType = pPayload->sas_identify.dev_type;
3231     u8 link_rate = (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3232     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3233     u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3234     struct pm8001_port *port = &pm8001_ha->port[port_id];
3235 
3236     if (deviceType == SAS_END_DEVICE) {
3237         pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3238                     PHY_NOTIFY_ENABLE_SPINUP);
3239     }
3240 
3241     port->wide_port_phymap |= (1U << phy_id);
3242     pm8001_get_lrate_mode(phy, link_rate);
3243     phy->sas_phy.oob_mode = SAS_OOB_MODE;
3244     phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3245     phy->phy_attached = 1;
3246 }
3247 
3248 /**
3249  * hw_event_sas_phy_up - FW tells me a SAS phy up event.
3250  * @pm8001_ha: our hba card information
3251  * @piomb: IO message buffer
3252  */
3253 static void
3254 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3255 {
3256     struct hw_event_resp *pPayload =
3257         (struct hw_event_resp *)(piomb + 4);
3258     u32 lr_status_evt_portid =
3259         le32_to_cpu(pPayload->lr_status_evt_portid);
3260     u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3261 
3262     u8 link_rate =
3263         (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3264     u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3265     u8 phy_id =
3266         (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3267     u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3268 
3269     struct pm8001_port *port = &pm8001_ha->port[port_id];
3270     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3271     unsigned long flags;
3272     u8 deviceType = pPayload->sas_identify.dev_type;
3273     phy->port = port;
3274     port->port_id = port_id;
3275     port->port_state = portstate;
3276     port->wide_port_phymap |= (1U << phy_id);
3277     phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3278     pm8001_dbg(pm8001_ha, MSG,
3279            "portid:%d; phyid:%d; linkrate:%d; portstate:%x; devicetype:%x\n",
3280            port_id, phy_id, link_rate, portstate, deviceType);
3281 
3282     switch (deviceType) {
3283     case SAS_PHY_UNUSED:
3284         pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3285         break;
3286     case SAS_END_DEVICE:
3287         pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3288         pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
3289             PHY_NOTIFY_ENABLE_SPINUP);
3290         port->port_attached = 1;
3291         pm8001_get_lrate_mode(phy, link_rate);
3292         break;
3293     case SAS_EDGE_EXPANDER_DEVICE:
3294         pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3295         port->port_attached = 1;
3296         pm8001_get_lrate_mode(phy, link_rate);
3297         break;
3298     case SAS_FANOUT_EXPANDER_DEVICE:
3299         pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3300         port->port_attached = 1;
3301         pm8001_get_lrate_mode(phy, link_rate);
3302         break;
3303     default:
3304         pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3305                deviceType);
3306         break;
3307     }
3308     phy->phy_type |= PORT_TYPE_SAS;
3309     phy->identify.device_type = deviceType;
3310     phy->phy_attached = 1;
3311     if (phy->identify.device_type == SAS_END_DEVICE)
3312         phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3313     else if (phy->identify.device_type != SAS_PHY_UNUSED)
3314         phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3315     phy->sas_phy.oob_mode = SAS_OOB_MODE;
3316     sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3317     spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3318     memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3319         sizeof(struct sas_identify_frame)-4);
3320     phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3321     pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3322     spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3323     if (pm8001_ha->flags == PM8001F_RUN_TIME)
3324         mdelay(200); /* delay a moment to wait for disk to spin up */
3325     pm8001_bytes_dmaed(pm8001_ha, phy_id);
3326 }
3327 
3328 /**
3329  * hw_event_sata_phy_up - FW tells me a SATA phy up event.
3330  * @pm8001_ha: our hba card information
3331  * @piomb: IO message buffer
3332  */
3333 static void
3334 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3335 {
3336     struct hw_event_resp *pPayload =
3337         (struct hw_event_resp *)(piomb + 4);
3338     u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3339     u32 lr_status_evt_portid =
3340         le32_to_cpu(pPayload->lr_status_evt_portid);
3341     u8 link_rate =
3342         (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
3343     u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3344     u8 phy_id =
3345         (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3346 
3347     u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3348 
3349     struct pm8001_port *port = &pm8001_ha->port[port_id];
3350     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3351     unsigned long flags;
3352     pm8001_dbg(pm8001_ha, DEVIO,
3353            "port id %d, phy id %d link_rate %d portstate 0x%x\n",
3354            port_id, phy_id, link_rate, portstate);
3355 
3356     phy->port = port;
3357     port->port_id = port_id;
3358     port->port_state = portstate;
3359     phy->phy_state = PHY_STATE_LINK_UP_SPCV;
3360     port->port_attached = 1;
3361     pm8001_get_lrate_mode(phy, link_rate);
3362     phy->phy_type |= PORT_TYPE_SATA;
3363     phy->phy_attached = 1;
3364     phy->sas_phy.oob_mode = SATA_OOB_MODE;
3365     sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3366     spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3367     memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3368         sizeof(struct dev_to_host_fis));
3369     phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3370     phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3371     phy->identify.device_type = SAS_SATA_DEV;
3372     pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3373     spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3374     pm8001_bytes_dmaed(pm8001_ha, phy_id);
3375 }
3376 
3377 /**
3378  * hw_event_phy_down - we should notify the libsas the phy is down.
3379  * @pm8001_ha: our hba card information
3380  * @piomb: IO message buffer
3381  */
3382 static void
3383 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3384 {
3385     struct hw_event_resp *pPayload =
3386         (struct hw_event_resp *)(piomb + 4);
3387 
3388     u32 lr_status_evt_portid =
3389         le32_to_cpu(pPayload->lr_status_evt_portid);
3390     u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3391     u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3392     u8 phy_id =
3393         (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3394     u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3395 
3396     struct pm8001_port *port = &pm8001_ha->port[port_id];
3397     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3398     u32 port_sata = (phy->phy_type & PORT_TYPE_SATA);
3399     port->port_state = portstate;
3400     phy->identify.device_type = 0;
3401     phy->phy_attached = 0;
3402     switch (portstate) {
3403     case PORT_VALID:
3404         break;
3405     case PORT_INVALID:
3406         pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3407                port_id);
3408         pm8001_dbg(pm8001_ha, MSG,
3409                " Last phy Down and port invalid\n");
3410         if (port_sata) {
3411             phy->phy_type = 0;
3412             port->port_attached = 0;
3413             pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3414                     port_id, phy_id, 0, 0);
3415         }
3416         sas_phy_disconnected(&phy->sas_phy);
3417         break;
3418     case PORT_IN_RESET:
3419         pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3420                port_id);
3421         break;
3422     case PORT_NOT_ESTABLISHED:
3423         pm8001_dbg(pm8001_ha, MSG,
3424                " Phy Down and PORT_NOT_ESTABLISHED\n");
3425         port->port_attached = 0;
3426         break;
3427     case PORT_LOSTCOMM:
3428         pm8001_dbg(pm8001_ha, MSG, " Phy Down and PORT_LOSTCOMM\n");
3429         pm8001_dbg(pm8001_ha, MSG,
3430                " Last phy Down and port invalid\n");
3431         if (port_sata) {
3432             port->port_attached = 0;
3433             phy->phy_type = 0;
3434             pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3435                     port_id, phy_id, 0, 0);
3436         }
3437         sas_phy_disconnected(&phy->sas_phy);
3438         break;
3439     default:
3440         port->port_attached = 0;
3441         pm8001_dbg(pm8001_ha, DEVIO,
3442                " Phy Down and(default) = 0x%x\n",
3443                portstate);
3444         break;
3445 
3446     }
3447     if (port_sata && (portstate != PORT_IN_RESET))
3448         sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3449                 GFP_ATOMIC);
3450 }
3451 
3452 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3453 {
3454     struct phy_start_resp *pPayload =
3455         (struct phy_start_resp *)(piomb + 4);
3456     u32 status =
3457         le32_to_cpu(pPayload->status);
3458     u32 phy_id =
3459         le32_to_cpu(pPayload->phyid) & 0xFF;
3460     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3461 
3462     pm8001_dbg(pm8001_ha, INIT,
3463            "phy start resp status:0x%x, phyid:0x%x\n",
3464            status, phy_id);
3465     if (status == 0)
3466         phy->phy_state = PHY_LINK_DOWN;
3467 
3468     if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3469             phy->enable_completion != NULL) {
3470         complete(phy->enable_completion);
3471         phy->enable_completion = NULL;
3472     }
3473     return 0;
3474 
3475 }
3476 
3477 /**
3478  * mpi_thermal_hw_event - a thermal hw event has come.
3479  * @pm8001_ha: our hba card information
3480  * @piomb: IO message buffer
3481  */
3482 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3483 {
3484     struct thermal_hw_event *pPayload =
3485         (struct thermal_hw_event *)(piomb + 4);
3486 
3487     u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3488     u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3489 
3490     if (thermal_event & 0x40) {
3491         pm8001_dbg(pm8001_ha, IO,
3492                "Thermal Event: Local high temperature violated!\n");
3493         pm8001_dbg(pm8001_ha, IO,
3494                "Thermal Event: Measured local high temperature %d\n",
3495                ((rht_lht & 0xFF00) >> 8));
3496     }
3497     if (thermal_event & 0x10) {
3498         pm8001_dbg(pm8001_ha, IO,
3499                "Thermal Event: Remote high temperature violated!\n");
3500         pm8001_dbg(pm8001_ha, IO,
3501                "Thermal Event: Measured remote high temperature %d\n",
3502                ((rht_lht & 0xFF000000) >> 24));
3503     }
3504     return 0;
3505 }
3506 
3507 /**
3508  * mpi_hw_event - The hw event has come.
3509  * @pm8001_ha: our hba card information
3510  * @piomb: IO message buffer
3511  */
3512 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3513 {
3514     unsigned long flags, i;
3515     struct hw_event_resp *pPayload =
3516         (struct hw_event_resp *)(piomb + 4);
3517     u32 lr_status_evt_portid =
3518         le32_to_cpu(pPayload->lr_status_evt_portid);
3519     u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3520     u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3521     u8 phy_id =
3522         (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3523     u16 eventType =
3524         (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3525     u8 status =
3526         (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3527     struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3528     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3529     struct pm8001_port *port = &pm8001_ha->port[port_id];
3530     struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3531     pm8001_dbg(pm8001_ha, DEV,
3532            "portid:%d phyid:%d event:0x%x status:0x%x\n",
3533            port_id, phy_id, eventType, status);
3534 
3535     switch (eventType) {
3536 
3537     case HW_EVENT_SAS_PHY_UP:
3538         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3539         hw_event_sas_phy_up(pm8001_ha, piomb);
3540         break;
3541     case HW_EVENT_SATA_PHY_UP:
3542         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3543         hw_event_sata_phy_up(pm8001_ha, piomb);
3544         break;
3545     case HW_EVENT_SATA_SPINUP_HOLD:
3546         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3547         sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3548             GFP_ATOMIC);
3549         break;
3550     case HW_EVENT_PHY_DOWN:
3551         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3552         hw_event_phy_down(pm8001_ha, piomb);
3553         if (pm8001_ha->reset_in_progress) {
3554             pm8001_dbg(pm8001_ha, MSG, "Reset in progress\n");
3555             return 0;
3556         }
3557         phy->phy_attached = 0;
3558         phy->phy_state = PHY_LINK_DISABLE;
3559         break;
3560     case HW_EVENT_PORT_INVALID:
3561         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_INVALID\n");
3562         sas_phy_disconnected(sas_phy);
3563         phy->phy_attached = 0;
3564         sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3565             GFP_ATOMIC);
3566         break;
3567     /* the broadcast change primitive received, tell the LIBSAS this event
3568     to revalidate the sas domain*/
3569     case HW_EVENT_BROADCAST_CHANGE:
3570         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_CHANGE\n");
3571         pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3572             port_id, phy_id, 1, 0);
3573         spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3574         sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3575         spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3576         sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3577             GFP_ATOMIC);
3578         break;
3579     case HW_EVENT_PHY_ERROR:
3580         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_ERROR\n");
3581         sas_phy_disconnected(&phy->sas_phy);
3582         phy->phy_attached = 0;
3583         sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR, GFP_ATOMIC);
3584         break;
3585     case HW_EVENT_BROADCAST_EXP:
3586         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_EXP\n");
3587         spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3588         sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3589         spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3590         sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3591             GFP_ATOMIC);
3592         break;
3593     case HW_EVENT_LINK_ERR_INVALID_DWORD:
3594         pm8001_dbg(pm8001_ha, MSG,
3595                "HW_EVENT_LINK_ERR_INVALID_DWORD\n");
3596         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3597             HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3598         break;
3599     case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3600         pm8001_dbg(pm8001_ha, MSG,
3601                "HW_EVENT_LINK_ERR_DISPARITY_ERROR\n");
3602         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3603             HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3604             port_id, phy_id, 0, 0);
3605         break;
3606     case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3607         pm8001_dbg(pm8001_ha, MSG,
3608                "HW_EVENT_LINK_ERR_CODE_VIOLATION\n");
3609         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3610             HW_EVENT_LINK_ERR_CODE_VIOLATION,
3611             port_id, phy_id, 0, 0);
3612         break;
3613     case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3614         pm8001_dbg(pm8001_ha, MSG,
3615                "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n");
3616         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3617             HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3618             port_id, phy_id, 0, 0);
3619         break;
3620     case HW_EVENT_MALFUNCTION:
3621         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_MALFUNCTION\n");
3622         break;
3623     case HW_EVENT_BROADCAST_SES:
3624         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_BROADCAST_SES\n");
3625         spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3626         sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3627         spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3628         sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD,
3629             GFP_ATOMIC);
3630         break;
3631     case HW_EVENT_INBOUND_CRC_ERROR:
3632         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_INBOUND_CRC_ERROR\n");
3633         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3634             HW_EVENT_INBOUND_CRC_ERROR,
3635             port_id, phy_id, 0, 0);
3636         break;
3637     case HW_EVENT_HARD_RESET_RECEIVED:
3638         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_HARD_RESET_RECEIVED\n");
3639         sas_notify_port_event(sas_phy, PORTE_HARD_RESET, GFP_ATOMIC);
3640         break;
3641     case HW_EVENT_ID_FRAME_TIMEOUT:
3642         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_ID_FRAME_TIMEOUT\n");
3643         sas_phy_disconnected(sas_phy);
3644         phy->phy_attached = 0;
3645         sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3646             GFP_ATOMIC);
3647         break;
3648     case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3649         pm8001_dbg(pm8001_ha, MSG,
3650                "HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n");
3651         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3652             HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3653             port_id, phy_id, 0, 0);
3654         sas_phy_disconnected(sas_phy);
3655         phy->phy_attached = 0;
3656         sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3657             GFP_ATOMIC);
3658         break;
3659     case HW_EVENT_PORT_RESET_TIMER_TMO:
3660         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_TIMER_TMO\n");
3661         if (!pm8001_ha->phy[phy_id].reset_completion) {
3662             pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3663                 port_id, phy_id, 0, 0);
3664         }
3665         sas_phy_disconnected(sas_phy);
3666         phy->phy_attached = 0;
3667         sas_notify_port_event(sas_phy, PORTE_LINK_RESET_ERR,
3668             GFP_ATOMIC);
3669         if (pm8001_ha->phy[phy_id].reset_completion) {
3670             pm8001_ha->phy[phy_id].port_reset_status =
3671                     PORT_RESET_TMO;
3672             complete(pm8001_ha->phy[phy_id].reset_completion);
3673             pm8001_ha->phy[phy_id].reset_completion = NULL;
3674         }
3675         break;
3676     case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3677         pm8001_dbg(pm8001_ha, MSG,
3678                "HW_EVENT_PORT_RECOVERY_TIMER_TMO\n");
3679         pm80xx_hw_event_ack_req(pm8001_ha, 0,
3680             HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3681             port_id, phy_id, 0, 0);
3682         for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
3683             if (port->wide_port_phymap & (1 << i)) {
3684                 phy = &pm8001_ha->phy[i];
3685                 sas_notify_phy_event(&phy->sas_phy,
3686                     PHYE_LOSS_OF_SIGNAL, GFP_ATOMIC);
3687                 port->wide_port_phymap &= ~(1 << i);
3688             }
3689         }
3690         break;
3691     case HW_EVENT_PORT_RECOVER:
3692         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RECOVER\n");
3693         hw_event_port_recover(pm8001_ha, piomb);
3694         break;
3695     case HW_EVENT_PORT_RESET_COMPLETE:
3696         pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PORT_RESET_COMPLETE\n");
3697         if (pm8001_ha->phy[phy_id].reset_completion) {
3698             pm8001_ha->phy[phy_id].port_reset_status =
3699                     PORT_RESET_SUCCESS;
3700             complete(pm8001_ha->phy[phy_id].reset_completion);
3701             pm8001_ha->phy[phy_id].reset_completion = NULL;
3702         }
3703         break;
3704     case EVENT_BROADCAST_ASYNCH_EVENT:
3705         pm8001_dbg(pm8001_ha, MSG, "EVENT_BROADCAST_ASYNCH_EVENT\n");
3706         break;
3707     default:
3708         pm8001_dbg(pm8001_ha, DEVIO, "Unknown event type 0x%x\n",
3709                eventType);
3710         break;
3711     }
3712     return 0;
3713 }
3714 
3715 /**
3716  * mpi_phy_stop_resp - SPCv specific
3717  * @pm8001_ha: our hba card information
3718  * @piomb: IO message buffer
3719  */
3720 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3721 {
3722     struct phy_stop_resp *pPayload =
3723         (struct phy_stop_resp *)(piomb + 4);
3724     u32 status =
3725         le32_to_cpu(pPayload->status);
3726     u32 phyid =
3727         le32_to_cpu(pPayload->phyid) & 0xFF;
3728     struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3729     pm8001_dbg(pm8001_ha, MSG, "phy:0x%x status:0x%x\n",
3730            phyid, status);
3731     if (status == PHY_STOP_SUCCESS ||
3732         status == PHY_STOP_ERR_DEVICE_ATTACHED) {
3733         phy->phy_state = PHY_LINK_DISABLE;
3734         phy->sas_phy.phy->negotiated_linkrate = SAS_PHY_DISABLED;
3735         phy->sas_phy.linkrate = SAS_PHY_DISABLED;
3736     }
3737 
3738     return 0;
3739 }
3740 
3741 /**
3742  * mpi_set_controller_config_resp - SPCv specific
3743  * @pm8001_ha: our hba card information
3744  * @piomb: IO message buffer
3745  */
3746 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3747             void *piomb)
3748 {
3749     struct set_ctrl_cfg_resp *pPayload =
3750             (struct set_ctrl_cfg_resp *)(piomb + 4);
3751     u32 status = le32_to_cpu(pPayload->status);
3752     u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3753 
3754     pm8001_dbg(pm8001_ha, MSG,
3755            "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3756            status, err_qlfr_pgcd);
3757 
3758     return 0;
3759 }
3760 
3761 /**
3762  * mpi_get_controller_config_resp - SPCv specific
3763  * @pm8001_ha: our hba card information
3764  * @piomb: IO message buffer
3765  */
3766 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3767             void *piomb)
3768 {
3769     pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3770 
3771     return 0;
3772 }
3773 
3774 /**
3775  * mpi_get_phy_profile_resp - SPCv specific
3776  * @pm8001_ha: our hba card information
3777  * @piomb: IO message buffer
3778  */
3779 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3780             void *piomb)
3781 {
3782     pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3783 
3784     return 0;
3785 }
3786 
3787 /**
3788  * mpi_flash_op_ext_resp - SPCv specific
3789  * @pm8001_ha: our hba card information
3790  * @piomb: IO message buffer
3791  */
3792 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3793 {
3794     pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3795 
3796     return 0;
3797 }
3798 
3799 /**
3800  * mpi_set_phy_profile_resp - SPCv specific
3801  * @pm8001_ha: our hba card information
3802  * @piomb: IO message buffer
3803  */
3804 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3805             void *piomb)
3806 {
3807     u32 tag;
3808     u8 page_code;
3809     int rc = 0;
3810     struct set_phy_profile_resp *pPayload =
3811         (struct set_phy_profile_resp *)(piomb + 4);
3812     u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3813     u32 status = le32_to_cpu(pPayload->status);
3814 
3815     tag = le32_to_cpu(pPayload->tag);
3816     page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3817     if (status) {
3818         /* status is FAILED */
3819         pm8001_dbg(pm8001_ha, FAIL,
3820                "PhyProfile command failed  with status 0x%08X\n",
3821                status);
3822         rc = -1;
3823     } else {
3824         if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3825             pm8001_dbg(pm8001_ha, FAIL, "Invalid page code 0x%X\n",
3826                    page_code);
3827             rc = -1;
3828         }
3829     }
3830     pm8001_tag_free(pm8001_ha, tag);
3831     return rc;
3832 }
3833 
3834 /**
3835  * mpi_kek_management_resp - SPCv specific
3836  * @pm8001_ha: our hba card information
3837  * @piomb: IO message buffer
3838  */
3839 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3840             void *piomb)
3841 {
3842     struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3843 
3844     u32 status = le32_to_cpu(pPayload->status);
3845     u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3846     u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3847 
3848     pm8001_dbg(pm8001_ha, MSG,
3849            "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3850            status, kidx_new_curr_ksop, err_qlfr);
3851 
3852     return 0;
3853 }
3854 
3855 /**
3856  * mpi_dek_management_resp - SPCv specific
3857  * @pm8001_ha: our hba card information
3858  * @piomb: IO message buffer
3859  */
3860 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3861             void *piomb)
3862 {
3863     pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3864 
3865     return 0;
3866 }
3867 
3868 /**
3869  * ssp_coalesced_comp_resp - SPCv specific
3870  * @pm8001_ha: our hba card information
3871  * @piomb: IO message buffer
3872  */
3873 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3874             void *piomb)
3875 {
3876     pm8001_dbg(pm8001_ha, MSG, " pm80xx_addition_functionality\n");
3877 
3878     return 0;
3879 }
3880 
3881 /**
3882  * process_one_iomb - process one outbound Queue memory block
3883  * @pm8001_ha: our hba card information
3884  * @circularQ: outbound circular queue
3885  * @piomb: IO message buffer
3886  */
3887 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha,
3888         struct outbound_queue_table *circularQ, void *piomb)
3889 {
3890     __le32 pHeader = *(__le32 *)piomb;
3891     u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3892 
3893     switch (opc) {
3894     case OPC_OUB_ECHO:
3895         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_ECHO\n");
3896         break;
3897     case OPC_OUB_HW_EVENT:
3898         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_HW_EVENT\n");
3899         mpi_hw_event(pm8001_ha, piomb);
3900         break;
3901     case OPC_OUB_THERM_HW_EVENT:
3902         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_THERMAL_EVENT\n");
3903         mpi_thermal_hw_event(pm8001_ha, piomb);
3904         break;
3905     case OPC_OUB_SSP_COMP:
3906         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_COMP\n");
3907         mpi_ssp_completion(pm8001_ha, piomb);
3908         break;
3909     case OPC_OUB_SMP_COMP:
3910         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_COMP\n");
3911         mpi_smp_completion(pm8001_ha, piomb);
3912         break;
3913     case OPC_OUB_LOCAL_PHY_CNTRL:
3914         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_LOCAL_PHY_CNTRL\n");
3915         pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3916         break;
3917     case OPC_OUB_DEV_REGIST:
3918         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_REGIST\n");
3919         pm8001_mpi_reg_resp(pm8001_ha, piomb);
3920         break;
3921     case OPC_OUB_DEREG_DEV:
3922         pm8001_dbg(pm8001_ha, MSG, "unregister the device\n");
3923         pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3924         break;
3925     case OPC_OUB_GET_DEV_HANDLE:
3926         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEV_HANDLE\n");
3927         break;
3928     case OPC_OUB_SATA_COMP:
3929         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_COMP\n");
3930         mpi_sata_completion(pm8001_ha, circularQ, piomb);
3931         break;
3932     case OPC_OUB_SATA_EVENT:
3933         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_EVENT\n");
3934         mpi_sata_event(pm8001_ha, circularQ, piomb);
3935         break;
3936     case OPC_OUB_SSP_EVENT:
3937         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_EVENT\n");
3938         mpi_ssp_event(pm8001_ha, piomb);
3939         break;
3940     case OPC_OUB_DEV_HANDLE_ARRIV:
3941         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEV_HANDLE_ARRIV\n");
3942         /*This is for target*/
3943         break;
3944     case OPC_OUB_SSP_RECV_EVENT:
3945         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_RECV_EVENT\n");
3946         /*This is for target*/
3947         break;
3948     case OPC_OUB_FW_FLASH_UPDATE:
3949         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_FW_FLASH_UPDATE\n");
3950         pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3951         break;
3952     case OPC_OUB_GPIO_RESPONSE:
3953         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_RESPONSE\n");
3954         break;
3955     case OPC_OUB_GPIO_EVENT:
3956         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GPIO_EVENT\n");
3957         break;
3958     case OPC_OUB_GENERAL_EVENT:
3959         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GENERAL_EVENT\n");
3960         pm8001_mpi_general_event(pm8001_ha, piomb);
3961         break;
3962     case OPC_OUB_SSP_ABORT_RSP:
3963         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SSP_ABORT_RSP\n");
3964         pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3965         break;
3966     case OPC_OUB_SATA_ABORT_RSP:
3967         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SATA_ABORT_RSP\n");
3968         pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3969         break;
3970     case OPC_OUB_SAS_DIAG_MODE_START_END:
3971         pm8001_dbg(pm8001_ha, MSG,
3972                "OPC_OUB_SAS_DIAG_MODE_START_END\n");
3973         break;
3974     case OPC_OUB_SAS_DIAG_EXECUTE:
3975         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_DIAG_EXECUTE\n");
3976         break;
3977     case OPC_OUB_GET_TIME_STAMP:
3978         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_TIME_STAMP\n");
3979         break;
3980     case OPC_OUB_SAS_HW_EVENT_ACK:
3981         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SAS_HW_EVENT_ACK\n");
3982         break;
3983     case OPC_OUB_PORT_CONTROL:
3984         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_PORT_CONTROL\n");
3985         break;
3986     case OPC_OUB_SMP_ABORT_RSP:
3987         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SMP_ABORT_RSP\n");
3988         pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3989         break;
3990     case OPC_OUB_GET_NVMD_DATA:
3991         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_NVMD_DATA\n");
3992         pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3993         break;
3994     case OPC_OUB_SET_NVMD_DATA:
3995         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_NVMD_DATA\n");
3996         pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3997         break;
3998     case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3999         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_DEVICE_HANDLE_REMOVAL\n");
4000         break;
4001     case OPC_OUB_SET_DEVICE_STATE:
4002         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEVICE_STATE\n");
4003         pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
4004         break;
4005     case OPC_OUB_GET_DEVICE_STATE:
4006         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_GET_DEVICE_STATE\n");
4007         break;
4008     case OPC_OUB_SET_DEV_INFO:
4009         pm8001_dbg(pm8001_ha, MSG, "OPC_OUB_SET_DEV_INFO\n");
4010         break;
4011     /* spcv specific commands */
4012     case OPC_OUB_PHY_START_RESP:
4013         pm8001_dbg(pm8001_ha, MSG,
4014                "OPC_OUB_PHY_START_RESP opcode:%x\n", opc);
4015         mpi_phy_start_resp(pm8001_ha, piomb);
4016         break;
4017     case OPC_OUB_PHY_STOP_RESP:
4018         pm8001_dbg(pm8001_ha, MSG,
4019                "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc);
4020         mpi_phy_stop_resp(pm8001_ha, piomb);
4021         break;
4022     case OPC_OUB_SET_CONTROLLER_CONFIG:
4023         pm8001_dbg(pm8001_ha, MSG,
4024                "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc);
4025         mpi_set_controller_config_resp(pm8001_ha, piomb);
4026         break;
4027     case OPC_OUB_GET_CONTROLLER_CONFIG:
4028         pm8001_dbg(pm8001_ha, MSG,
4029                "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc);
4030         mpi_get_controller_config_resp(pm8001_ha, piomb);
4031         break;
4032     case OPC_OUB_GET_PHY_PROFILE:
4033         pm8001_dbg(pm8001_ha, MSG,
4034                "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc);
4035         mpi_get_phy_profile_resp(pm8001_ha, piomb);
4036         break;
4037     case OPC_OUB_FLASH_OP_EXT:
4038         pm8001_dbg(pm8001_ha, MSG,
4039                "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc);
4040         mpi_flash_op_ext_resp(pm8001_ha, piomb);
4041         break;
4042     case OPC_OUB_SET_PHY_PROFILE:
4043         pm8001_dbg(pm8001_ha, MSG,
4044                "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc);
4045         mpi_set_phy_profile_resp(pm8001_ha, piomb);
4046         break;
4047     case OPC_OUB_KEK_MANAGEMENT_RESP:
4048         pm8001_dbg(pm8001_ha, MSG,
4049                "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc);
4050         mpi_kek_management_resp(pm8001_ha, piomb);
4051         break;
4052     case OPC_OUB_DEK_MANAGEMENT_RESP:
4053         pm8001_dbg(pm8001_ha, MSG,
4054                "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc);
4055         mpi_dek_management_resp(pm8001_ha, piomb);
4056         break;
4057     case OPC_OUB_SSP_COALESCED_COMP_RESP:
4058         pm8001_dbg(pm8001_ha, MSG,
4059                "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc);
4060         ssp_coalesced_comp_resp(pm8001_ha, piomb);
4061         break;
4062     default:
4063         pm8001_dbg(pm8001_ha, DEVIO,
4064                "Unknown outbound Queue IOMB OPC = 0x%x\n", opc);
4065         break;
4066     }
4067 }
4068 
4069 static void print_scratchpad_registers(struct pm8001_hba_info *pm8001_ha)
4070 {
4071     pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_0: 0x%x\n",
4072            pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
4073     pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_1:0x%x\n",
4074            pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1));
4075     pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_2: 0x%x\n",
4076            pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2));
4077     pm8001_dbg(pm8001_ha, FAIL, "MSGU_SCRATCH_PAD_3: 0x%x\n",
4078            pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
4079     pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_0: 0x%x\n",
4080            pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0));
4081     pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_1: 0x%x\n",
4082            pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_1));
4083     pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_2: 0x%x\n",
4084            pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_2));
4085     pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_3: 0x%x\n",
4086            pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_3));
4087     pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_4: 0x%x\n",
4088            pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_4));
4089     pm8001_dbg(pm8001_ha, FAIL, "MSGU_HOST_SCRATCH_PAD_5: 0x%x\n",
4090            pm8001_cr32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_5));
4091     pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_0: 0x%x\n",
4092            pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_0));
4093     pm8001_dbg(pm8001_ha, FAIL, "MSGU_RSVD_SCRATCH_PAD_1: 0x%x\n",
4094            pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_RSVD_1));
4095 }
4096 
4097 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
4098 {
4099     struct outbound_queue_table *circularQ;
4100     void *pMsg1 = NULL;
4101     u8 bc;
4102     u32 ret = MPI_IO_STATUS_FAIL;
4103     u32 regval;
4104 
4105     /*
4106      * Fatal errors are programmed to be signalled in irq vector
4107      * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.
4108      * fatal_err_interrupt
4109      */
4110     if (vec == (pm8001_ha->max_q_num - 1)) {
4111         u32 mipsall_ready;
4112 
4113         if (pm8001_ha->chip_id == chip_8008 ||
4114             pm8001_ha->chip_id == chip_8009)
4115             mipsall_ready = SCRATCH_PAD_MIPSALL_READY_8PORT;
4116         else
4117             mipsall_ready = SCRATCH_PAD_MIPSALL_READY_16PORT;
4118 
4119         regval = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
4120         if ((regval & mipsall_ready) != mipsall_ready) {
4121             pm8001_ha->controller_fatal_error = true;
4122             pm8001_dbg(pm8001_ha, FAIL,
4123                    "Firmware Fatal error! Regval:0x%x\n",
4124                    regval);
4125             pm8001_handle_event(pm8001_ha, NULL, IO_FATAL_ERROR);
4126             print_scratchpad_registers(pm8001_ha);
4127             return ret;
4128         } else {
4129             /*read scratchpad rsvd 0 register*/
4130             regval = pm8001_cr32(pm8001_ha, 0,
4131                          MSGU_SCRATCH_PAD_RSVD_0);
4132             switch (regval) {
4133             case NON_FATAL_SPBC_LBUS_ECC_ERR:
4134             case NON_FATAL_BDMA_ERR:
4135             case NON_FATAL_THERM_OVERTEMP_ERR:
4136                 /*Clear the register*/
4137                 pm8001_cw32(pm8001_ha, 0,
4138                         MSGU_SCRATCH_PAD_RSVD_0,
4139                         0x00000000);
4140                 break;
4141             default:
4142                 break;
4143             }
4144         }
4145     }
4146     circularQ = &pm8001_ha->outbnd_q_tbl[vec];
4147     spin_lock_irqsave(&circularQ->oq_lock, circularQ->lock_flags);
4148     do {
4149         /* spurious interrupt during setup if kexec-ing and
4150          * driver doing a doorbell access w/ the pre-kexec oq
4151          * interrupt setup.
4152          */
4153         if (!circularQ->pi_virt)
4154             break;
4155         ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
4156         if (MPI_IO_STATUS_SUCCESS == ret) {
4157             /* process the outbound message */
4158             process_one_iomb(pm8001_ha, circularQ,
4159                         (void *)(pMsg1 - 4));
4160             /* free the message from the outbound circular buffer */
4161             pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
4162                             circularQ, bc);
4163         }
4164         if (MPI_IO_STATUS_BUSY == ret) {
4165             /* Update the producer index from SPC */
4166             circularQ->producer_index =
4167                 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
4168             if (le32_to_cpu(circularQ->producer_index) ==
4169                 circularQ->consumer_idx)
4170                 /* OQ is empty */
4171                 break;
4172         }
4173     } while (1);
4174     spin_unlock_irqrestore(&circularQ->oq_lock, circularQ->lock_flags);
4175     return ret;
4176 }
4177 
4178 /* DMA_... to our direction translation. */
4179 static const u8 data_dir_flags[] = {
4180     [DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT, /* UNSPECIFIED */
4181     [DMA_TO_DEVICE]     = DATA_DIR_OUT,     /* OUTBOUND */
4182     [DMA_FROM_DEVICE]   = DATA_DIR_IN,      /* INBOUND */
4183     [DMA_NONE]      = DATA_DIR_NONE,    /* NO TRANSFER */
4184 };
4185 
4186 static void build_smp_cmd(u32 deviceID, __le32 hTag,
4187             struct smp_req *psmp_cmd, int mode, int length)
4188 {
4189     psmp_cmd->tag = hTag;
4190     psmp_cmd->device_id = cpu_to_le32(deviceID);
4191     if (mode == SMP_DIRECT) {
4192         length = length - 4; /* subtract crc */
4193         psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
4194     } else {
4195         psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
4196     }
4197 }
4198 
4199 /**
4200  * pm80xx_chip_smp_req - send an SMP task to FW
4201  * @pm8001_ha: our hba card information.
4202  * @ccb: the ccb information this request used.
4203  */
4204 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
4205     struct pm8001_ccb_info *ccb)
4206 {
4207     int elem, rc;
4208     struct sas_task *task = ccb->task;
4209     struct domain_device *dev = task->dev;
4210     struct pm8001_device *pm8001_dev = dev->lldd_dev;
4211     struct scatterlist *sg_req, *sg_resp, *smp_req;
4212     u32 req_len, resp_len;
4213     struct smp_req smp_cmd;
4214     u32 opc;
4215     u32 i, length;
4216     u8 *payload;
4217     u8 *to;
4218 
4219     memset(&smp_cmd, 0, sizeof(smp_cmd));
4220     /*
4221      * DMA-map SMP request, response buffers
4222      */
4223     sg_req = &task->smp_task.smp_req;
4224     elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, DMA_TO_DEVICE);
4225     if (!elem)
4226         return -ENOMEM;
4227     req_len = sg_dma_len(sg_req);
4228 
4229     sg_resp = &task->smp_task.smp_resp;
4230     elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, DMA_FROM_DEVICE);
4231     if (!elem) {
4232         rc = -ENOMEM;
4233         goto err_out;
4234     }
4235     resp_len = sg_dma_len(sg_resp);
4236     /* must be in dwords */
4237     if ((req_len & 0x3) || (resp_len & 0x3)) {
4238         rc = -EINVAL;
4239         goto err_out_2;
4240     }
4241 
4242     opc = OPC_INB_SMP_REQUEST;
4243     smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
4244 
4245     length = sg_req->length;
4246     pm8001_dbg(pm8001_ha, IO, "SMP Frame Length %d\n", sg_req->length);
4247     if (!(length - 8))
4248         pm8001_ha->smp_exp_mode = SMP_DIRECT;
4249     else
4250         pm8001_ha->smp_exp_mode = SMP_INDIRECT;
4251 
4252 
4253     smp_req = &task->smp_task.smp_req;
4254     to = kmap_atomic(sg_page(smp_req));
4255     payload = to + smp_req->offset;
4256 
4257     /* INDIRECT MODE command settings. Use DMA */
4258     if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
4259         pm8001_dbg(pm8001_ha, IO, "SMP REQUEST INDIRECT MODE\n");
4260         /* for SPCv indirect mode. Place the top 4 bytes of
4261          * SMP Request header here. */
4262         for (i = 0; i < 4; i++)
4263             smp_cmd.smp_req16[i] = *(payload + i);
4264         /* exclude top 4 bytes for SMP req header */
4265         smp_cmd.long_smp_req.long_req_addr =
4266             cpu_to_le64((u64)sg_dma_address
4267                 (&task->smp_task.smp_req) + 4);
4268         /* exclude 4 bytes for SMP req header and CRC */
4269         smp_cmd.long_smp_req.long_req_size =
4270             cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
4271         smp_cmd.long_smp_req.long_resp_addr =
4272                 cpu_to_le64((u64)sg_dma_address
4273                     (&task->smp_task.smp_resp));
4274         smp_cmd.long_smp_req.long_resp_size =
4275                 cpu_to_le32((u32)sg_dma_len
4276                     (&task->smp_task.smp_resp)-4);
4277     } else { /* DIRECT MODE */
4278         smp_cmd.long_smp_req.long_req_addr =
4279             cpu_to_le64((u64)sg_dma_address
4280                     (&task->smp_task.smp_req));
4281         smp_cmd.long_smp_req.long_req_size =
4282             cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
4283         smp_cmd.long_smp_req.long_resp_addr =
4284             cpu_to_le64((u64)sg_dma_address
4285                 (&task->smp_task.smp_resp));
4286         smp_cmd.long_smp_req.long_resp_size =
4287             cpu_to_le32
4288             ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
4289     }
4290     if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
4291         pm8001_dbg(pm8001_ha, IO, "SMP REQUEST DIRECT MODE\n");
4292         for (i = 0; i < length; i++)
4293             if (i < 16) {
4294                 smp_cmd.smp_req16[i] = *(payload + i);
4295                 pm8001_dbg(pm8001_ha, IO,
4296                        "Byte[%d]:%x (DMA data:%x)\n",
4297                        i, smp_cmd.smp_req16[i],
4298                        *(payload));
4299             } else {
4300                 smp_cmd.smp_req[i] = *(payload + i);
4301                 pm8001_dbg(pm8001_ha, IO,
4302                        "Byte[%d]:%x (DMA data:%x)\n",
4303                        i, smp_cmd.smp_req[i],
4304                        *(payload));
4305             }
4306     }
4307     kunmap_atomic(to);
4308     build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
4309                 &smp_cmd, pm8001_ha->smp_exp_mode, length);
4310     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &smp_cmd,
4311                   sizeof(smp_cmd), 0);
4312     if (rc)
4313         goto err_out_2;
4314     return 0;
4315 
4316 err_out_2:
4317     dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
4318             DMA_FROM_DEVICE);
4319 err_out:
4320     dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
4321             DMA_TO_DEVICE);
4322     return rc;
4323 }
4324 
4325 static int check_enc_sas_cmd(struct sas_task *task)
4326 {
4327     u8 cmd = task->ssp_task.cmd->cmnd[0];
4328 
4329     if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
4330         return 1;
4331     else
4332         return 0;
4333 }
4334 
4335 static int check_enc_sat_cmd(struct sas_task *task)
4336 {
4337     int ret = 0;
4338     switch (task->ata_task.fis.command) {
4339     case ATA_CMD_FPDMA_READ:
4340     case ATA_CMD_READ_EXT:
4341     case ATA_CMD_READ:
4342     case ATA_CMD_FPDMA_WRITE:
4343     case ATA_CMD_WRITE_EXT:
4344     case ATA_CMD_WRITE:
4345     case ATA_CMD_PIO_READ:
4346     case ATA_CMD_PIO_READ_EXT:
4347     case ATA_CMD_PIO_WRITE:
4348     case ATA_CMD_PIO_WRITE_EXT:
4349         ret = 1;
4350         break;
4351     default:
4352         ret = 0;
4353         break;
4354     }
4355     return ret;
4356 }
4357 
4358 static u32 pm80xx_chip_get_q_index(struct sas_task *task)
4359 {
4360     struct scsi_cmnd *scmd = NULL;
4361     u32 blk_tag;
4362 
4363     if (task->uldd_task) {
4364         struct ata_queued_cmd *qc;
4365 
4366         if (dev_is_sata(task->dev)) {
4367             qc = task->uldd_task;
4368             scmd = qc->scsicmd;
4369         } else {
4370             scmd = task->uldd_task;
4371         }
4372     }
4373 
4374     if (!scmd)
4375         return 0;
4376 
4377     blk_tag = blk_mq_unique_tag(scsi_cmd_to_rq(scmd));
4378     return blk_mq_unique_tag_to_hwq(blk_tag);
4379 }
4380 
4381 /**
4382  * pm80xx_chip_ssp_io_req - send an SSP task to FW
4383  * @pm8001_ha: our hba card information.
4384  * @ccb: the ccb information this request used.
4385  */
4386 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
4387     struct pm8001_ccb_info *ccb)
4388 {
4389     struct sas_task *task = ccb->task;
4390     struct domain_device *dev = task->dev;
4391     struct pm8001_device *pm8001_dev = dev->lldd_dev;
4392     struct ssp_ini_io_start_req ssp_cmd;
4393     u32 tag = ccb->ccb_tag;
4394     u64 phys_addr, end_addr;
4395     u32 end_addr_high, end_addr_low;
4396     u32 q_index;
4397     u32 opc = OPC_INB_SSPINIIOSTART;
4398 
4399     memset(&ssp_cmd, 0, sizeof(ssp_cmd));
4400     memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
4401 
4402     /* data address domain added for spcv; set to 0 by host,
4403      * used internally by controller
4404      * 0 for SAS 1.1 and SAS 2.0 compatible TLR
4405      */
4406     ssp_cmd.dad_dir_m_tlr =
4407         cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
4408     ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4409     ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
4410     ssp_cmd.tag = cpu_to_le32(tag);
4411     if (task->ssp_task.enable_first_burst)
4412         ssp_cmd.ssp_iu.efb_prio_attr = 0x80;
4413     ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
4414     ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
4415     memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
4416                task->ssp_task.cmd->cmd_len);
4417     q_index = pm80xx_chip_get_q_index(task);
4418 
4419     /* Check if encryption is set */
4420     if (pm8001_ha->chip->encrypt &&
4421         !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
4422         pm8001_dbg(pm8001_ha, IO,
4423                "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
4424                task->ssp_task.cmd->cmnd[0]);
4425         opc = OPC_INB_SSP_INI_DIF_ENC_IO;
4426         /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
4427         ssp_cmd.dad_dir_m_tlr = cpu_to_le32
4428             ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
4429 
4430         /* fill in PRD (scatter/gather) table, if any */
4431         if (task->num_scatter > 1) {
4432             pm8001_chip_make_sg(task->scatter,
4433                         ccb->n_elem, ccb->buf_prd);
4434             phys_addr = ccb->ccb_dma_handle;
4435             ssp_cmd.enc_addr_low =
4436                 cpu_to_le32(lower_32_bits(phys_addr));
4437             ssp_cmd.enc_addr_high =
4438                 cpu_to_le32(upper_32_bits(phys_addr));
4439             ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4440         } else if (task->num_scatter == 1) {
4441             u64 dma_addr = sg_dma_address(task->scatter);
4442 
4443             ssp_cmd.enc_addr_low =
4444                 cpu_to_le32(lower_32_bits(dma_addr));
4445             ssp_cmd.enc_addr_high =
4446                 cpu_to_le32(upper_32_bits(dma_addr));
4447             ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4448             ssp_cmd.enc_esgl = 0;
4449 
4450             /* Check 4G Boundary */
4451             end_addr = dma_addr + le32_to_cpu(ssp_cmd.enc_len) - 1;
4452             end_addr_low = lower_32_bits(end_addr);
4453             end_addr_high = upper_32_bits(end_addr);
4454 
4455             if (end_addr_high != le32_to_cpu(ssp_cmd.enc_addr_high)) {
4456                 pm8001_dbg(pm8001_ha, FAIL,
4457                        "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4458                        dma_addr,
4459                        le32_to_cpu(ssp_cmd.enc_len),
4460                        end_addr_high, end_addr_low);
4461                 pm8001_chip_make_sg(task->scatter, 1,
4462                     ccb->buf_prd);
4463                 phys_addr = ccb->ccb_dma_handle;
4464                 ssp_cmd.enc_addr_low =
4465                     cpu_to_le32(lower_32_bits(phys_addr));
4466                 ssp_cmd.enc_addr_high =
4467                     cpu_to_le32(upper_32_bits(phys_addr));
4468                 ssp_cmd.enc_esgl = cpu_to_le32(1U<<31);
4469             }
4470         } else if (task->num_scatter == 0) {
4471             ssp_cmd.enc_addr_low = 0;
4472             ssp_cmd.enc_addr_high = 0;
4473             ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4474             ssp_cmd.enc_esgl = 0;
4475         }
4476 
4477         /* XTS mode. All other fields are 0 */
4478         ssp_cmd.key_cmode = cpu_to_le32(0x6 << 4);
4479 
4480         /* set tweak values. Should be the start lba */
4481         ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4482                         (task->ssp_task.cmd->cmnd[3] << 16) |
4483                         (task->ssp_task.cmd->cmnd[4] << 8) |
4484                         (task->ssp_task.cmd->cmnd[5]));
4485     } else {
4486         pm8001_dbg(pm8001_ha, IO,
4487                "Sending Normal SAS command 0x%x inb q %x\n",
4488                task->ssp_task.cmd->cmnd[0], q_index);
4489         /* fill in PRD (scatter/gather) table, if any */
4490         if (task->num_scatter > 1) {
4491             pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4492                     ccb->buf_prd);
4493             phys_addr = ccb->ccb_dma_handle;
4494             ssp_cmd.addr_low =
4495                 cpu_to_le32(lower_32_bits(phys_addr));
4496             ssp_cmd.addr_high =
4497                 cpu_to_le32(upper_32_bits(phys_addr));
4498             ssp_cmd.esgl = cpu_to_le32(1<<31);
4499         } else if (task->num_scatter == 1) {
4500             u64 dma_addr = sg_dma_address(task->scatter);
4501 
4502             ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4503             ssp_cmd.addr_high =
4504                 cpu_to_le32(upper_32_bits(dma_addr));
4505             ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4506             ssp_cmd.esgl = 0;
4507 
4508             /* Check 4G Boundary */
4509             end_addr = dma_addr + le32_to_cpu(ssp_cmd.len) - 1;
4510             end_addr_low = lower_32_bits(end_addr);
4511             end_addr_high = upper_32_bits(end_addr);
4512             if (end_addr_high != le32_to_cpu(ssp_cmd.addr_high)) {
4513                 pm8001_dbg(pm8001_ha, FAIL,
4514                        "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4515                        dma_addr,
4516                        le32_to_cpu(ssp_cmd.len),
4517                        end_addr_high, end_addr_low);
4518                 pm8001_chip_make_sg(task->scatter, 1,
4519                     ccb->buf_prd);
4520                 phys_addr = ccb->ccb_dma_handle;
4521                 ssp_cmd.addr_low =
4522                     cpu_to_le32(lower_32_bits(phys_addr));
4523                 ssp_cmd.addr_high =
4524                     cpu_to_le32(upper_32_bits(phys_addr));
4525                 ssp_cmd.esgl = cpu_to_le32(1<<31);
4526             }
4527         } else if (task->num_scatter == 0) {
4528             ssp_cmd.addr_low = 0;
4529             ssp_cmd.addr_high = 0;
4530             ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4531             ssp_cmd.esgl = 0;
4532         }
4533     }
4534 
4535     return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &ssp_cmd,
4536                     sizeof(ssp_cmd), q_index);
4537 }
4538 
4539 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4540     struct pm8001_ccb_info *ccb)
4541 {
4542     struct sas_task *task = ccb->task;
4543     struct domain_device *dev = task->dev;
4544     struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4545     struct ata_queued_cmd *qc = task->uldd_task;
4546     u32 tag = ccb->ccb_tag, q_index;
4547     struct sata_start_req sata_cmd;
4548     u32 hdr_tag, ncg_tag = 0;
4549     u64 phys_addr, end_addr;
4550     u32 end_addr_high, end_addr_low;
4551     u32 ATAP = 0x0;
4552     u32 dir;
4553     unsigned long flags;
4554     u32 opc = OPC_INB_SATA_HOST_OPSTART;
4555     memset(&sata_cmd, 0, sizeof(sata_cmd));
4556 
4557     q_index = pm80xx_chip_get_q_index(task);
4558 
4559     if (task->data_dir == DMA_NONE && !task->ata_task.use_ncq) {
4560         ATAP = 0x04; /* no data*/
4561         pm8001_dbg(pm8001_ha, IO, "no data\n");
4562     } else if (likely(!task->ata_task.device_control_reg_update)) {
4563         if (task->ata_task.use_ncq &&
4564             dev->sata_dev.class != ATA_DEV_ATAPI) {
4565             ATAP = 0x07; /* FPDMA */
4566             pm8001_dbg(pm8001_ha, IO, "FPDMA\n");
4567         } else if (task->ata_task.dma_xfer) {
4568             ATAP = 0x06; /* DMA */
4569             pm8001_dbg(pm8001_ha, IO, "DMA\n");
4570         } else {
4571             ATAP = 0x05; /* PIO*/
4572             pm8001_dbg(pm8001_ha, IO, "PIO\n");
4573         }
4574     }
4575     if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4576         task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4577         ncg_tag = hdr_tag;
4578     }
4579     dir = data_dir_flags[task->data_dir] << 8;
4580     sata_cmd.tag = cpu_to_le32(tag);
4581     sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4582     sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4583 
4584     sata_cmd.sata_fis = task->ata_task.fis;
4585     if (likely(!task->ata_task.device_control_reg_update))
4586         sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4587     sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4588 
4589     /* Check if encryption is set */
4590     if (pm8001_ha->chip->encrypt &&
4591         !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4592         pm8001_dbg(pm8001_ha, IO,
4593                "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4594                sata_cmd.sata_fis.command);
4595         opc = OPC_INB_SATA_DIF_ENC_IO;
4596 
4597         /* set encryption bit */
4598         sata_cmd.ncqtag_atap_dir_m_dad =
4599             cpu_to_le32(((ncg_tag & 0xff)<<16)|
4600                 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4601                             /* dad (bit 0-1) is 0 */
4602         /* fill in PRD (scatter/gather) table, if any */
4603         if (task->num_scatter > 1) {
4604             pm8001_chip_make_sg(task->scatter,
4605                         ccb->n_elem, ccb->buf_prd);
4606             phys_addr = ccb->ccb_dma_handle;
4607             sata_cmd.enc_addr_low =
4608                 cpu_to_le32(lower_32_bits(phys_addr));
4609             sata_cmd.enc_addr_high =
4610                 cpu_to_le32(upper_32_bits(phys_addr));
4611             sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4612         } else if (task->num_scatter == 1) {
4613             u64 dma_addr = sg_dma_address(task->scatter);
4614 
4615             sata_cmd.enc_addr_low =
4616                 cpu_to_le32(lower_32_bits(dma_addr));
4617             sata_cmd.enc_addr_high =
4618                 cpu_to_le32(upper_32_bits(dma_addr));
4619             sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4620             sata_cmd.enc_esgl = 0;
4621 
4622             /* Check 4G Boundary */
4623             end_addr = dma_addr + le32_to_cpu(sata_cmd.enc_len) - 1;
4624             end_addr_low = lower_32_bits(end_addr);
4625             end_addr_high = upper_32_bits(end_addr);
4626             if (end_addr_high != le32_to_cpu(sata_cmd.enc_addr_high)) {
4627                 pm8001_dbg(pm8001_ha, FAIL,
4628                        "The sg list address start_addr=0x%016llx data_len=0x%x end_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4629                        dma_addr,
4630                        le32_to_cpu(sata_cmd.enc_len),
4631                        end_addr_high, end_addr_low);
4632                 pm8001_chip_make_sg(task->scatter, 1,
4633                     ccb->buf_prd);
4634                 phys_addr = ccb->ccb_dma_handle;
4635                 sata_cmd.enc_addr_low =
4636                     cpu_to_le32(lower_32_bits(phys_addr));
4637                 sata_cmd.enc_addr_high =
4638                     cpu_to_le32(upper_32_bits(phys_addr));
4639                 sata_cmd.enc_esgl =
4640                     cpu_to_le32(1 << 31);
4641             }
4642         } else if (task->num_scatter == 0) {
4643             sata_cmd.enc_addr_low = 0;
4644             sata_cmd.enc_addr_high = 0;
4645             sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4646             sata_cmd.enc_esgl = 0;
4647         }
4648         /* XTS mode. All other fields are 0 */
4649         sata_cmd.key_index_mode = cpu_to_le32(0x6 << 4);
4650 
4651         /* set tweak values. Should be the start lba */
4652         sata_cmd.twk_val0 =
4653             cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4654                     (sata_cmd.sata_fis.lbah << 16) |
4655                     (sata_cmd.sata_fis.lbam << 8) |
4656                     (sata_cmd.sata_fis.lbal));
4657         sata_cmd.twk_val1 =
4658             cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4659                      (sata_cmd.sata_fis.lbam_exp));
4660     } else {
4661         pm8001_dbg(pm8001_ha, IO,
4662                "Sending Normal SATA command 0x%x inb %x\n",
4663                sata_cmd.sata_fis.command, q_index);
4664         /* dad (bit 0-1) is 0 */
4665         sata_cmd.ncqtag_atap_dir_m_dad =
4666             cpu_to_le32(((ncg_tag & 0xff)<<16) |
4667                     ((ATAP & 0x3f) << 10) | dir);
4668 
4669         /* fill in PRD (scatter/gather) table, if any */
4670         if (task->num_scatter > 1) {
4671             pm8001_chip_make_sg(task->scatter,
4672                     ccb->n_elem, ccb->buf_prd);
4673             phys_addr = ccb->ccb_dma_handle;
4674             sata_cmd.addr_low = lower_32_bits(phys_addr);
4675             sata_cmd.addr_high = upper_32_bits(phys_addr);
4676             sata_cmd.esgl = cpu_to_le32(1U << 31);
4677         } else if (task->num_scatter == 1) {
4678             u64 dma_addr = sg_dma_address(task->scatter);
4679 
4680             sata_cmd.addr_low = lower_32_bits(dma_addr);
4681             sata_cmd.addr_high = upper_32_bits(dma_addr);
4682             sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4683             sata_cmd.esgl = 0;
4684 
4685             /* Check 4G Boundary */
4686             end_addr = dma_addr + le32_to_cpu(sata_cmd.len) - 1;
4687             end_addr_low = lower_32_bits(end_addr);
4688             end_addr_high = upper_32_bits(end_addr);
4689             if (end_addr_high != sata_cmd.addr_high) {
4690                 pm8001_dbg(pm8001_ha, FAIL,
4691                        "The sg list address start_addr=0x%016llx data_len=0x%xend_addr_high=0x%08x end_addr_low=0x%08x has crossed 4G boundary\n",
4692                        dma_addr,
4693                        le32_to_cpu(sata_cmd.len),
4694                        end_addr_high, end_addr_low);
4695                 pm8001_chip_make_sg(task->scatter, 1,
4696                     ccb->buf_prd);
4697                 phys_addr = ccb->ccb_dma_handle;
4698                 sata_cmd.addr_low = lower_32_bits(phys_addr);
4699                 sata_cmd.addr_high = upper_32_bits(phys_addr);
4700                 sata_cmd.esgl = cpu_to_le32(1U << 31);
4701             }
4702         } else if (task->num_scatter == 0) {
4703             sata_cmd.addr_low = 0;
4704             sata_cmd.addr_high = 0;
4705             sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4706             sata_cmd.esgl = 0;
4707         }
4708 
4709         /* scsi cdb */
4710         sata_cmd.atapi_scsi_cdb[0] =
4711             cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4712                      (task->ata_task.atapi_packet[1] << 8) |
4713                      (task->ata_task.atapi_packet[2] << 16) |
4714                      (task->ata_task.atapi_packet[3] << 24)));
4715         sata_cmd.atapi_scsi_cdb[1] =
4716             cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4717                      (task->ata_task.atapi_packet[5] << 8) |
4718                      (task->ata_task.atapi_packet[6] << 16) |
4719                      (task->ata_task.atapi_packet[7] << 24)));
4720         sata_cmd.atapi_scsi_cdb[2] =
4721             cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4722                      (task->ata_task.atapi_packet[9] << 8) |
4723                      (task->ata_task.atapi_packet[10] << 16) |
4724                      (task->ata_task.atapi_packet[11] << 24)));
4725         sata_cmd.atapi_scsi_cdb[3] =
4726             cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4727                      (task->ata_task.atapi_packet[13] << 8) |
4728                      (task->ata_task.atapi_packet[14] << 16) |
4729                      (task->ata_task.atapi_packet[15] << 24)));
4730     }
4731 
4732     /* Check for read log for failed drive and return */
4733     if (sata_cmd.sata_fis.command == 0x2f) {
4734         if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4735             (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4736             (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4737             struct task_status_struct *ts;
4738 
4739             pm8001_ha_dev->id &= 0xDFFFFFFF;
4740             ts = &task->task_status;
4741 
4742             spin_lock_irqsave(&task->task_state_lock, flags);
4743             ts->resp = SAS_TASK_COMPLETE;
4744             ts->stat = SAS_SAM_STAT_GOOD;
4745             task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4746             task->task_state_flags |= SAS_TASK_STATE_DONE;
4747             if (unlikely((task->task_state_flags &
4748                     SAS_TASK_STATE_ABORTED))) {
4749                 spin_unlock_irqrestore(&task->task_state_lock,
4750                             flags);
4751                 pm8001_dbg(pm8001_ha, FAIL,
4752                        "task 0x%p resp 0x%x  stat 0x%x but aborted by upper layer\n",
4753                        task, ts->resp,
4754                        ts->stat);
4755                 pm8001_ccb_task_free(pm8001_ha, ccb);
4756                 return 0;
4757             } else {
4758                 spin_unlock_irqrestore(&task->task_state_lock,
4759                             flags);
4760                 pm8001_ccb_task_free_done(pm8001_ha, ccb);
4761                 atomic_dec(&pm8001_ha_dev->running_req);
4762                 return 0;
4763             }
4764         }
4765     }
4766     trace_pm80xx_request_issue(pm8001_ha->id,
4767                 ccb->device ? ccb->device->attached_phy : PM8001_MAX_PHYS,
4768                 ccb->ccb_tag, opc,
4769                 qc ? qc->tf.command : 0, // ata opcode
4770                 ccb->device ? atomic_read(&ccb->device->running_req) : 0);
4771     return pm8001_mpi_build_cmd(pm8001_ha, q_index, opc, &sata_cmd,
4772                     sizeof(sata_cmd), q_index);
4773 }
4774 
4775 /**
4776  * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4777  * @pm8001_ha: our hba card information.
4778  * @phy_id: the phy id which we wanted to start up.
4779  */
4780 static int
4781 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4782 {
4783     struct phy_start_req payload;
4784     u32 tag = 0x01;
4785     u32 opcode = OPC_INB_PHYSTART;
4786 
4787     memset(&payload, 0, sizeof(payload));
4788     payload.tag = cpu_to_le32(tag);
4789 
4790     pm8001_dbg(pm8001_ha, INIT, "PHY START REQ for phy_id %d\n", phy_id);
4791 
4792     payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4793             LINKMODE_AUTO | pm8001_ha->link_rate | phy_id);
4794     /* SSC Disable and SAS Analog ST configuration */
4795     /*
4796     payload.ase_sh_lm_slr_phyid =
4797         cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4798         LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4799         phy_id);
4800     Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4801     */
4802 
4803     payload.sas_identify.dev_type = SAS_END_DEVICE;
4804     payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4805     memcpy(payload.sas_identify.sas_addr,
4806       &pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4807     payload.sas_identify.phy_id = phy_id;
4808 
4809     return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4810                     sizeof(payload), 0);
4811 }
4812 
4813 /**
4814  * pm80xx_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4815  * @pm8001_ha: our hba card information.
4816  * @phy_id: the phy id which we wanted to start up.
4817  */
4818 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4819     u8 phy_id)
4820 {
4821     struct phy_stop_req payload;
4822     u32 tag = 0x01;
4823     u32 opcode = OPC_INB_PHYSTOP;
4824 
4825     memset(&payload, 0, sizeof(payload));
4826     payload.tag = cpu_to_le32(tag);
4827     payload.phy_id = cpu_to_le32(phy_id);
4828 
4829     return pm8001_mpi_build_cmd(pm8001_ha, 0, opcode, &payload,
4830                     sizeof(payload), 0);
4831 }
4832 
4833 /*
4834  * see comments on pm8001_mpi_reg_resp.
4835  */
4836 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4837     struct pm8001_device *pm8001_dev, u32 flag)
4838 {
4839     struct reg_dev_req payload;
4840     u32 opc;
4841     u32 stp_sspsmp_sata = 0x4;
4842     u32 linkrate, phy_id;
4843     int rc;
4844     struct pm8001_ccb_info *ccb;
4845     u8 retryFlag = 0x1;
4846     u16 firstBurstSize = 0;
4847     u16 ITNT = 2000;
4848     struct domain_device *dev = pm8001_dev->sas_device;
4849     struct domain_device *parent_dev = dev->parent;
4850     struct pm8001_port *port = dev->port->lldd_port;
4851 
4852     memset(&payload, 0, sizeof(payload));
4853     ccb = pm8001_ccb_alloc(pm8001_ha, pm8001_dev, NULL);
4854     if (!ccb)
4855         return -SAS_QUEUE_FULL;
4856 
4857     payload.tag = cpu_to_le32(ccb->ccb_tag);
4858 
4859     if (flag == 1) {
4860         stp_sspsmp_sata = 0x02; /*direct attached sata */
4861     } else {
4862         if (pm8001_dev->dev_type == SAS_SATA_DEV)
4863             stp_sspsmp_sata = 0x00; /* stp*/
4864         else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4865             dev_is_expander(pm8001_dev->dev_type))
4866             stp_sspsmp_sata = 0x01; /*ssp or smp*/
4867     }
4868     if (parent_dev && dev_is_expander(parent_dev->dev_type))
4869         phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4870     else
4871         phy_id = pm8001_dev->attached_phy;
4872 
4873     opc = OPC_INB_REG_DEV;
4874 
4875     linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4876             pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4877 
4878     payload.phyid_portid =
4879         cpu_to_le32(((port->port_id) & 0xFF) |
4880         ((phy_id & 0xFF) << 8));
4881 
4882     payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4883         ((linkrate & 0x0F) << 24) |
4884         ((stp_sspsmp_sata & 0x03) << 28));
4885     payload.firstburstsize_ITNexustimeout =
4886         cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4887 
4888     memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4889         SAS_ADDR_SIZE);
4890 
4891     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4892             sizeof(payload), 0);
4893     if (rc)
4894         pm8001_ccb_free(pm8001_ha, ccb);
4895 
4896     return rc;
4897 }
4898 
4899 /**
4900  * pm80xx_chip_phy_ctl_req - support the local phy operation
4901  * @pm8001_ha: our hba card information.
4902  * @phyId: the phy id which we wanted to operate
4903  * @phy_op: phy operation to request
4904  */
4905 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4906     u32 phyId, u32 phy_op)
4907 {
4908     u32 tag;
4909     int rc;
4910     struct local_phy_ctl_req payload;
4911     u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4912 
4913     memset(&payload, 0, sizeof(payload));
4914     rc = pm8001_tag_alloc(pm8001_ha, &tag);
4915     if (rc)
4916         return rc;
4917 
4918     payload.tag = cpu_to_le32(tag);
4919     payload.phyop_phyid =
4920         cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4921 
4922     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4923                   sizeof(payload), 0);
4924     if (rc)
4925         pm8001_tag_free(pm8001_ha, tag);
4926 
4927     return rc;
4928 }
4929 
4930 static u32 pm80xx_chip_is_our_interrupt(struct pm8001_hba_info *pm8001_ha)
4931 {
4932 #ifdef PM8001_USE_MSIX
4933     return 1;
4934 #else
4935     u32 value;
4936 
4937     value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4938     if (value)
4939         return 1;
4940     return 0;
4941 #endif
4942 }
4943 
4944 /**
4945  * pm80xx_chip_isr - PM8001 isr handler.
4946  * @pm8001_ha: our hba card information.
4947  * @vec: irq number.
4948  */
4949 static irqreturn_t
4950 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4951 {
4952     pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4953     pm8001_dbg(pm8001_ha, DEVIO,
4954            "irq vec %d, ODMR:0x%x\n",
4955            vec, pm8001_cr32(pm8001_ha, 0, 0x30));
4956     process_oq(pm8001_ha, vec);
4957     pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4958     return IRQ_HANDLED;
4959 }
4960 
4961 static void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4962                     u32 operation, u32 phyid,
4963                     u32 length, u32 *buf)
4964 {
4965     u32 tag, i, j = 0;
4966     int rc;
4967     struct set_phy_profile_req payload;
4968     u32 opc = OPC_INB_SET_PHY_PROFILE;
4969 
4970     memset(&payload, 0, sizeof(payload));
4971     rc = pm8001_tag_alloc(pm8001_ha, &tag);
4972     if (rc) {
4973         pm8001_dbg(pm8001_ha, FAIL, "Invalid tag\n");
4974         return;
4975     }
4976 
4977     payload.tag = cpu_to_le32(tag);
4978     payload.ppc_phyid =
4979         cpu_to_le32(((operation & 0xF) << 8) | (phyid  & 0xFF));
4980     pm8001_dbg(pm8001_ha, INIT,
4981            " phy profile command for phy %x ,length is %d\n",
4982            le32_to_cpu(payload.ppc_phyid), length);
4983     for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4984         payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4985         j++;
4986     }
4987     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
4988                   sizeof(payload), 0);
4989     if (rc)
4990         pm8001_tag_free(pm8001_ha, tag);
4991 }
4992 
4993 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4994     u32 length, u8 *buf)
4995 {
4996     u32 i;
4997 
4998     for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4999         mpi_set_phy_profile_req(pm8001_ha,
5000             SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
5001         length = length + PHY_DWORD_LENGTH;
5002     }
5003     pm8001_dbg(pm8001_ha, INIT, "phy settings completed\n");
5004 }
5005 
5006 void pm8001_set_phy_profile_single(struct pm8001_hba_info *pm8001_ha,
5007         u32 phy, u32 length, u32 *buf)
5008 {
5009     u32 tag, opc;
5010     int rc, i;
5011     struct set_phy_profile_req payload;
5012 
5013     memset(&payload, 0, sizeof(payload));
5014 
5015     rc = pm8001_tag_alloc(pm8001_ha, &tag);
5016     if (rc) {
5017         pm8001_dbg(pm8001_ha, INIT, "Invalid tag\n");
5018         return;
5019     }
5020 
5021     opc = OPC_INB_SET_PHY_PROFILE;
5022 
5023     payload.tag = cpu_to_le32(tag);
5024     payload.ppc_phyid =
5025         cpu_to_le32(((SAS_PHY_ANALOG_SETTINGS_PAGE & 0xF) << 8)
5026                 | (phy & 0xFF));
5027 
5028     for (i = 0; i < length; i++)
5029         payload.reserved[i] = cpu_to_le32(*(buf + i));
5030 
5031     rc = pm8001_mpi_build_cmd(pm8001_ha, 0, opc, &payload,
5032             sizeof(payload), 0);
5033     if (rc)
5034         pm8001_tag_free(pm8001_ha, tag);
5035 
5036     pm8001_dbg(pm8001_ha, INIT, "PHY %d settings applied\n", phy);
5037 }
5038 const struct pm8001_dispatch pm8001_80xx_dispatch = {
5039     .name           = "pmc80xx",
5040     .chip_init      = pm80xx_chip_init,
5041     .chip_post_init     = pm80xx_chip_post_init,
5042     .chip_soft_rst      = pm80xx_chip_soft_rst,
5043     .chip_rst       = pm80xx_hw_chip_rst,
5044     .chip_iounmap       = pm8001_chip_iounmap,
5045     .isr            = pm80xx_chip_isr,
5046     .is_our_interrupt   = pm80xx_chip_is_our_interrupt,
5047     .isr_process_oq     = process_oq,
5048     .interrupt_enable   = pm80xx_chip_interrupt_enable,
5049     .interrupt_disable  = pm80xx_chip_interrupt_disable,
5050     .make_prd       = pm8001_chip_make_sg,
5051     .smp_req        = pm80xx_chip_smp_req,
5052     .ssp_io_req     = pm80xx_chip_ssp_io_req,
5053     .sata_req       = pm80xx_chip_sata_req,
5054     .phy_start_req      = pm80xx_chip_phy_start_req,
5055     .phy_stop_req       = pm80xx_chip_phy_stop_req,
5056     .reg_dev_req        = pm80xx_chip_reg_dev_req,
5057     .dereg_dev_req      = pm8001_chip_dereg_dev_req,
5058     .phy_ctl_req        = pm80xx_chip_phy_ctl_req,
5059     .task_abort     = pm8001_chip_abort_task,
5060     .ssp_tm_req     = pm8001_chip_ssp_tm_req,
5061     .get_nvmd_req       = pm8001_chip_get_nvmd_req,
5062     .set_nvmd_req       = pm8001_chip_set_nvmd_req,
5063     .fw_flash_update_req    = pm8001_chip_fw_flash_update_req,
5064     .set_dev_state_req  = pm8001_chip_set_dev_state_req,
5065     .fatal_errors       = pm80xx_fatal_errors,
5066     .hw_event_ack_req   = pm80xx_hw_event_ack_req,
5067 };
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