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0001 /*
0002  * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
0003  *
0004  * Copyright (c) 2008-2009 USI Co., Ltd.
0005  * All rights reserved.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions, and the following disclaimer,
0012  *    without modification.
0013  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
0014  *    substantially similar to the "NO WARRANTY" disclaimer below
0015  *    ("Disclaimer") and any redistribution must be conditioned upon
0016  *    including a substantially similar Disclaimer requirement for further
0017  *    binary redistribution.
0018  * 3. Neither the names of the above-listed copyright holders nor the names
0019  *    of any contributors may be used to endorse or promote products derived
0020  *    from this software without specific prior written permission.
0021  *
0022  * Alternatively, this software may be distributed under the terms of the
0023  * GNU General Public License ("GPL") version 2 as published by the Free
0024  * Software Foundation.
0025  *
0026  * NO WARRANTY
0027  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0028  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0029  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
0030  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0031  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0032  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0033  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0034  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0035  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0036  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGES.
0038  *
0039  */
0040 
0041 #include <linux/slab.h>
0042 #include "pm8001_sas.h"
0043 #include "pm8001_chips.h"
0044 #include "pm80xx_hwi.h"
0045 
0046 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING;
0047 module_param(logging_level, ulong, 0644);
0048 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
0049 
0050 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
0051 module_param(link_rate, ulong, 0644);
0052 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
0053         " 1: Link rate 1.5G\n"
0054         " 2: Link rate 3.0G\n"
0055         " 4: Link rate 6.0G\n"
0056         " 8: Link rate 12.0G\n");
0057 
0058 static struct scsi_transport_template *pm8001_stt;
0059 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
0060 
0061 /*
0062  * chip info structure to identify chip key functionality as
0063  * encryption available/not, no of ports, hw specific function ref
0064  */
0065 static const struct pm8001_chip_info pm8001_chips[] = {
0066     [chip_8001] = {0,  8, &pm8001_8001_dispatch,},
0067     [chip_8008] = {0,  8, &pm8001_80xx_dispatch,},
0068     [chip_8009] = {1,  8, &pm8001_80xx_dispatch,},
0069     [chip_8018] = {0,  16, &pm8001_80xx_dispatch,},
0070     [chip_8019] = {1,  16, &pm8001_80xx_dispatch,},
0071     [chip_8074] = {0,  8, &pm8001_80xx_dispatch,},
0072     [chip_8076] = {0,  16, &pm8001_80xx_dispatch,},
0073     [chip_8077] = {0,  16, &pm8001_80xx_dispatch,},
0074     [chip_8006] = {0,  16, &pm8001_80xx_dispatch,},
0075     [chip_8070] = {0,  8, &pm8001_80xx_dispatch,},
0076     [chip_8072] = {0,  16, &pm8001_80xx_dispatch,},
0077 };
0078 static int pm8001_id;
0079 
0080 LIST_HEAD(hba_list);
0081 
0082 struct workqueue_struct *pm8001_wq;
0083 
0084 static int pm8001_map_queues(struct Scsi_Host *shost)
0085 {
0086     struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
0087     struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
0088     struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
0089 
0090     if (pm8001_ha->number_of_intr > 1)
0091         blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
0092 
0093     return blk_mq_map_queues(qmap);
0094 }
0095 
0096 /*
0097  * The main structure which LLDD must register for scsi core.
0098  */
0099 static struct scsi_host_template pm8001_sht = {
0100     .module         = THIS_MODULE,
0101     .name           = DRV_NAME,
0102     .queuecommand       = sas_queuecommand,
0103     .dma_need_drain     = ata_scsi_dma_need_drain,
0104     .target_alloc       = sas_target_alloc,
0105     .slave_configure    = sas_slave_configure,
0106     .scan_finished      = pm8001_scan_finished,
0107     .scan_start     = pm8001_scan_start,
0108     .change_queue_depth = sas_change_queue_depth,
0109     .bios_param     = sas_bios_param,
0110     .can_queue      = 1,
0111     .this_id        = -1,
0112     .sg_tablesize       = PM8001_MAX_DMA_SG,
0113     .max_sectors        = SCSI_DEFAULT_MAX_SECTORS,
0114     .eh_device_reset_handler = sas_eh_device_reset_handler,
0115     .eh_target_reset_handler = sas_eh_target_reset_handler,
0116     .slave_alloc        = sas_slave_alloc,
0117     .target_destroy     = sas_target_destroy,
0118     .ioctl          = sas_ioctl,
0119 #ifdef CONFIG_COMPAT
0120     .compat_ioctl       = sas_ioctl,
0121 #endif
0122     .shost_groups       = pm8001_host_groups,
0123     .track_queue_depth  = 1,
0124     .cmd_per_lun        = 32,
0125     .map_queues     = pm8001_map_queues,
0126 };
0127 
0128 /*
0129  * Sas layer call this function to execute specific task.
0130  */
0131 static struct sas_domain_function_template pm8001_transport_ops = {
0132     .lldd_dev_found     = pm8001_dev_found,
0133     .lldd_dev_gone      = pm8001_dev_gone,
0134 
0135     .lldd_execute_task  = pm8001_queue_command,
0136     .lldd_control_phy   = pm8001_phy_control,
0137 
0138     .lldd_abort_task    = pm8001_abort_task,
0139     .lldd_abort_task_set    = sas_abort_task_set,
0140     .lldd_clear_task_set    = pm8001_clear_task_set,
0141     .lldd_I_T_nexus_reset   = pm8001_I_T_nexus_reset,
0142     .lldd_lu_reset      = pm8001_lu_reset,
0143     .lldd_query_task    = pm8001_query_task,
0144     .lldd_port_formed   = pm8001_port_formed,
0145     .lldd_tmf_exec_complete = pm8001_setds_completion,
0146     .lldd_tmf_aborted   = pm8001_tmf_aborted,
0147 };
0148 
0149 /**
0150  * pm8001_phy_init - initiate our adapter phys
0151  * @pm8001_ha: our hba structure.
0152  * @phy_id: phy id.
0153  */
0154 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
0155 {
0156     struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
0157     struct asd_sas_phy *sas_phy = &phy->sas_phy;
0158     phy->phy_state = PHY_LINK_DISABLE;
0159     phy->pm8001_ha = pm8001_ha;
0160     phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
0161     phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
0162     sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
0163     sas_phy->class = SAS;
0164     sas_phy->iproto = SAS_PROTOCOL_ALL;
0165     sas_phy->tproto = 0;
0166     sas_phy->type = PHY_TYPE_PHYSICAL;
0167     sas_phy->role = PHY_ROLE_INITIATOR;
0168     sas_phy->oob_mode = OOB_NOT_CONNECTED;
0169     sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
0170     sas_phy->id = phy_id;
0171     sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
0172     sas_phy->frame_rcvd = &phy->frame_rcvd[0];
0173     sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
0174     sas_phy->lldd_phy = phy;
0175 }
0176 
0177 /**
0178  * pm8001_free - free hba
0179  * @pm8001_ha:  our hba structure.
0180  */
0181 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
0182 {
0183     int i;
0184 
0185     if (!pm8001_ha)
0186         return;
0187 
0188     for (i = 0; i < USI_MAX_MEMCNT; i++) {
0189         if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
0190             dma_free_coherent(&pm8001_ha->pdev->dev,
0191                 (pm8001_ha->memoryMap.region[i].total_len +
0192                 pm8001_ha->memoryMap.region[i].alignment),
0193                 pm8001_ha->memoryMap.region[i].virt_ptr,
0194                 pm8001_ha->memoryMap.region[i].phys_addr);
0195             }
0196     }
0197     PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
0198     flush_workqueue(pm8001_wq);
0199     bitmap_free(pm8001_ha->tags);
0200     kfree(pm8001_ha);
0201 }
0202 
0203 #ifdef PM8001_USE_TASKLET
0204 
0205 /**
0206  * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
0207  * @opaque: the passed general host adapter struct
0208  * Note: pm8001_tasklet is common for pm8001 & pm80xx
0209  */
0210 static void pm8001_tasklet(unsigned long opaque)
0211 {
0212     struct pm8001_hba_info *pm8001_ha;
0213     struct isr_param *irq_vector;
0214 
0215     irq_vector = (struct isr_param *)opaque;
0216     pm8001_ha = irq_vector->drv_inst;
0217     if (unlikely(!pm8001_ha))
0218         BUG_ON(1);
0219     PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
0220 }
0221 #endif
0222 
0223 /**
0224  * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
0225  * It obtains the vector number and calls the equivalent bottom
0226  * half or services directly.
0227  * @irq: interrupt number
0228  * @opaque: the passed outbound queue/vector. Host structure is
0229  * retrieved from the same.
0230  */
0231 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
0232 {
0233     struct isr_param *irq_vector;
0234     struct pm8001_hba_info *pm8001_ha;
0235     irqreturn_t ret = IRQ_HANDLED;
0236     irq_vector = (struct isr_param *)opaque;
0237     pm8001_ha = irq_vector->drv_inst;
0238 
0239     if (unlikely(!pm8001_ha))
0240         return IRQ_NONE;
0241     if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
0242         return IRQ_NONE;
0243 #ifdef PM8001_USE_TASKLET
0244     tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
0245 #else
0246     ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
0247 #endif
0248     return ret;
0249 }
0250 
0251 /**
0252  * pm8001_interrupt_handler_intx - main INTx interrupt handler.
0253  * @irq: interrupt number
0254  * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
0255  */
0256 
0257 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
0258 {
0259     struct pm8001_hba_info *pm8001_ha;
0260     irqreturn_t ret = IRQ_HANDLED;
0261     struct sas_ha_struct *sha = dev_id;
0262     pm8001_ha = sha->lldd_ha;
0263     if (unlikely(!pm8001_ha))
0264         return IRQ_NONE;
0265     if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
0266         return IRQ_NONE;
0267 
0268 #ifdef PM8001_USE_TASKLET
0269     tasklet_schedule(&pm8001_ha->tasklet[0]);
0270 #else
0271     ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
0272 #endif
0273     return ret;
0274 }
0275 
0276 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha);
0277 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
0278 
0279 /**
0280  * pm8001_alloc - initiate our hba structure and 6 DMAs area.
0281  * @pm8001_ha: our hba structure.
0282  * @ent: PCI device ID structure to match on
0283  */
0284 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
0285             const struct pci_device_id *ent)
0286 {
0287     int i, count = 0, rc = 0;
0288     u32 ci_offset, ib_offset, ob_offset, pi_offset;
0289     struct inbound_queue_table *ibq;
0290     struct outbound_queue_table *obq;
0291 
0292     spin_lock_init(&pm8001_ha->lock);
0293     spin_lock_init(&pm8001_ha->bitmap_lock);
0294     pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
0295            pm8001_ha->chip->n_phy);
0296 
0297     /* Setup Interrupt */
0298     rc = pm8001_setup_irq(pm8001_ha);
0299     if (rc) {
0300         pm8001_dbg(pm8001_ha, FAIL,
0301                "pm8001_setup_irq failed [ret: %d]\n", rc);
0302         goto err_out;
0303     }
0304     /* Request Interrupt */
0305     rc = pm8001_request_irq(pm8001_ha);
0306     if (rc)
0307         goto err_out;
0308 
0309     count = pm8001_ha->max_q_num;
0310     /* Queues are chosen based on the number of cores/msix availability */
0311     ib_offset = pm8001_ha->ib_offset  = USI_MAX_MEMCNT_BASE;
0312     ci_offset = pm8001_ha->ci_offset  = ib_offset + count;
0313     ob_offset = pm8001_ha->ob_offset  = ci_offset + count;
0314     pi_offset = pm8001_ha->pi_offset  = ob_offset + count;
0315     pm8001_ha->max_memcnt = pi_offset + count;
0316 
0317     for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
0318         pm8001_phy_init(pm8001_ha, i);
0319         pm8001_ha->port[i].wide_port_phymap = 0;
0320         pm8001_ha->port[i].port_attached = 0;
0321         pm8001_ha->port[i].port_state = 0;
0322         INIT_LIST_HEAD(&pm8001_ha->port[i].list);
0323     }
0324 
0325     /* MPI Memory region 1 for AAP Event Log for fw */
0326     pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
0327     pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
0328     pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
0329     pm8001_ha->memoryMap.region[AAP1].alignment = 32;
0330 
0331     /* MPI Memory region 2 for IOP Event Log for fw */
0332     pm8001_ha->memoryMap.region[IOP].num_elements = 1;
0333     pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
0334     pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
0335     pm8001_ha->memoryMap.region[IOP].alignment = 32;
0336 
0337     for (i = 0; i < count; i++) {
0338         ibq = &pm8001_ha->inbnd_q_tbl[i];
0339         spin_lock_init(&ibq->iq_lock);
0340         /* MPI Memory region 3 for consumer Index of inbound queues */
0341         pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
0342         pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
0343         pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
0344         pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
0345 
0346         if ((ent->driver_data) != chip_8001) {
0347             /* MPI Memory region 5 inbound queues */
0348             pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
0349                         PM8001_MPI_QUEUE;
0350             pm8001_ha->memoryMap.region[ib_offset+i].element_size
0351                                 = 128;
0352             pm8001_ha->memoryMap.region[ib_offset+i].total_len =
0353                         PM8001_MPI_QUEUE * 128;
0354             pm8001_ha->memoryMap.region[ib_offset+i].alignment
0355                                 = 128;
0356         } else {
0357             pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
0358                         PM8001_MPI_QUEUE;
0359             pm8001_ha->memoryMap.region[ib_offset+i].element_size
0360                                 = 64;
0361             pm8001_ha->memoryMap.region[ib_offset+i].total_len =
0362                         PM8001_MPI_QUEUE * 64;
0363             pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
0364         }
0365     }
0366 
0367     for (i = 0; i < count; i++) {
0368         obq = &pm8001_ha->outbnd_q_tbl[i];
0369         spin_lock_init(&obq->oq_lock);
0370         /* MPI Memory region 4 for producer Index of outbound queues */
0371         pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
0372         pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
0373         pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
0374         pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
0375 
0376         if (ent->driver_data != chip_8001) {
0377             /* MPI Memory region 6 Outbound queues */
0378             pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
0379                         PM8001_MPI_QUEUE;
0380             pm8001_ha->memoryMap.region[ob_offset+i].element_size
0381                                 = 128;
0382             pm8001_ha->memoryMap.region[ob_offset+i].total_len =
0383                         PM8001_MPI_QUEUE * 128;
0384             pm8001_ha->memoryMap.region[ob_offset+i].alignment
0385                                 = 128;
0386         } else {
0387             /* MPI Memory region 6 Outbound queues */
0388             pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
0389                         PM8001_MPI_QUEUE;
0390             pm8001_ha->memoryMap.region[ob_offset+i].element_size
0391                                 = 64;
0392             pm8001_ha->memoryMap.region[ob_offset+i].total_len =
0393                         PM8001_MPI_QUEUE * 64;
0394             pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
0395         }
0396 
0397     }
0398     /* Memory region write DMA*/
0399     pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
0400     pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
0401     pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
0402 
0403     /* Memory region for fw flash */
0404     pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
0405 
0406     pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
0407     pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
0408     pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
0409     pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
0410     for (i = 0; i < pm8001_ha->max_memcnt; i++) {
0411         struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
0412 
0413         if (pm8001_mem_alloc(pm8001_ha->pdev,
0414                      &region->virt_ptr,
0415                      &region->phys_addr,
0416                      &region->phys_addr_hi,
0417                      &region->phys_addr_lo,
0418                      region->total_len,
0419                      region->alignment) != 0) {
0420             pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
0421             goto err_out;
0422         }
0423     }
0424 
0425     /* Memory region for devices*/
0426     pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
0427                 * sizeof(struct pm8001_device), GFP_KERNEL);
0428     if (!pm8001_ha->devices) {
0429         rc = -ENOMEM;
0430         goto err_out_nodev;
0431     }
0432     for (i = 0; i < PM8001_MAX_DEVICES; i++) {
0433         pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
0434         pm8001_ha->devices[i].id = i;
0435         pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
0436         atomic_set(&pm8001_ha->devices[i].running_req, 0);
0437     }
0438     pm8001_ha->flags = PM8001F_INIT_TIME;
0439     /* Initialize tags */
0440     pm8001_tag_init(pm8001_ha);
0441     return 0;
0442 
0443 err_out_nodev:
0444     for (i = 0; i < pm8001_ha->max_memcnt; i++) {
0445         if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
0446             dma_free_coherent(&pm8001_ha->pdev->dev,
0447                 (pm8001_ha->memoryMap.region[i].total_len +
0448                 pm8001_ha->memoryMap.region[i].alignment),
0449                 pm8001_ha->memoryMap.region[i].virt_ptr,
0450                 pm8001_ha->memoryMap.region[i].phys_addr);
0451         }
0452     }
0453 err_out:
0454     return 1;
0455 }
0456 
0457 /**
0458  * pm8001_ioremap - remap the pci high physical address to kernel virtual
0459  * address so that we can access them.
0460  * @pm8001_ha: our hba structure.
0461  */
0462 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
0463 {
0464     u32 bar;
0465     u32 logicalBar = 0;
0466     struct pci_dev *pdev;
0467 
0468     pdev = pm8001_ha->pdev;
0469     /* map pci mem (PMC pci base 0-3)*/
0470     for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
0471         /*
0472         ** logical BARs for SPC:
0473         ** bar 0 and 1 - logical BAR0
0474         ** bar 2 and 3 - logical BAR1
0475         ** bar4 - logical BAR2
0476         ** bar5 - logical BAR3
0477         ** Skip the appropriate assignments:
0478         */
0479         if ((bar == 1) || (bar == 3))
0480             continue;
0481         if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
0482             pm8001_ha->io_mem[logicalBar].membase =
0483                 pci_resource_start(pdev, bar);
0484             pm8001_ha->io_mem[logicalBar].memsize =
0485                 pci_resource_len(pdev, bar);
0486             pm8001_ha->io_mem[logicalBar].memvirtaddr =
0487                 ioremap(pm8001_ha->io_mem[logicalBar].membase,
0488                 pm8001_ha->io_mem[logicalBar].memsize);
0489             if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
0490                 pm8001_dbg(pm8001_ha, INIT,
0491                     "Failed to ioremap bar %d, logicalBar %d",
0492                    bar, logicalBar);
0493                 return -ENOMEM;
0494             }
0495             pm8001_dbg(pm8001_ha, INIT,
0496                    "base addr %llx virt_addr=%llx len=%d\n",
0497                    (u64)pm8001_ha->io_mem[logicalBar].membase,
0498                    (u64)(unsigned long)
0499                    pm8001_ha->io_mem[logicalBar].memvirtaddr,
0500                    pm8001_ha->io_mem[logicalBar].memsize);
0501         } else {
0502             pm8001_ha->io_mem[logicalBar].membase   = 0;
0503             pm8001_ha->io_mem[logicalBar].memsize   = 0;
0504             pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
0505         }
0506         logicalBar++;
0507     }
0508     return 0;
0509 }
0510 
0511 /**
0512  * pm8001_pci_alloc - initialize our ha card structure
0513  * @pdev: pci device.
0514  * @ent: ent
0515  * @shost: scsi host struct which has been initialized before.
0516  */
0517 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
0518                  const struct pci_device_id *ent,
0519                 struct Scsi_Host *shost)
0520 
0521 {
0522     struct pm8001_hba_info *pm8001_ha;
0523     struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
0524     int j;
0525 
0526     pm8001_ha = sha->lldd_ha;
0527     if (!pm8001_ha)
0528         return NULL;
0529 
0530     pm8001_ha->pdev = pdev;
0531     pm8001_ha->dev = &pdev->dev;
0532     pm8001_ha->chip_id = ent->driver_data;
0533     pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
0534     pm8001_ha->irq = pdev->irq;
0535     pm8001_ha->sas = sha;
0536     pm8001_ha->shost = shost;
0537     pm8001_ha->id = pm8001_id++;
0538     pm8001_ha->logging_level = logging_level;
0539     pm8001_ha->non_fatal_count = 0;
0540     if (link_rate >= 1 && link_rate <= 15)
0541         pm8001_ha->link_rate = (link_rate << 8);
0542     else {
0543         pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
0544             LINKRATE_60 | LINKRATE_120;
0545         pm8001_dbg(pm8001_ha, FAIL,
0546                "Setting link rate to default value\n");
0547     }
0548     sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
0549     /* IOMB size is 128 for 8088/89 controllers */
0550     if (pm8001_ha->chip_id != chip_8001)
0551         pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
0552     else
0553         pm8001_ha->iomb_size = IOMB_SIZE_SPC;
0554 
0555 #ifdef PM8001_USE_TASKLET
0556     /* Tasklet for non msi-x interrupt handler */
0557     if ((!pdev->msix_cap || !pci_msi_enabled())
0558         || (pm8001_ha->chip_id == chip_8001))
0559         tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
0560             (unsigned long)&(pm8001_ha->irq_vector[0]));
0561     else
0562         for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
0563             tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
0564                 (unsigned long)&(pm8001_ha->irq_vector[j]));
0565 #endif
0566     if (pm8001_ioremap(pm8001_ha))
0567         goto failed_pci_alloc;
0568     if (!pm8001_alloc(pm8001_ha, ent))
0569         return pm8001_ha;
0570 failed_pci_alloc:
0571     pm8001_free(pm8001_ha);
0572     return NULL;
0573 }
0574 
0575 /**
0576  * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
0577  * @pdev: pci device.
0578  */
0579 static int pci_go_44(struct pci_dev *pdev)
0580 {
0581     int rc;
0582 
0583     rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
0584     if (rc) {
0585         rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
0586         if (rc)
0587             dev_printk(KERN_ERR, &pdev->dev,
0588                 "32-bit DMA enable failed\n");
0589     }
0590     return rc;
0591 }
0592 
0593 /**
0594  * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
0595  * @shost: scsi host which has been allocated outside.
0596  * @chip_info: our ha struct.
0597  */
0598 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
0599                    const struct pm8001_chip_info *chip_info)
0600 {
0601     int phy_nr, port_nr;
0602     struct asd_sas_phy **arr_phy;
0603     struct asd_sas_port **arr_port;
0604     struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
0605 
0606     phy_nr = chip_info->n_phy;
0607     port_nr = phy_nr;
0608     memset(sha, 0x00, sizeof(*sha));
0609     arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
0610     if (!arr_phy)
0611         goto exit;
0612     arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
0613     if (!arr_port)
0614         goto exit_free2;
0615 
0616     sha->sas_phy = arr_phy;
0617     sha->sas_port = arr_port;
0618     sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
0619     if (!sha->lldd_ha)
0620         goto exit_free1;
0621 
0622     shost->transportt = pm8001_stt;
0623     shost->max_id = PM8001_MAX_DEVICES;
0624     shost->unique_id = pm8001_id;
0625     shost->max_cmd_len = 16;
0626     return 0;
0627 exit_free1:
0628     kfree(arr_port);
0629 exit_free2:
0630     kfree(arr_phy);
0631 exit:
0632     return -1;
0633 }
0634 
0635 /**
0636  * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
0637  * @shost: scsi host which has been allocated outside
0638  * @chip_info: our ha struct.
0639  */
0640 static void  pm8001_post_sas_ha_init(struct Scsi_Host *shost,
0641                      const struct pm8001_chip_info *chip_info)
0642 {
0643     int i = 0;
0644     struct pm8001_hba_info *pm8001_ha;
0645     struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
0646 
0647     pm8001_ha = sha->lldd_ha;
0648     for (i = 0; i < chip_info->n_phy; i++) {
0649         sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
0650         sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
0651         sha->sas_phy[i]->sas_addr =
0652             (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
0653     }
0654     sha->sas_ha_name = DRV_NAME;
0655     sha->dev = pm8001_ha->dev;
0656     sha->strict_wide_ports = 1;
0657     sha->lldd_module = THIS_MODULE;
0658     sha->sas_addr = &pm8001_ha->sas_addr[0];
0659     sha->num_phys = chip_info->n_phy;
0660     sha->core.shost = shost;
0661 }
0662 
0663 /**
0664  * pm8001_init_sas_add - initialize sas address
0665  * @pm8001_ha: our ha struct.
0666  *
0667  * Currently we just set the fixed SAS address to our HBA, for manufacture,
0668  * it should read from the EEPROM
0669  */
0670 static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
0671 {
0672     u8 i, j;
0673     u8 sas_add[8];
0674 #ifdef PM8001_READ_VPD
0675     /* For new SPC controllers WWN is stored in flash vpd
0676     *  For SPC/SPCve controllers WWN is stored in EEPROM
0677     *  For Older SPC WWN is stored in NVMD
0678     */
0679     DECLARE_COMPLETION_ONSTACK(completion);
0680     struct pm8001_ioctl_payload payload;
0681     u16 deviceid;
0682     int rc;
0683 
0684     pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
0685     pm8001_ha->nvmd_completion = &completion;
0686 
0687     if (pm8001_ha->chip_id == chip_8001) {
0688         if (deviceid == 0x8081 || deviceid == 0x0042) {
0689             payload.minor_function = 4;
0690             payload.rd_length = 4096;
0691         } else {
0692             payload.minor_function = 0;
0693             payload.rd_length = 128;
0694         }
0695     } else if ((pm8001_ha->chip_id == chip_8070 ||
0696             pm8001_ha->chip_id == chip_8072) &&
0697             pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
0698         payload.minor_function = 4;
0699         payload.rd_length = 4096;
0700     } else {
0701         payload.minor_function = 1;
0702         payload.rd_length = 4096;
0703     }
0704     payload.offset = 0;
0705     payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
0706     if (!payload.func_specific) {
0707         pm8001_dbg(pm8001_ha, INIT, "mem alloc fail\n");
0708         return;
0709     }
0710     rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
0711     if (rc) {
0712         kfree(payload.func_specific);
0713         pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
0714         return;
0715     }
0716     wait_for_completion(&completion);
0717 
0718     for (i = 0, j = 0; i <= 7; i++, j++) {
0719         if (pm8001_ha->chip_id == chip_8001) {
0720             if (deviceid == 0x8081)
0721                 pm8001_ha->sas_addr[j] =
0722                     payload.func_specific[0x704 + i];
0723             else if (deviceid == 0x0042)
0724                 pm8001_ha->sas_addr[j] =
0725                     payload.func_specific[0x010 + i];
0726         } else if ((pm8001_ha->chip_id == chip_8070 ||
0727                 pm8001_ha->chip_id == chip_8072) &&
0728                 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
0729             pm8001_ha->sas_addr[j] =
0730                     payload.func_specific[0x010 + i];
0731         } else
0732             pm8001_ha->sas_addr[j] =
0733                     payload.func_specific[0x804 + i];
0734     }
0735     memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
0736     for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
0737         if (i && ((i % 4) == 0))
0738             sas_add[7] = sas_add[7] + 4;
0739         memcpy(&pm8001_ha->phy[i].dev_sas_addr,
0740             sas_add, SAS_ADDR_SIZE);
0741         pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
0742                pm8001_ha->phy[i].dev_sas_addr);
0743     }
0744     kfree(payload.func_specific);
0745 #else
0746     for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
0747         pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
0748         pm8001_ha->phy[i].dev_sas_addr =
0749             cpu_to_be64((u64)
0750                 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
0751     }
0752     memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
0753         SAS_ADDR_SIZE);
0754 #endif
0755 }
0756 
0757 /*
0758  * pm8001_get_phy_settings_info : Read phy setting values.
0759  * @pm8001_ha : our hba.
0760  */
0761 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
0762 {
0763 
0764 #ifdef PM8001_READ_VPD
0765     /*OPTION ROM FLASH read for the SPC cards */
0766     DECLARE_COMPLETION_ONSTACK(completion);
0767     struct pm8001_ioctl_payload payload;
0768     int rc;
0769 
0770     pm8001_ha->nvmd_completion = &completion;
0771     /* SAS ADDRESS read from flash / EEPROM */
0772     payload.minor_function = 6;
0773     payload.offset = 0;
0774     payload.rd_length = 4096;
0775     payload.func_specific = kzalloc(4096, GFP_KERNEL);
0776     if (!payload.func_specific)
0777         return -ENOMEM;
0778     /* Read phy setting values from flash */
0779     rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
0780     if (rc) {
0781         kfree(payload.func_specific);
0782         pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
0783         return -ENOMEM;
0784     }
0785     wait_for_completion(&completion);
0786     pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
0787     kfree(payload.func_specific);
0788 #endif
0789     return 0;
0790 }
0791 
0792 struct pm8001_mpi3_phy_pg_trx_config {
0793     u32 LaneLosCfg;
0794     u32 LanePgaCfg1;
0795     u32 LanePisoCfg1;
0796     u32 LanePisoCfg2;
0797     u32 LanePisoCfg3;
0798     u32 LanePisoCfg4;
0799     u32 LanePisoCfg5;
0800     u32 LanePisoCfg6;
0801     u32 LaneBctCtrl;
0802 };
0803 
0804 /**
0805  * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
0806  * @pm8001_ha : our adapter
0807  * @phycfg : PHY config page to populate
0808  */
0809 static
0810 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
0811         struct pm8001_mpi3_phy_pg_trx_config *phycfg)
0812 {
0813     phycfg->LaneLosCfg   = 0x00000132;
0814     phycfg->LanePgaCfg1  = 0x00203949;
0815     phycfg->LanePisoCfg1 = 0x000000FF;
0816     phycfg->LanePisoCfg2 = 0xFF000001;
0817     phycfg->LanePisoCfg3 = 0xE7011300;
0818     phycfg->LanePisoCfg4 = 0x631C40C0;
0819     phycfg->LanePisoCfg5 = 0xF8102036;
0820     phycfg->LanePisoCfg6 = 0xF74A1000;
0821     phycfg->LaneBctCtrl  = 0x00FB33F8;
0822 }
0823 
0824 /**
0825  * pm8001_get_external_phy_settings - Retrieves the external PHY settings
0826  * @pm8001_ha : our adapter
0827  * @phycfg : PHY config page to populate
0828  */
0829 static
0830 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
0831         struct pm8001_mpi3_phy_pg_trx_config *phycfg)
0832 {
0833     phycfg->LaneLosCfg   = 0x00000132;
0834     phycfg->LanePgaCfg1  = 0x00203949;
0835     phycfg->LanePisoCfg1 = 0x000000FF;
0836     phycfg->LanePisoCfg2 = 0xFF000001;
0837     phycfg->LanePisoCfg3 = 0xE7011300;
0838     phycfg->LanePisoCfg4 = 0x63349140;
0839     phycfg->LanePisoCfg5 = 0xF8102036;
0840     phycfg->LanePisoCfg6 = 0xF80D9300;
0841     phycfg->LaneBctCtrl  = 0x00FB33F8;
0842 }
0843 
0844 /**
0845  * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
0846  * @pm8001_ha : our adapter
0847  * @phymask : The PHY mask
0848  */
0849 static
0850 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
0851 {
0852     switch (pm8001_ha->pdev->subsystem_device) {
0853     case 0x0070: /* H1280 - 8 external 0 internal */
0854     case 0x0072: /* H12F0 - 16 external 0 internal */
0855         *phymask = 0x0000;
0856         break;
0857 
0858     case 0x0071: /* H1208 - 0 external 8 internal */
0859     case 0x0073: /* H120F - 0 external 16 internal */
0860         *phymask = 0xFFFF;
0861         break;
0862 
0863     case 0x0080: /* H1244 - 4 external 4 internal */
0864         *phymask = 0x00F0;
0865         break;
0866 
0867     case 0x0081: /* H1248 - 4 external 8 internal */
0868         *phymask = 0x0FF0;
0869         break;
0870 
0871     case 0x0082: /* H1288 - 8 external 8 internal */
0872         *phymask = 0xFF00;
0873         break;
0874 
0875     default:
0876         pm8001_dbg(pm8001_ha, INIT,
0877                "Unknown subsystem device=0x%.04x\n",
0878                pm8001_ha->pdev->subsystem_device);
0879     }
0880 }
0881 
0882 /**
0883  * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
0884  * @pm8001_ha : our adapter
0885  */
0886 static
0887 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
0888 {
0889     struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
0890     struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
0891     int phymask = 0;
0892     int i = 0;
0893 
0894     memset(&phycfg_int, 0, sizeof(phycfg_int));
0895     memset(&phycfg_ext, 0, sizeof(phycfg_ext));
0896 
0897     pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
0898     pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
0899     pm8001_get_phy_mask(pm8001_ha, &phymask);
0900 
0901     for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
0902         if (phymask & (1 << i)) {/* Internal PHY */
0903             pm8001_set_phy_profile_single(pm8001_ha, i,
0904                     sizeof(phycfg_int) / sizeof(u32),
0905                     (u32 *)&phycfg_int);
0906 
0907         } else { /* External PHY */
0908             pm8001_set_phy_profile_single(pm8001_ha, i,
0909                     sizeof(phycfg_ext) / sizeof(u32),
0910                     (u32 *)&phycfg_ext);
0911         }
0912     }
0913 
0914     return 0;
0915 }
0916 
0917 /**
0918  * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
0919  * @pm8001_ha : our hba.
0920  */
0921 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
0922 {
0923     switch (pm8001_ha->pdev->subsystem_vendor) {
0924     case PCI_VENDOR_ID_ATTO:
0925         if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
0926             return 0;
0927         else
0928             return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
0929 
0930     case PCI_VENDOR_ID_ADAPTEC2:
0931     case 0:
0932         return 0;
0933 
0934     default:
0935         return pm8001_get_phy_settings_info(pm8001_ha);
0936     }
0937 }
0938 
0939 #ifdef PM8001_USE_MSIX
0940 /**
0941  * pm8001_setup_msix - enable MSI-X interrupt
0942  * @pm8001_ha: our ha struct.
0943  */
0944 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
0945 {
0946     unsigned int allocated_irq_vectors;
0947     int rc;
0948 
0949     /* SPCv controllers supports 64 msi-x */
0950     if (pm8001_ha->chip_id == chip_8001) {
0951         rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
0952                        PCI_IRQ_MSIX);
0953     } else {
0954         /*
0955          * Queue index #0 is used always for housekeeping, so don't
0956          * include in the affinity spreading.
0957          */
0958         struct irq_affinity desc = {
0959             .pre_vectors = 1,
0960         };
0961         rc = pci_alloc_irq_vectors_affinity(
0962                 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
0963                 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
0964     }
0965 
0966     allocated_irq_vectors = rc;
0967     if (rc < 0)
0968         return rc;
0969 
0970     /* Assigns the number of interrupts */
0971     pm8001_ha->number_of_intr = allocated_irq_vectors;
0972 
0973     /* Maximum queue number updating in HBA structure */
0974     pm8001_ha->max_q_num = allocated_irq_vectors;
0975 
0976     pm8001_dbg(pm8001_ha, INIT,
0977            "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
0978            rc, pm8001_ha->number_of_intr);
0979     return 0;
0980 }
0981 
0982 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
0983 {
0984     u32 i = 0, j = 0;
0985     int flag = 0, rc = 0;
0986     int nr_irqs = pm8001_ha->number_of_intr;
0987 
0988     if (pm8001_ha->chip_id != chip_8001)
0989         flag &= ~IRQF_SHARED;
0990 
0991     pm8001_dbg(pm8001_ha, INIT,
0992            "pci_enable_msix request number of intr %d\n",
0993            pm8001_ha->number_of_intr);
0994 
0995     if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
0996         nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
0997 
0998     for (i = 0; i < nr_irqs; i++) {
0999         snprintf(pm8001_ha->intr_drvname[i],
1000             sizeof(pm8001_ha->intr_drvname[0]),
1001             "%s-%d", pm8001_ha->name, i);
1002         pm8001_ha->irq_vector[i].irq_id = i;
1003         pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1004 
1005         rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1006             pm8001_interrupt_handler_msix, flag,
1007             pm8001_ha->intr_drvname[i],
1008             &(pm8001_ha->irq_vector[i]));
1009         if (rc) {
1010             for (j = 0; j < i; j++) {
1011                 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1012                     &(pm8001_ha->irq_vector[i]));
1013             }
1014             pci_free_irq_vectors(pm8001_ha->pdev);
1015             break;
1016         }
1017     }
1018 
1019     return rc;
1020 }
1021 #endif
1022 
1023 static u32 pm8001_setup_irq(struct pm8001_hba_info *pm8001_ha)
1024 {
1025     struct pci_dev *pdev;
1026 
1027     pdev = pm8001_ha->pdev;
1028 
1029 #ifdef PM8001_USE_MSIX
1030     if (pci_find_capability(pdev, PCI_CAP_ID_MSIX))
1031         return pm8001_setup_msix(pm8001_ha);
1032     pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1033 #endif
1034     return 0;
1035 }
1036 
1037 /**
1038  * pm8001_request_irq - register interrupt
1039  * @pm8001_ha: our ha struct.
1040  */
1041 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1042 {
1043     struct pci_dev *pdev;
1044     int rc;
1045 
1046     pdev = pm8001_ha->pdev;
1047 
1048 #ifdef PM8001_USE_MSIX
1049     if (pdev->msix_cap && pci_msi_enabled())
1050         return pm8001_request_msix(pm8001_ha);
1051     else {
1052         pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1053         goto intx;
1054     }
1055 #endif
1056 
1057 intx:
1058     /* initialize the INT-X interrupt */
1059     pm8001_ha->irq_vector[0].irq_id = 0;
1060     pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1061     rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
1062         pm8001_ha->name, SHOST_TO_SAS_HA(pm8001_ha->shost));
1063     return rc;
1064 }
1065 
1066 /**
1067  * pm8001_pci_probe - probe supported device
1068  * @pdev: pci device which kernel has been prepared for.
1069  * @ent: pci device id
1070  *
1071  * This function is the main initialization function, when register a new
1072  * pci driver it is invoked, all struct and hardware initialization should be
1073  * done here, also, register interrupt.
1074  */
1075 static int pm8001_pci_probe(struct pci_dev *pdev,
1076                 const struct pci_device_id *ent)
1077 {
1078     unsigned int rc;
1079     u32 pci_reg;
1080     u8  i = 0;
1081     struct pm8001_hba_info *pm8001_ha;
1082     struct Scsi_Host *shost = NULL;
1083     const struct pm8001_chip_info *chip;
1084     struct sas_ha_struct *sha;
1085 
1086     dev_printk(KERN_INFO, &pdev->dev,
1087         "pm80xx: driver version %s\n", DRV_VERSION);
1088     rc = pci_enable_device(pdev);
1089     if (rc)
1090         goto err_out_enable;
1091     pci_set_master(pdev);
1092     /*
1093      * Enable pci slot busmaster by setting pci command register.
1094      * This is required by FW for Cyclone card.
1095      */
1096 
1097     pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1098     pci_reg |= 0x157;
1099     pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1100     rc = pci_request_regions(pdev, DRV_NAME);
1101     if (rc)
1102         goto err_out_disable;
1103     rc = pci_go_44(pdev);
1104     if (rc)
1105         goto err_out_regions;
1106 
1107     shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1108     if (!shost) {
1109         rc = -ENOMEM;
1110         goto err_out_regions;
1111     }
1112     chip = &pm8001_chips[ent->driver_data];
1113     sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1114     if (!sha) {
1115         rc = -ENOMEM;
1116         goto err_out_free_host;
1117     }
1118     SHOST_TO_SAS_HA(shost) = sha;
1119 
1120     rc = pm8001_prep_sas_ha_init(shost, chip);
1121     if (rc) {
1122         rc = -ENOMEM;
1123         goto err_out_free;
1124     }
1125     pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1126     /* ent->driver variable is used to differentiate between controllers */
1127     pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1128     if (!pm8001_ha) {
1129         rc = -ENOMEM;
1130         goto err_out_free;
1131     }
1132 
1133     PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1134     rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1135     if (rc) {
1136         pm8001_dbg(pm8001_ha, FAIL,
1137                "chip_init failed [ret: %d]\n", rc);
1138         goto err_out_ha_free;
1139     }
1140 
1141     rc = pm8001_init_ccb_tag(pm8001_ha);
1142     if (rc)
1143         goto err_out_enable;
1144 
1145 
1146     PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1147 
1148     if (pm8001_ha->number_of_intr > 1) {
1149         shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1150         /*
1151          * For now, ensure we're not sent too many commands by setting
1152          * host_tagset. This is also required if we start using request
1153          * tag.
1154          */
1155         shost->host_tagset = 1;
1156     }
1157 
1158     rc = scsi_add_host(shost, &pdev->dev);
1159     if (rc)
1160         goto err_out_ha_free;
1161 
1162     PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1163     if (pm8001_ha->chip_id != chip_8001) {
1164         for (i = 1; i < pm8001_ha->number_of_intr; i++)
1165             PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1166         /* setup thermal configuration. */
1167         pm80xx_set_thermal_config(pm8001_ha);
1168     }
1169 
1170     pm8001_init_sas_add(pm8001_ha);
1171     /* phy setting support for motherboard controller */
1172     rc = pm8001_configure_phy_settings(pm8001_ha);
1173     if (rc)
1174         goto err_out_shost;
1175 
1176     pm8001_post_sas_ha_init(shost, chip);
1177     rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1178     if (rc) {
1179         pm8001_dbg(pm8001_ha, FAIL,
1180                "sas_register_ha failed [ret: %d]\n", rc);
1181         goto err_out_shost;
1182     }
1183     list_add_tail(&pm8001_ha->list, &hba_list);
1184     pm8001_ha->flags = PM8001F_RUN_TIME;
1185     scsi_scan_host(pm8001_ha->shost);
1186     return 0;
1187 
1188 err_out_shost:
1189     scsi_remove_host(pm8001_ha->shost);
1190 err_out_ha_free:
1191     pm8001_free(pm8001_ha);
1192 err_out_free:
1193     kfree(sha);
1194 err_out_free_host:
1195     scsi_host_put(shost);
1196 err_out_regions:
1197     pci_release_regions(pdev);
1198 err_out_disable:
1199     pci_disable_device(pdev);
1200 err_out_enable:
1201     return rc;
1202 }
1203 
1204 /**
1205  * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1206  * @pm8001_ha: our hba card information.
1207  */
1208 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1209 {
1210     struct Scsi_Host *shost = pm8001_ha->shost;
1211     struct device *dev = pm8001_ha->dev;
1212     u32 max_out_io, ccb_count;
1213     u32 can_queue;
1214     int i;
1215 
1216     max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1217     ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1218 
1219     /* Update to the scsi host*/
1220     can_queue = ccb_count - PM8001_RESERVE_SLOT;
1221     shost->can_queue = can_queue;
1222 
1223     pm8001_ha->tags = bitmap_zalloc(ccb_count, GFP_KERNEL);
1224     if (!pm8001_ha->tags)
1225         goto err_out;
1226 
1227     /* Memory region for ccb_info*/
1228     pm8001_ha->ccb_count = ccb_count;
1229     pm8001_ha->ccb_info =
1230         kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1231     if (!pm8001_ha->ccb_info) {
1232         pm8001_dbg(pm8001_ha, FAIL,
1233                "Unable to allocate memory for ccb\n");
1234         goto err_out_noccb;
1235     }
1236     for (i = 0; i < ccb_count; i++) {
1237         pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1238                 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1239                 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1240                 GFP_KERNEL);
1241         if (!pm8001_ha->ccb_info[i].buf_prd) {
1242             pm8001_dbg(pm8001_ha, FAIL,
1243                    "ccb prd memory allocation error\n");
1244             goto err_out;
1245         }
1246         pm8001_ha->ccb_info[i].task = NULL;
1247         pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1248         pm8001_ha->ccb_info[i].device = NULL;
1249         ++pm8001_ha->tags_num;
1250     }
1251 
1252     return 0;
1253 
1254 err_out_noccb:
1255     kfree(pm8001_ha->devices);
1256 err_out:
1257     return -ENOMEM;
1258 }
1259 
1260 static void pm8001_pci_remove(struct pci_dev *pdev)
1261 {
1262     struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1263     struct pm8001_hba_info *pm8001_ha;
1264     int i, j;
1265     pm8001_ha = sha->lldd_ha;
1266     sas_unregister_ha(sha);
1267     sas_remove_host(pm8001_ha->shost);
1268     list_del(&pm8001_ha->list);
1269     PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1270     PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1271 
1272 #ifdef PM8001_USE_MSIX
1273     for (i = 0; i < pm8001_ha->number_of_intr; i++)
1274         synchronize_irq(pci_irq_vector(pdev, i));
1275     for (i = 0; i < pm8001_ha->number_of_intr; i++)
1276         free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1277     pci_free_irq_vectors(pdev);
1278 #else
1279     free_irq(pm8001_ha->irq, sha);
1280 #endif
1281 #ifdef PM8001_USE_TASKLET
1282     /* For non-msix and msix interrupts */
1283     if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1284         (pm8001_ha->chip_id == chip_8001))
1285         tasklet_kill(&pm8001_ha->tasklet[0]);
1286     else
1287         for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1288             tasklet_kill(&pm8001_ha->tasklet[j]);
1289 #endif
1290     scsi_host_put(pm8001_ha->shost);
1291 
1292     for (i = 0; i < pm8001_ha->ccb_count; i++) {
1293         dma_free_coherent(&pm8001_ha->pdev->dev,
1294             sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1295             pm8001_ha->ccb_info[i].buf_prd,
1296             pm8001_ha->ccb_info[i].ccb_dma_handle);
1297     }
1298     kfree(pm8001_ha->ccb_info);
1299     kfree(pm8001_ha->devices);
1300 
1301     pm8001_free(pm8001_ha);
1302     kfree(sha->sas_phy);
1303     kfree(sha->sas_port);
1304     kfree(sha);
1305     pci_release_regions(pdev);
1306     pci_disable_device(pdev);
1307 }
1308 
1309 /**
1310  * pm8001_pci_suspend - power management suspend main entry point
1311  * @dev: Device struct
1312  *
1313  * Return: 0 on success, anything else on error.
1314  */
1315 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1316 {
1317     struct pci_dev *pdev = to_pci_dev(dev);
1318     struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1319     struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1320     int  i, j;
1321     sas_suspend_ha(sha);
1322     flush_workqueue(pm8001_wq);
1323     scsi_block_requests(pm8001_ha->shost);
1324     if (!pdev->pm_cap) {
1325         dev_err(dev, " PCI PM not supported\n");
1326         return -ENODEV;
1327     }
1328     PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1329     PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1330 #ifdef PM8001_USE_MSIX
1331     for (i = 0; i < pm8001_ha->number_of_intr; i++)
1332         synchronize_irq(pci_irq_vector(pdev, i));
1333     for (i = 0; i < pm8001_ha->number_of_intr; i++)
1334         free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1335     pci_free_irq_vectors(pdev);
1336 #else
1337     free_irq(pm8001_ha->irq, sha);
1338 #endif
1339 #ifdef PM8001_USE_TASKLET
1340     /* For non-msix and msix interrupts */
1341     if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1342         (pm8001_ha->chip_id == chip_8001))
1343         tasklet_kill(&pm8001_ha->tasklet[0]);
1344     else
1345         for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1346             tasklet_kill(&pm8001_ha->tasklet[j]);
1347 #endif
1348     pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1349               "suspended state\n", pdev,
1350               pm8001_ha->name);
1351     return 0;
1352 }
1353 
1354 /**
1355  * pm8001_pci_resume - power management resume main entry point
1356  * @dev: Device struct
1357  *
1358  * Return: 0 on success, anything else on error.
1359  */
1360 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1361 {
1362     struct pci_dev *pdev = to_pci_dev(dev);
1363     struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1364     struct pm8001_hba_info *pm8001_ha;
1365     int rc;
1366     u8 i = 0, j;
1367     DECLARE_COMPLETION_ONSTACK(completion);
1368 
1369     pm8001_ha = sha->lldd_ha;
1370 
1371     pm8001_info(pm8001_ha,
1372             "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1373             pdev, pm8001_ha->name, pdev->current_state);
1374 
1375     rc = pci_go_44(pdev);
1376     if (rc)
1377         goto err_out_disable;
1378     sas_prep_resume_ha(sha);
1379     /* chip soft rst only for spc */
1380     if (pm8001_ha->chip_id == chip_8001) {
1381         PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1382         pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1383     }
1384     rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1385     if (rc)
1386         goto err_out_disable;
1387 
1388     /* disable all the interrupt bits */
1389     PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1390 
1391     rc = pm8001_request_irq(pm8001_ha);
1392     if (rc)
1393         goto err_out_disable;
1394 #ifdef PM8001_USE_TASKLET
1395     /*  Tasklet for non msi-x interrupt handler */
1396     if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1397         (pm8001_ha->chip_id == chip_8001))
1398         tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1399             (unsigned long)&(pm8001_ha->irq_vector[0]));
1400     else
1401         for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1402             tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1403                 (unsigned long)&(pm8001_ha->irq_vector[j]));
1404 #endif
1405     PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1406     if (pm8001_ha->chip_id != chip_8001) {
1407         for (i = 1; i < pm8001_ha->number_of_intr; i++)
1408             PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1409     }
1410 
1411     /* Chip documentation for the 8070 and 8072 SPCv    */
1412     /* states that a 500ms minimum delay is required    */
1413     /* before issuing commands. Otherwise, the firmware */
1414     /* will enter an unrecoverable state.               */
1415 
1416     if (pm8001_ha->chip_id == chip_8070 ||
1417         pm8001_ha->chip_id == chip_8072) {
1418         mdelay(500);
1419     }
1420 
1421     /* Spin up the PHYs */
1422 
1423     pm8001_ha->flags = PM8001F_RUN_TIME;
1424     for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1425         pm8001_ha->phy[i].enable_completion = &completion;
1426         PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1427         wait_for_completion(&completion);
1428     }
1429     sas_resume_ha(sha);
1430     return 0;
1431 
1432 err_out_disable:
1433     scsi_remove_host(pm8001_ha->shost);
1434 
1435     return rc;
1436 }
1437 
1438 /* update of pci device, vendor id and driver data with
1439  * unique value for each of the controller
1440  */
1441 static struct pci_device_id pm8001_pci_table[] = {
1442     { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1443     { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1444     { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1445     { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1446     /* Support for SPC/SPCv/SPCve controllers */
1447     { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1448     { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1449     { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1450     { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1451     { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1452     { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1453     { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1454     { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1455     { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1456     { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1457     { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1458     { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1459     { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1460     { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1461     { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1462     { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1463         PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1464     { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1465         PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1466     { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1467         PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1468     { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1469         PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1470     { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1471         PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1472     { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1473         PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1474     { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1475         PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1476     { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1477         PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1478     { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1479         PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1480     { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1481         PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1482     { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1483         PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1484     { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1485         PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1486     { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1487         PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1488     { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1489         PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1490     { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1491         PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1492     { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1493         PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1494     { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1495         PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1496     { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1497         PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1498     { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1499         PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1500     { PCI_VENDOR_ID_ATTO, 0x8070,
1501         PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1502     { PCI_VENDOR_ID_ATTO, 0x8070,
1503         PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1504     { PCI_VENDOR_ID_ATTO, 0x8072,
1505         PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1506     { PCI_VENDOR_ID_ATTO, 0x8072,
1507         PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1508     { PCI_VENDOR_ID_ATTO, 0x8070,
1509         PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1510     { PCI_VENDOR_ID_ATTO, 0x8072,
1511         PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1512     { PCI_VENDOR_ID_ATTO, 0x8072,
1513         PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1514     {} /* terminate list */
1515 };
1516 
1517 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1518              pm8001_pci_suspend,
1519              pm8001_pci_resume);
1520 
1521 static struct pci_driver pm8001_pci_driver = {
1522     .name       = DRV_NAME,
1523     .id_table   = pm8001_pci_table,
1524     .probe      = pm8001_pci_probe,
1525     .remove     = pm8001_pci_remove,
1526     .driver.pm  = &pm8001_pci_pm_ops,
1527 };
1528 
1529 /**
1530  *  pm8001_init - initialize scsi transport template
1531  */
1532 static int __init pm8001_init(void)
1533 {
1534     int rc = -ENOMEM;
1535 
1536     pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1537     if (!pm8001_wq)
1538         goto err;
1539 
1540     pm8001_id = 0;
1541     pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1542     if (!pm8001_stt)
1543         goto err_wq;
1544     rc = pci_register_driver(&pm8001_pci_driver);
1545     if (rc)
1546         goto err_tp;
1547     return 0;
1548 
1549 err_tp:
1550     sas_release_transport(pm8001_stt);
1551 err_wq:
1552     destroy_workqueue(pm8001_wq);
1553 err:
1554     return rc;
1555 }
1556 
1557 static void __exit pm8001_exit(void)
1558 {
1559     pci_unregister_driver(&pm8001_pci_driver);
1560     sas_release_transport(pm8001_stt);
1561     destroy_workqueue(pm8001_wq);
1562 }
1563 
1564 module_init(pm8001_init);
1565 module_exit(pm8001_exit);
1566 
1567 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1568 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1569 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1570 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1571 MODULE_DESCRIPTION(
1572         "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1573         "SAS/SATA controller driver");
1574 MODULE_VERSION(DRV_VERSION);
1575 MODULE_LICENSE("GPL");
1576 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1577
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