scsi/pm8001/pm8001_hwi.h

0001 /*
0002  * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
0003  *
0004  * Copyright (c) 2008-2009 USI Co., Ltd.
0005  * All rights reserved.
0006  *
0007  * Redistribution and use in source and binary forms, with or without
0008  * modification, are permitted provided that the following conditions
0009  * are met:
0010  * 1. Redistributions of source code must retain the above copyright
0011  *    notice, this list of conditions, and the following disclaimer,
0012  *    without modification.
0013  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
0014  *    substantially similar to the "NO WARRANTY" disclaimer below
0015  *    ("Disclaimer") and any redistribution must be conditioned upon
0016  *    including a substantially similar Disclaimer requirement for further
0017  *    binary redistribution.
0018  * 3. Neither the names of the above-listed copyright holders nor the names
0019  *    of any contributors may be used to endorse or promote products derived
0020  *    from this software without specific prior written permission.
0021  *
0022  * Alternatively, this software may be distributed under the terms of the
0023  * GNU General Public License ("GPL") version 2 as published by the Free
0024  * Software Foundation.
0025  *
0026  * NO WARRANTY
0027  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0028  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0029  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
0030  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
0031  * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
0032  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
0033  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
0034  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
0035  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
0036  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
0037  * POSSIBILITY OF SUCH DAMAGES.
0038  *
0039  */
0040 #ifndef _PMC8001_REG_H_
0041 #define _PMC8001_REG_H_
0042
0043 #include <linux/types.h>
0044 #include <scsi/libsas.h>
0045
0046
0047 /* for Request Opcode of IOMB */
0048 #define OPC_INB_ECHO                1   /* 0x000 */
0049 #define OPC_INB_PHYSTART            4   /* 0x004 */
0050 #define OPC_INB_PHYSTOP             5   /* 0x005 */
0051 #define OPC_INB_SSPINIIOSTART           6   /* 0x006 */
0052 #define OPC_INB_SSPINITMSTART           7   /* 0x007 */
0053 #define OPC_INB_SSPINIEXTIOSTART        8   /* 0x008 */
0054 #define OPC_INB_DEV_HANDLE_ACCEPT       9   /* 0x009 */
0055 #define OPC_INB_SSPTGTIOSTART           10  /* 0x00A */
0056 #define OPC_INB_SSPTGTRSPSTART          11  /* 0x00B */
0057 #define OPC_INB_SSPINIEDCIOSTART        12  /* 0x00C */
0058 #define OPC_INB_SSPINIEXTEDCIOSTART     13  /* 0x00D */
0059 #define OPC_INB_SSPTGTEDCIOSTART        14  /* 0x00E */
0060 #define OPC_INB_SSP_ABORT           15  /* 0x00F */
0061 #define OPC_INB_DEREG_DEV_HANDLE        16  /* 0x010 */
0062 #define OPC_INB_GET_DEV_HANDLE          17  /* 0x011 */
0063 #define OPC_INB_SMP_REQUEST         18  /* 0x012 */
0064 /* SMP_RESPONSE is removed */
0065 #define OPC_INB_SMP_RESPONSE            19  /* 0x013 */
0066 #define OPC_INB_SMP_ABORT           20  /* 0x014 */
0067 #define OPC_INB_REG_DEV             22  /* 0x016 */
0068 #define OPC_INB_SATA_HOST_OPSTART       23  /* 0x017 */
0069 #define OPC_INB_SATA_ABORT          24  /* 0x018 */
0070 #define OPC_INB_LOCAL_PHY_CONTROL       25  /* 0x019 */
0071 #define OPC_INB_GET_DEV_INFO            26  /* 0x01A */
0072 #define OPC_INB_FW_FLASH_UPDATE         32  /* 0x020 */
0073 #define OPC_INB_GPIO                34  /* 0x022 */
0074 #define OPC_INB_SAS_DIAG_MODE_START_END     35  /* 0x023 */
0075 #define OPC_INB_SAS_DIAG_EXECUTE        36  /* 0x024 */
0076 #define OPC_INB_SAS_HW_EVENT_ACK        37  /* 0x025 */
0077 #define OPC_INB_GET_TIME_STAMP          38  /* 0x026 */
0078 #define OPC_INB_PORT_CONTROL            39  /* 0x027 */
0079 #define OPC_INB_GET_NVMD_DATA           40  /* 0x028 */
0080 #define OPC_INB_SET_NVMD_DATA           41  /* 0x029 */
0081 #define OPC_INB_SET_DEVICE_STATE        42  /* 0x02A */
0082 #define OPC_INB_GET_DEVICE_STATE        43  /* 0x02B */
0083 #define OPC_INB_SET_DEV_INFO            44  /* 0x02C */
0084 #define OPC_INB_SAS_RE_INITIALIZE       45  /* 0x02D */
0085
0086 /* for Response Opcode of IOMB */
0087 #define OPC_OUB_ECHO                1   /* 0x001 */
0088 #define OPC_OUB_HW_EVENT            4   /* 0x004 */
0089 #define OPC_OUB_SSP_COMP            5   /* 0x005 */
0090 #define OPC_OUB_SMP_COMP            6   /* 0x006 */
0091 #define OPC_OUB_LOCAL_PHY_CNTRL         7   /* 0x007 */
0092 #define OPC_OUB_DEV_REGIST          10  /* 0x00A */
0093 #define OPC_OUB_DEREG_DEV           11  /* 0x00B */
0094 #define OPC_OUB_GET_DEV_HANDLE          12  /* 0x00C */
0095 #define OPC_OUB_SATA_COMP           13  /* 0x00D */
0096 #define OPC_OUB_SATA_EVENT          14  /* 0x00E */
0097 #define OPC_OUB_SSP_EVENT           15  /* 0x00F */
0098 #define OPC_OUB_DEV_HANDLE_ARRIV        16  /* 0x010 */
0099 /* SMP_RECEIVED Notification is removed */
0100 #define OPC_OUB_SMP_RECV_EVENT          17  /* 0x011 */
0101 #define OPC_OUB_SSP_RECV_EVENT          18  /* 0x012 */
0102 #define OPC_OUB_DEV_INFO            19  /* 0x013 */
0103 #define OPC_OUB_FW_FLASH_UPDATE         20  /* 0x014 */
0104 #define OPC_OUB_GPIO_RESPONSE           22  /* 0x016 */
0105 #define OPC_OUB_GPIO_EVENT          23  /* 0x017 */
0106 #define OPC_OUB_GENERAL_EVENT           24  /* 0x018 */
0107 #define OPC_OUB_SSP_ABORT_RSP           26  /* 0x01A */
0108 #define OPC_OUB_SATA_ABORT_RSP          27  /* 0x01B */
0109 #define OPC_OUB_SAS_DIAG_MODE_START_END     28  /* 0x01C */
0110 #define OPC_OUB_SAS_DIAG_EXECUTE        29  /* 0x01D */
0111 #define OPC_OUB_GET_TIME_STAMP          30  /* 0x01E */
0112 #define OPC_OUB_SAS_HW_EVENT_ACK        31  /* 0x01F */
0113 #define OPC_OUB_PORT_CONTROL            32  /* 0x020 */
0114 #define OPC_OUB_SKIP_ENTRY          33  /* 0x021 */
0115 #define OPC_OUB_SMP_ABORT_RSP           34  /* 0x022 */
0116 #define OPC_OUB_GET_NVMD_DATA           35  /* 0x023 */
0117 #define OPC_OUB_SET_NVMD_DATA           36  /* 0x024 */
0118 #define OPC_OUB_DEVICE_HANDLE_REMOVAL       37  /* 0x025 */
0119 #define OPC_OUB_SET_DEVICE_STATE        38  /* 0x026 */
0120 #define OPC_OUB_GET_DEVICE_STATE        39  /* 0x027 */
0121 #define OPC_OUB_SET_DEV_INFO            40  /* 0x028 */
0122 #define OPC_OUB_SAS_RE_INITIALIZE       41  /* 0x029 */
0123
0124 /* for phy start*/
0125 #define SPINHOLD_DISABLE        (0x00 << 14)
0126 #define SPINHOLD_ENABLE         (0x01 << 14)
0127 #define LINKMODE_SAS            (0x01 << 12)
0128 #define LINKMODE_DSATA          (0x02 << 12)
0129 #define LINKMODE_AUTO           (0x03 << 12)
0130 #define LINKRATE_15         (0x01 << 8)
0131 #define LINKRATE_30         (0x02 << 8)
0132 #define LINKRATE_60         (0x04 << 8)
0133
0134 /* for new SPC controllers MEMBASE III is shared between BIOS and DATA */
0135 #define GSM_SM_BASE         0x4F0000
0136 struct mpi_msg_hdr{
0137     __le32  header; /* Bits [11:0]  - Message operation code */
0138     /* Bits [15:12] - Message Category */
0139     /* Bits [21:16] - Outboundqueue ID for the
0140     operation completion message */
0141     /* Bits [23:22] - Reserved */
0142     /* Bits [28:24] - Buffer Count, indicates how
0143     many buffer are allocated for the massage */
0144     /* Bits [30:29] - Reserved */
0145     /* Bits [31] - Message Valid bit */
0146 } __attribute__((packed, aligned(4)));
0147
0148
0149 /*
0150  * brief the data structure of PHY Start Command
0151  * use to describe enable the phy (64 bytes)
0152  */
0153 struct phy_start_req {
0154     __le32  tag;
0155     __le32  ase_sh_lm_slr_phyid;
0156     struct sas_identify_frame sas_identify;
0157     u32 reserved[5];
0158 } __attribute__((packed, aligned(4)));
0159
0160
0161 /*
0162  * brief the data structure of PHY Start Command
0163  * use to disable the phy (64 bytes)
0164  */
0165 struct phy_stop_req {
0166     __le32  tag;
0167     __le32  phy_id;
0168     u32 reserved[13];
0169 } __attribute__((packed, aligned(4)));
0170
0171
0172 /* set device bits fis - device to host */
0173 struct  set_dev_bits_fis {
0174     u8  fis_type;   /* 0xA1*/
0175     u8  n_i_pmport;
0176     /* b7 : n Bit. Notification bit. If set device needs attention. */
0177     /* b6 : i Bit. Interrupt Bit */
0178     /* b5-b4: reserved2 */
0179     /* b3-b0: PM Port */
0180     u8  status;
0181     u8  error;
0182     u32 _r_a;
0183 } __attribute__ ((packed));
0184 /* PIO setup FIS - device to host */
0185 struct  pio_setup_fis {
0186     u8  fis_type;   /* 0x5f */
0187     u8  i_d_pmPort;
0188     /* b7 : reserved */
0189     /* b6 : i bit. Interrupt bit */
0190     /* b5 : d bit. data transfer direction. set to 1 for device to host
0191     xfer */
0192     /* b4 : reserved */
0193     /* b3-b0: PM Port */
0194     u8  status;
0195     u8  error;
0196     u8  lbal;
0197     u8  lbam;
0198     u8  lbah;
0199     u8  device;
0200     u8  lbal_exp;
0201     u8  lbam_exp;
0202     u8  lbah_exp;
0203     u8  _r_a;
0204     u8  sector_count;
0205     u8  sector_count_exp;
0206     u8  _r_b;
0207     u8  e_status;
0208     u8  _r_c[2];
0209     u8  transfer_count;
0210 } __attribute__ ((packed));
0211
0212 /*
0213  * brief the data structure of SATA Completion Response
0214  * use to describe the sata task response (64 bytes)
0215  */
0216 struct sata_completion_resp {
0217     __le32  tag;
0218     __le32  status;
0219     __le32  param;
0220     u32 sata_resp[12];
0221 } __attribute__((packed, aligned(4)));
0222
0223
0224 /*
0225  * brief the data structure of SAS HW Event Notification
0226  * use to alert the host about the hardware event(64 bytes)
0227  */
0228 struct hw_event_resp {
0229     __le32  lr_evt_status_phyid_portid;
0230     __le32  evt_param;
0231     __le32  npip_portstate;
0232     struct sas_identify_frame   sas_identify;
0233     struct dev_to_host_fis  sata_fis;
0234 } __attribute__((packed, aligned(4)));
0235
0236
0237 /*
0238  * brief the data structure of  REGISTER DEVICE Command
0239  * use to describe MPI REGISTER DEVICE Command (64 bytes)
0240  */
0241
0242 struct reg_dev_req {
0243     __le32  tag;
0244     __le32  phyid_portid;
0245     __le32  dtype_dlr_retry;
0246     __le32  firstburstsize_ITNexustimeout;
0247     u8  sas_addr[SAS_ADDR_SIZE];
0248     __le32  upper_device_id;
0249     u32 reserved[8];
0250 } __attribute__((packed, aligned(4)));
0251
0252
0253 /*
0254  * brief the data structure of  DEREGISTER DEVICE Command
0255  * use to request spc to remove all internal resources associated
0256  * with the device id (64 bytes)
0257  */
0258
0259 struct dereg_dev_req {
0260     __le32  tag;
0261     __le32  device_id;
0262     u32 reserved[13];
0263 } __attribute__((packed, aligned(4)));
0264
0265
0266 /*
0267  * brief the data structure of DEVICE_REGISTRATION Response
0268  * use to notify the completion of the device registration  (64 bytes)
0269  */
0270
0271 struct dev_reg_resp {
0272     __le32  tag;
0273     __le32  status;
0274     __le32  device_id;
0275     u32 reserved[12];
0276 } __attribute__((packed, aligned(4)));
0277
0278
0279 /*
0280  * brief the data structure of Local PHY Control Command
0281  * use to issue PHY CONTROL to local phy (64 bytes)
0282  */
0283 struct local_phy_ctl_req {
0284     __le32  tag;
0285     __le32  phyop_phyid;
0286     u32 reserved1[13];
0287 } __attribute__((packed, aligned(4)));
0288
0289
0290 /**
0291  * brief the data structure of Local Phy Control Response
0292  * use to describe MPI Local Phy Control Response (64 bytes)
0293  */
0294 struct local_phy_ctl_resp {
0295     __le32  tag;
0296     __le32  phyop_phyid;
0297     __le32  status;
0298     u32 reserved[12];
0299 } __attribute__((packed, aligned(4)));
0300
0301
0302 #define OP_BITS 0x0000FF00
0303 #define ID_BITS 0x000000FF
0304
0305 /*
0306  * brief the data structure of PORT Control Command
0307  * use to control port properties (64 bytes)
0308  */
0309
0310 struct port_ctl_req {
0311     __le32  tag;
0312     __le32  portop_portid;
0313     __le32  param0;
0314     __le32  param1;
0315     u32 reserved1[11];
0316 } __attribute__((packed, aligned(4)));
0317
0318
0319 /*
0320  * brief the data structure of HW Event Ack Command
0321  * use to acknowledge receive HW event (64 bytes)
0322  */
0323
0324 struct hw_event_ack_req {
0325     __le32  tag;
0326     __le32  sea_phyid_portid;
0327     __le32  param0;
0328     __le32  param1;
0329     u32 reserved1[11];
0330 } __attribute__((packed, aligned(4)));
0331
0332
0333 /*
0334  * brief the data structure of SSP Completion Response
0335  * use to indicate a SSP Completion  (n bytes)
0336  */
0337 struct ssp_completion_resp {
0338     __le32  tag;
0339     __le32  status;
0340     __le32  param;
0341     __le32  ssptag_rescv_rescpad;
0342     struct ssp_response_iu  ssp_resp_iu;
0343     __le32  residual_count;
0344 } __attribute__((packed, aligned(4)));
0345
0346
0347 #define SSP_RESCV_BIT   0x00010000
0348
0349 /*
0350  * brief the data structure of SATA EVNET esponse
0351  * use to indicate a SATA Completion  (64 bytes)
0352  */
0353
0354 struct sata_event_resp {
0355     __le32  tag;
0356     __le32  event;
0357     __le32  port_id;
0358     __le32  device_id;
0359     u32 reserved[11];
0360 } __attribute__((packed, aligned(4)));
0361
0362 /*
0363  * brief the data structure of SSP EVNET esponse
0364  * use to indicate a SSP Completion  (64 bytes)
0365  */
0366
0367 struct ssp_event_resp {
0368     __le32  tag;
0369     __le32  event;
0370     __le32  port_id;
0371     __le32  device_id;
0372     u32 reserved[11];
0373 } __attribute__((packed, aligned(4)));
0374
0375 /**
0376  * brief the data structure of General Event Notification Response
0377  * use to describe MPI General Event Notification Response (64 bytes)
0378  */
0379 struct general_event_resp {
0380     __le32  status;
0381     __le32  inb_IOMB_payload[14];
0382 } __attribute__((packed, aligned(4)));
0383
0384
0385 #define GENERAL_EVENT_PAYLOAD   14
0386 #define OPCODE_BITS 0x00000fff
0387
0388 /*
0389  * brief the data structure of SMP Request Command
0390  * use to describe MPI SMP REQUEST Command (64 bytes)
0391  */
0392 struct smp_req {
0393     __le32  tag;
0394     __le32  device_id;
0395     __le32  len_ip_ir;
0396     /* Bits [0]  - Indirect response */
0397     /* Bits [1] - Indirect Payload */
0398     /* Bits [15:2] - Reserved */
0399     /* Bits [23:16] - direct payload Len */
0400     /* Bits [31:24] - Reserved */
0401     u8  smp_req16[16];
0402     union {
0403         u8  smp_req[32];
0404         struct {
0405             __le64 long_req_addr;/* sg dma address, LE */
0406             __le32 long_req_size;/* LE */
0407             u32 _r_a;
0408             __le64 long_resp_addr;/* sg dma address, LE */
0409             __le32 long_resp_size;/* LE */
0410             u32 _r_b;
0411             } long_smp_req;/* sequencer extension */
0412     };
0413 } __attribute__((packed, aligned(4)));
0414 /*
0415  * brief the data structure of SMP Completion Response
0416  * use to describe MPI SMP Completion Response (64 bytes)
0417  */
0418 struct smp_completion_resp {
0419     __le32  tag;
0420     __le32  status;
0421     __le32  param;
0422     __le32  _r_a[12];
0423 } __attribute__((packed, aligned(4)));
0424
0425 /*
0426  *brief the data structure of SSP SMP SATA Abort Command
0427  * use to describe MPI SSP SMP & SATA Abort Command (64 bytes)
0428  */
0429 struct task_abort_req {
0430     __le32  tag;
0431     __le32  device_id;
0432     __le32  tag_to_abort;
0433     __le32  abort_all;
0434     u32 reserved[11];
0435 } __attribute__((packed, aligned(4)));
0436
0437 /**
0438  * brief the data structure of SSP SATA SMP Abort Response
0439  * use to describe SSP SMP & SATA Abort Response ( 64 bytes)
0440  */
0441 struct task_abort_resp {
0442     __le32  tag;
0443     __le32  status;
0444     __le32  scp;
0445     u32 reserved[12];
0446 } __attribute__((packed, aligned(4)));
0447
0448
0449 /**
0450  * brief the data structure of SAS Diagnostic Start/End Command
0451  * use to describe MPI SAS Diagnostic Start/End Command (64 bytes)
0452  */
0453 struct sas_diag_start_end_req {
0454     __le32  tag;
0455     __le32  operation_phyid;
0456     u32 reserved[13];
0457 } __attribute__((packed, aligned(4)));
0458
0459
0460 /**
0461  * brief the data structure of SAS Diagnostic Execute Command
0462  * use to describe MPI SAS Diagnostic Execute Command (64 bytes)
0463  */
0464 struct sas_diag_execute_req{
0465     __le32  tag;
0466     __le32  cmdtype_cmddesc_phyid;
0467     __le32  pat1_pat2;
0468     __le32  threshold;
0469     __le32  codepat_errmsk;
0470     __le32  pmon;
0471     __le32  pERF1CTL;
0472     u32 reserved[8];
0473 } __attribute__((packed, aligned(4)));
0474
0475
0476 #define SAS_DIAG_PARAM_BYTES 24
0477
0478 /*
0479  * brief the data structure of Set Device State Command
0480  * use to describe MPI Set Device State Command (64 bytes)
0481  */
0482 struct set_dev_state_req {
0483     __le32  tag;
0484     __le32  device_id;
0485     __le32  nds;
0486     u32 reserved[12];
0487 } __attribute__((packed, aligned(4)));
0488
0489 /*
0490  * brief the data structure of sas_re_initialization
0491  */
0492 struct sas_re_initialization_req {
0493
0494     __le32  tag;
0495     __le32  SSAHOLT;/* bit29-set max port;
0496             ** bit28-set open reject cmd retries.
0497             ** bit27-set open reject data retries.
0498             ** bit26-set open reject option, remap:1 or not:0.
0499             ** bit25-set sata head of line time out.
0500             */
0501     __le32 reserved_maxPorts;
0502     __le32 open_reject_cmdretries_data_retries;/* cmd retries: 31-bit16;
0503                             * data retries: bit15-bit0.
0504                             */
0505     __le32  sata_hol_tmo;
0506     u32 reserved1[10];
0507 } __attribute__((packed, aligned(4)));
0508
0509 /*
0510  * brief the data structure of SATA Start Command
0511  * use to describe MPI SATA IO Start Command (64 bytes)
0512  */
0513
0514 struct sata_start_req {
0515     __le32  tag;
0516     __le32  device_id;
0517     __le32  data_len;
0518     __le32  ncqtag_atap_dir_m;
0519     struct host_to_dev_fis  sata_fis;
0520     u32 reserved1;
0521     u32 reserved2;
0522     u32 addr_low;
0523     u32 addr_high;
0524     __le32  len;
0525     __le32  esgl;
0526 } __attribute__((packed, aligned(4)));
0527
0528 /**
0529  * brief the data structure of SSP INI TM Start Command
0530  * use to describe MPI SSP INI TM Start Command (64 bytes)
0531  */
0532 struct ssp_ini_tm_start_req {
0533     __le32  tag;
0534     __le32  device_id;
0535     __le32  relate_tag;
0536     __le32  tmf;
0537     u8  lun[8];
0538     __le32  ds_ads_m;
0539     u32 reserved[8];
0540 } __attribute__((packed, aligned(4)));
0541
0542
0543 struct ssp_info_unit {
0544     u8  lun[8];/* SCSI Logical Unit Number */
0545     u8  reserved1;/* reserved */
0546     u8  efb_prio_attr;
0547     /* B7   : enabledFirstBurst */
0548     /* B6-3 : taskPriority */
0549     /* B2-0 : taskAttribute */
0550     u8  reserved2;  /* reserved */
0551     u8  additional_cdb_len;
0552     /* B7-2 : additional_cdb_len */
0553     /* B1-0 : reserved */
0554     u8  cdb[16];/* The SCSI CDB up to 16 bytes length */
0555 } __attribute__((packed, aligned(4)));
0556
0557
0558 /**
0559  * brief the data structure of SSP INI IO Start Command
0560  * use to describe MPI SSP INI IO Start Command (64 bytes)
0561  */
0562 struct ssp_ini_io_start_req {
0563     __le32  tag;
0564     __le32  device_id;
0565     __le32  data_len;
0566     __le32  dir_m_tlr;
0567     struct ssp_info_unit    ssp_iu;
0568     __le32  addr_low;
0569     __le32  addr_high;
0570     __le32  len;
0571     __le32  esgl;
0572 } __attribute__((packed, aligned(4)));
0573
0574
0575 /**
0576  * brief the data structure of Firmware download
0577  * use to describe MPI FW DOWNLOAD Command (64 bytes)
0578  */
0579 struct fw_flash_Update_req {
0580     __le32  tag;
0581     __le32  cur_image_offset;
0582     __le32  cur_image_len;
0583     __le32  total_image_len;
0584     u32 reserved0[7];
0585     __le32  sgl_addr_lo;
0586     __le32  sgl_addr_hi;
0587     __le32  len;
0588     __le32  ext_reserved;
0589 } __attribute__((packed, aligned(4)));
0590
0591
0592 #define FWFLASH_IOMB_RESERVED_LEN 0x07
0593 /**
0594  * brief the data structure of FW_FLASH_UPDATE Response
0595  * use to describe MPI FW_FLASH_UPDATE Response (64 bytes)
0596  *
0597  */
0598 struct fw_flash_Update_resp {
0599     __le32  tag;
0600     __le32  status;
0601     u32 reserved[13];
0602 } __attribute__((packed, aligned(4)));
0603
0604
0605 /**
0606  * brief the data structure of Get NVM Data Command
0607  * use to get data from NVM in HBA(64 bytes)
0608  */
0609 struct get_nvm_data_req {
0610     __le32  tag;
0611     __le32  len_ir_vpdd;
0612     __le32  vpd_offset;
0613     u32 reserved[8];
0614     __le32  resp_addr_lo;
0615     __le32  resp_addr_hi;
0616     __le32  resp_len;
0617     u32 reserved1;
0618 } __attribute__((packed, aligned(4)));
0619
0620
0621 struct set_nvm_data_req {
0622     __le32  tag;
0623     __le32  len_ir_vpdd;
0624     __le32  vpd_offset;
0625     __le32  reserved[8];
0626     __le32  resp_addr_lo;
0627     __le32  resp_addr_hi;
0628     __le32  resp_len;
0629     u32 reserved1;
0630 } __attribute__((packed, aligned(4)));
0631
0632
0633 #define TWI_DEVICE  0x0
0634 #define C_SEEPROM   0x1
0635 #define VPD_FLASH   0x4
0636 #define AAP1_RDUMP  0x5
0637 #define IOP_RDUMP   0x6
0638 #define EXPAN_ROM   0x7
0639
0640 #define IPMode      0x80000000
0641 #define NVMD_TYPE   0x0000000F
0642 #define NVMD_STAT   0x0000FFFF
0643 #define NVMD_LEN    0xFF000000
0644 /**
0645  * brief the data structure of Get NVMD Data Response
0646  * use to describe MPI Get NVMD Data Response (64 bytes)
0647  */
0648 struct get_nvm_data_resp {
0649     __le32      tag;
0650     __le32      ir_tda_bn_dps_das_nvm;
0651     __le32      dlen_status;
0652     __le32      nvm_data[12];
0653 } __attribute__((packed, aligned(4)));
0654
0655
0656 /**
0657  * brief the data structure of SAS Diagnostic Start/End Response
0658  * use to describe MPI SAS Diagnostic Start/End Response (64 bytes)
0659  *
0660  */
0661 struct sas_diag_start_end_resp {
0662     __le32      tag;
0663     __le32      status;
0664     u32     reserved[13];
0665 } __attribute__((packed, aligned(4)));
0666
0667
0668 /**
0669  * brief the data structure of SAS Diagnostic Execute Response
0670  * use to describe MPI SAS Diagnostic Execute Response (64 bytes)
0671  *
0672  */
0673 struct sas_diag_execute_resp {
0674     __le32      tag;
0675     __le32      cmdtype_cmddesc_phyid;
0676     __le32      Status;
0677     __le32      ReportData;
0678     u32     reserved[11];
0679 } __attribute__((packed, aligned(4)));
0680
0681
0682 /**
0683  * brief the data structure of Set Device State Response
0684  * use to describe MPI Set Device State Response (64 bytes)
0685  *
0686  */
0687 struct set_dev_state_resp {
0688     __le32      tag;
0689     __le32      status;
0690     __le32      device_id;
0691     __le32      pds_nds;
0692     u32     reserved[11];
0693 } __attribute__((packed, aligned(4)));
0694
0695
0696 #define NDS_BITS 0x0F
0697 #define PDS_BITS 0xF0
0698
0699 /*
0700  * HW Events type
0701  */
0702
0703 #define HW_EVENT_RESET_START            0x01
0704 #define HW_EVENT_CHIP_RESET_COMPLETE        0x02
0705 #define HW_EVENT_PHY_STOP_STATUS        0x03
0706 #define HW_EVENT_SAS_PHY_UP         0x04
0707 #define HW_EVENT_SATA_PHY_UP            0x05
0708 #define HW_EVENT_SATA_SPINUP_HOLD       0x06
0709 #define HW_EVENT_PHY_DOWN           0x07
0710 #define HW_EVENT_PORT_INVALID           0x08
0711 #define HW_EVENT_BROADCAST_CHANGE       0x09
0712 #define HW_EVENT_PHY_ERROR          0x0A
0713 #define HW_EVENT_BROADCAST_SES          0x0B
0714 #define HW_EVENT_INBOUND_CRC_ERROR      0x0C
0715 #define HW_EVENT_HARD_RESET_RECEIVED        0x0D
0716 #define HW_EVENT_MALFUNCTION            0x0E
0717 #define HW_EVENT_ID_FRAME_TIMEOUT       0x0F
0718 #define HW_EVENT_BROADCAST_EXP          0x10
0719 #define HW_EVENT_PHY_START_STATUS       0x11
0720 #define HW_EVENT_LINK_ERR_INVALID_DWORD     0x12
0721 #define HW_EVENT_LINK_ERR_DISPARITY_ERROR   0x13
0722 #define HW_EVENT_LINK_ERR_CODE_VIOLATION    0x14
0723 #define HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH   0x15
0724 #define HW_EVENT_LINK_ERR_PHY_RESET_FAILED  0x16
0725 #define HW_EVENT_PORT_RECOVERY_TIMER_TMO    0x17
0726 #define HW_EVENT_PORT_RECOVER           0x18
0727 #define HW_EVENT_PORT_RESET_TIMER_TMO       0x19
0728 #define HW_EVENT_PORT_RESET_COMPLETE        0x20
0729 #define EVENT_BROADCAST_ASYNCH_EVENT        0x21
0730
0731 /* port state */
0732 #define PORT_NOT_ESTABLISHED            0x00
0733 #define PORT_VALID              0x01
0734 #define PORT_LOSTCOMM               0x02
0735 #define PORT_IN_RESET               0x04
0736 #define PORT_INVALID                0x08
0737
0738 /*
0739  * SSP/SMP/SATA IO Completion Status values
0740  */
0741
0742 #define IO_SUCCESS              0x00
0743 #define IO_ABORTED              0x01
0744 #define IO_OVERFLOW             0x02
0745 #define IO_UNDERFLOW                0x03
0746 #define IO_FAILED               0x04
0747 #define IO_ABORT_RESET              0x05
0748 #define IO_NOT_VALID                0x06
0749 #define IO_NO_DEVICE                0x07
0750 #define IO_ILLEGAL_PARAMETER            0x08
0751 #define IO_LINK_FAILURE             0x09
0752 #define IO_PROG_ERROR               0x0A
0753 #define IO_EDC_IN_ERROR             0x0B
0754 #define IO_EDC_OUT_ERROR            0x0C
0755 #define IO_ERROR_HW_TIMEOUT         0x0D
0756 #define IO_XFER_ERROR_BREAK         0x0E
0757 #define IO_XFER_ERROR_PHY_NOT_READY     0x0F
0758 #define IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED    0x10
0759 #define IO_OPEN_CNX_ERROR_ZONE_VIOLATION        0x11
0760 #define IO_OPEN_CNX_ERROR_BREAK             0x12
0761 #define IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS         0x13
0762 #define IO_OPEN_CNX_ERROR_BAD_DESTINATION       0x14
0763 #define IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED 0x15
0764 #define IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY        0x16
0765 #define IO_OPEN_CNX_ERROR_WRONG_DESTINATION     0x17
0766 #define IO_OPEN_CNX_ERROR_UNKNOWN_ERROR         0x18
0767 #define IO_XFER_ERROR_NAK_RECEIVED          0x19
0768 #define IO_XFER_ERROR_ACK_NAK_TIMEOUT           0x1A
0769 #define IO_XFER_ERROR_PEER_ABORTED          0x1B
0770 #define IO_XFER_ERROR_RX_FRAME              0x1C
0771 #define IO_XFER_ERROR_DMA               0x1D
0772 #define IO_XFER_ERROR_CREDIT_TIMEOUT            0x1E
0773 #define IO_XFER_ERROR_SATA_LINK_TIMEOUT         0x1F
0774 #define IO_XFER_ERROR_SATA              0x20
0775 #define IO_XFER_ERROR_ABORTED_DUE_TO_SRST       0x22
0776 #define IO_XFER_ERROR_REJECTED_NCQ_MODE         0x21
0777 #define IO_XFER_ERROR_ABORTED_NCQ_MODE          0x23
0778 #define IO_XFER_OPEN_RETRY_TIMEOUT          0x24
0779 #define IO_XFER_SMP_RESP_CONNECTION_ERROR       0x25
0780 #define IO_XFER_ERROR_UNEXPECTED_PHASE          0x26
0781 #define IO_XFER_ERROR_XFER_RDY_OVERRUN          0x27
0782 #define IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED     0x28
0783
0784 #define IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT     0x30
0785 #define IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK    0x31
0786 #define IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK 0x32
0787
0788 #define IO_XFER_ERROR_OFFSET_MISMATCH           0x34
0789 #define IO_XFER_ERROR_XFER_ZERO_DATA_LEN        0x35
0790 #define IO_XFER_CMD_FRAME_ISSUED            0x36
0791 #define IO_ERROR_INTERNAL_SMP_RESOURCE          0x37
0792 #define IO_PORT_IN_RESET                0x38
0793 #define IO_DS_NON_OPERATIONAL               0x39
0794 #define IO_DS_IN_RECOVERY               0x3A
0795 #define IO_TM_TAG_NOT_FOUND             0x3B
0796 #define IO_XFER_PIO_SETUP_ERROR             0x3C
0797 #define IO_SSP_EXT_IU_ZERO_LEN_ERROR            0x3D
0798 #define IO_DS_IN_ERROR                  0x3E
0799 #define IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY      0x3F
0800 #define IO_ABORT_IN_PROGRESS                0x40
0801 #define IO_ABORT_DELAYED                0x41
0802 #define IO_INVALID_LENGTH               0x42
0803 #define IO_FATAL_ERROR                  0x51
0804
0805 /* WARNING: This error code must always be the last number.
0806  * If you add error code, modify this code also
0807  * It is used as an index
0808  */
0809 #define IO_ERROR_UNKNOWN_GENERIC            0x43
0810
0811 /* MSGU CONFIGURATION  TABLE*/
0812
0813 #define SPC_MSGU_CFG_TABLE_UPDATE       0x01/* Inbound doorbell bit0 */
0814 #define SPC_MSGU_CFG_TABLE_RESET        0x02/* Inbound doorbell bit1 */
0815 #define SPC_MSGU_CFG_TABLE_FREEZE       0x04/* Inbound doorbell bit2 */
0816 #define SPC_MSGU_CFG_TABLE_UNFREEZE     0x08/* Inbound doorbell bit4 */
0817 #define MSGU_IBDB_SET               0x04
0818 #define MSGU_HOST_INT_STATUS            0x08
0819 #define MSGU_HOST_INT_MASK          0x0C
0820 #define MSGU_IOPIB_INT_STATUS           0x18
0821 #define MSGU_IOPIB_INT_MASK         0x1C
0822 #define MSGU_IBDB_CLEAR             0x20/* RevB - Host not use */
0823 #define MSGU_MSGU_CONTROL           0x24
0824 #define MSGU_ODR                0x3C/* RevB */
0825 #define MSGU_ODCR               0x40/* RevB */
0826 #define MSGU_SCRATCH_PAD_0          0x44
0827 #define MSGU_SCRATCH_PAD_1          0x48
0828 #define MSGU_SCRATCH_PAD_2          0x4C
0829 #define MSGU_SCRATCH_PAD_3          0x50
0830 #define MSGU_HOST_SCRATCH_PAD_0         0x54
0831 #define MSGU_HOST_SCRATCH_PAD_1         0x58
0832 #define MSGU_HOST_SCRATCH_PAD_2         0x5C
0833 #define MSGU_HOST_SCRATCH_PAD_3         0x60
0834 #define MSGU_HOST_SCRATCH_PAD_4         0x64
0835 #define MSGU_HOST_SCRATCH_PAD_5         0x68
0836 #define MSGU_HOST_SCRATCH_PAD_6         0x6C
0837 #define MSGU_HOST_SCRATCH_PAD_7         0x70
0838 #define MSGU_ODMR               0x74/* RevB */
0839
0840 /* bit definition for ODMR register */
0841 #define ODMR_MASK_ALL               0xFFFFFFFF/* mask all
0842                     interrupt vector */
0843 #define ODMR_CLEAR_ALL              0/* clear all
0844                     interrupt vector */
0845 /* bit definition for ODCR register */
0846 #define ODCR_CLEAR_ALL      0xFFFFFFFF   /* mask all
0847                     interrupt vector*/
0848 /* MSIX Interupts */
0849 #define MSIX_TABLE_OFFSET       0x2000
0850 #define MSIX_TABLE_ELEMENT_SIZE     0x10
0851 #define MSIX_INTERRUPT_CONTROL_OFFSET   0xC
0852 #define MSIX_TABLE_BASE   (MSIX_TABLE_OFFSET + MSIX_INTERRUPT_CONTROL_OFFSET)
0853 #define MSIX_INTERRUPT_DISABLE      0x1
0854 #define MSIX_INTERRUPT_ENABLE       0x0
0855
0856
0857 /* state definition for Scratch Pad1 register */
0858 #define SCRATCH_PAD1_POR        0x00  /* power on reset state */
0859 #define SCRATCH_PAD1_SFR        0x01  /* soft reset state */
0860 #define SCRATCH_PAD1_ERR        0x02  /* error state */
0861 #define SCRATCH_PAD1_RDY        0x03  /* ready state */
0862 #define SCRATCH_PAD1_RST        0x04  /* soft reset toggle flag */
0863 #define SCRATCH_PAD1_AAP1RDY_RST    0x08  /* AAP1 ready for soft reset */
0864 #define SCRATCH_PAD1_STATE_MASK     0xFFFFFFF0   /* ScratchPad1
0865  Mask, bit1-0 State, bit2 Soft Reset, bit3 FW RDY for Soft Reset */
0866 #define SCRATCH_PAD1_RESERVED       0x000003F8   /* Scratch Pad1
0867  Reserved bit 3 to 9 */
0868
0869  /* state definition for Scratch Pad2 register */
0870 #define SCRATCH_PAD2_POR        0x00  /* power on state */
0871 #define SCRATCH_PAD2_SFR        0x01  /* soft reset state */
0872 #define SCRATCH_PAD2_ERR        0x02  /* error state */
0873 #define SCRATCH_PAD2_RDY        0x03  /* ready state */
0874 #define SCRATCH_PAD2_FWRDY_RST      0x04  /* FW ready for soft reset flag*/
0875 #define SCRATCH_PAD2_IOPRDY_RST     0x08  /* IOP ready for soft reset */
0876 #define SCRATCH_PAD2_STATE_MASK     0xFFFFFFF4 /* ScratchPad 2
0877  Mask, bit1-0 State */
0878 #define SCRATCH_PAD2_RESERVED       0x000003FC   /* Scratch Pad1
0879  Reserved bit 2 to 9 */
0880
0881 #define SCRATCH_PAD_ERROR_MASK      0xFFFFFC00   /* Error mask bits */
0882 #define SCRATCH_PAD_STATE_MASK      0x00000003   /* State Mask bits */
0883
0884 /* main configuration offset - byte offset */
0885 #define MAIN_SIGNATURE_OFFSET       0x00/* DWORD 0x00 */
0886 #define MAIN_INTERFACE_REVISION     0x04/* DWORD 0x01 */
0887 #define MAIN_FW_REVISION        0x08/* DWORD 0x02 */
0888 #define MAIN_MAX_OUTSTANDING_IO_OFFSET  0x0C/* DWORD 0x03 */
0889 #define MAIN_MAX_SGL_OFFSET     0x10/* DWORD 0x04 */
0890 #define MAIN_CNTRL_CAP_OFFSET       0x14/* DWORD 0x05 */
0891 #define MAIN_GST_OFFSET         0x18/* DWORD 0x06 */
0892 #define MAIN_IBQ_OFFSET         0x1C/* DWORD 0x07 */
0893 #define MAIN_OBQ_OFFSET         0x20/* DWORD 0x08 */
0894 #define MAIN_IQNPPD_HPPD_OFFSET     0x24/* DWORD 0x09 */
0895 #define MAIN_OB_HW_EVENT_PID03_OFFSET   0x28/* DWORD 0x0A */
0896 #define MAIN_OB_HW_EVENT_PID47_OFFSET   0x2C/* DWORD 0x0B */
0897 #define MAIN_OB_NCQ_EVENT_PID03_OFFSET  0x30/* DWORD 0x0C */
0898 #define MAIN_OB_NCQ_EVENT_PID47_OFFSET  0x34/* DWORD 0x0D */
0899 #define MAIN_TITNX_EVENT_PID03_OFFSET   0x38/* DWORD 0x0E */
0900 #define MAIN_TITNX_EVENT_PID47_OFFSET   0x3C/* DWORD 0x0F */
0901 #define MAIN_OB_SSP_EVENT_PID03_OFFSET  0x40/* DWORD 0x10 */
0902 #define MAIN_OB_SSP_EVENT_PID47_OFFSET  0x44/* DWORD 0x11 */
0903 #define MAIN_OB_SMP_EVENT_PID03_OFFSET  0x48/* DWORD 0x12 */
0904 #define MAIN_OB_SMP_EVENT_PID47_OFFSET  0x4C/* DWORD 0x13 */
0905 #define MAIN_EVENT_LOG_ADDR_HI      0x50/* DWORD 0x14 */
0906 #define MAIN_EVENT_LOG_ADDR_LO      0x54/* DWORD 0x15 */
0907 #define MAIN_EVENT_LOG_BUFF_SIZE    0x58/* DWORD 0x16 */
0908 #define MAIN_EVENT_LOG_OPTION       0x5C/* DWORD 0x17 */
0909 #define MAIN_IOP_EVENT_LOG_ADDR_HI  0x60/* DWORD 0x18 */
0910 #define MAIN_IOP_EVENT_LOG_ADDR_LO  0x64/* DWORD 0x19 */
0911 #define MAIN_IOP_EVENT_LOG_BUFF_SIZE    0x68/* DWORD 0x1A */
0912 #define MAIN_IOP_EVENT_LOG_OPTION   0x6C/* DWORD 0x1B */
0913 #define MAIN_FATAL_ERROR_INTERRUPT  0x70/* DWORD 0x1C */
0914 #define MAIN_FATAL_ERROR_RDUMP0_OFFSET  0x74/* DWORD 0x1D */
0915 #define MAIN_FATAL_ERROR_RDUMP0_LENGTH  0x78/* DWORD 0x1E */
0916 #define MAIN_FATAL_ERROR_RDUMP1_OFFSET  0x7C/* DWORD 0x1F */
0917 #define MAIN_FATAL_ERROR_RDUMP1_LENGTH  0x80/* DWORD 0x20 */
0918 #define MAIN_HDA_FLAGS_OFFSET       0x84/* DWORD 0x21 */
0919 #define MAIN_ANALOG_SETUP_OFFSET    0x88/* DWORD 0x22 */
0920
0921 /* Gereral Status Table offset - byte offset */
0922 #define GST_GSTLEN_MPIS_OFFSET      0x00
0923 #define GST_IQ_FREEZE_STATE0_OFFSET 0x04
0924 #define GST_IQ_FREEZE_STATE1_OFFSET 0x08
0925 #define GST_MSGUTCNT_OFFSET     0x0C
0926 #define GST_IOPTCNT_OFFSET      0x10
0927 #define GST_PHYSTATE_OFFSET     0x18
0928 #define GST_PHYSTATE0_OFFSET        0x18
0929 #define GST_PHYSTATE1_OFFSET        0x1C
0930 #define GST_PHYSTATE2_OFFSET        0x20
0931 #define GST_PHYSTATE3_OFFSET        0x24
0932 #define GST_PHYSTATE4_OFFSET        0x28
0933 #define GST_PHYSTATE5_OFFSET        0x2C
0934 #define GST_PHYSTATE6_OFFSET        0x30
0935 #define GST_PHYSTATE7_OFFSET        0x34
0936 #define GST_RERRINFO_OFFSET     0x44
0937
0938 /* General Status Table - MPI state */
0939 #define GST_MPI_STATE_UNINIT        0x00
0940 #define GST_MPI_STATE_INIT      0x01
0941 #define GST_MPI_STATE_TERMINATION   0x02
0942 #define GST_MPI_STATE_ERROR     0x03
0943 #define GST_MPI_STATE_MASK      0x07
0944
0945 #define MBIC_NMI_ENABLE_VPE0_IOP    0x000418
0946 #define MBIC_NMI_ENABLE_VPE0_AAP1   0x000418
0947 /* PCIE registers - BAR2(0x18), BAR1(win) 0x010000 */
0948 #define PCIE_EVENT_INTERRUPT_ENABLE 0x003040
0949 #define PCIE_EVENT_INTERRUPT        0x003044
0950 #define PCIE_ERROR_INTERRUPT_ENABLE 0x003048
0951 #define PCIE_ERROR_INTERRUPT        0x00304C
0952 /* signature definition for host scratch pad0 register */
0953 #define SPC_SOFT_RESET_SIGNATURE    0x252acbcd
0954 /* Signature for Soft Reset */
0955
0956 /* SPC Reset register - BAR4(0x20), BAR2(win) (need dynamic mapping) */
0957 #define SPC_REG_RESET           0x000000/* reset register */
0958
0959 /* bit difination for SPC_RESET register */
0960 #define   SPC_REG_RESET_OSSP        0x00000001
0961 #define   SPC_REG_RESET_RAAE        0x00000002
0962 #define   SPC_REG_RESET_PCS_SPBC    0x00000004
0963 #define   SPC_REG_RESET_PCS_IOP_SS  0x00000008
0964 #define   SPC_REG_RESET_PCS_AAP1_SS 0x00000010
0965 #define   SPC_REG_RESET_PCS_AAP2_SS 0x00000020
0966 #define   SPC_REG_RESET_PCS_LM      0x00000040
0967 #define   SPC_REG_RESET_PCS     0x00000080
0968 #define   SPC_REG_RESET_GSM     0x00000100
0969 #define   SPC_REG_RESET_DDR2        0x00010000
0970 #define   SPC_REG_RESET_BDMA_CORE   0x00020000
0971 #define   SPC_REG_RESET_BDMA_SXCBI  0x00040000
0972 #define   SPC_REG_RESET_PCIE_AL_SXCBI   0x00080000
0973 #define   SPC_REG_RESET_PCIE_PWR    0x00100000
0974 #define   SPC_REG_RESET_PCIE_SFT    0x00200000
0975 #define   SPC_REG_RESET_PCS_SXCBI   0x00400000
0976 #define   SPC_REG_RESET_LMS_SXCBI   0x00800000
0977 #define   SPC_REG_RESET_PMIC_SXCBI  0x01000000
0978 #define   SPC_REG_RESET_PMIC_CORE   0x02000000
0979 #define   SPC_REG_RESET_PCIE_PC_SXCBI   0x04000000
0980 #define   SPC_REG_RESET_DEVICE      0x80000000
0981
0982 /* registers for BAR Shifting - BAR2(0x18), BAR1(win) */
0983 #define SPC_IBW_AXI_TRANSLATION_LOW 0x003258
0984
0985 #define MBIC_AAP1_ADDR_BASE     0x060000
0986 #define MBIC_IOP_ADDR_BASE      0x070000
0987 #define GSM_ADDR_BASE           0x0700000
0988 /* Dynamic map through Bar4 - 0x00700000 */
0989 #define GSM_CONFIG_RESET        0x00000000
0990 #define RAM_ECC_DB_ERR          0x00000018
0991 #define GSM_READ_ADDR_PARITY_INDIC  0x00000058
0992 #define GSM_WRITE_ADDR_PARITY_INDIC 0x00000060
0993 #define GSM_WRITE_DATA_PARITY_INDIC 0x00000068
0994 #define GSM_READ_ADDR_PARITY_CHECK  0x00000038
0995 #define GSM_WRITE_ADDR_PARITY_CHECK 0x00000040
0996 #define GSM_WRITE_DATA_PARITY_CHECK 0x00000048
0997
0998 #define RB6_ACCESS_REG          0x6A0000
0999 #define HDAC_EXEC_CMD           0x0002
1000 #define HDA_C_PA            0xcb
1001 #define HDA_SEQ_ID_BITS         0x00ff0000
1002 #define HDA_GSM_OFFSET_BITS     0x00FFFFFF
1003 #define MBIC_AAP1_ADDR_BASE     0x060000
1004 #define MBIC_IOP_ADDR_BASE      0x070000
1005 #define GSM_ADDR_BASE           0x0700000
1006 #define SPC_TOP_LEVEL_ADDR_BASE     0x000000
1007 #define GSM_CONFIG_RESET_VALUE          0x00003b00
1008 #define GPIO_ADDR_BASE                  0x00090000
1009 #define GPIO_GPIO_0_0UTPUT_CTL_OFFSET   0x0000010c
1010
1011 /* RB6 offset */
1012 #define SPC_RB6_OFFSET          0x80C0
1013 /* Magic number of  soft reset for RB6 */
1014 #define RB6_MAGIC_NUMBER_RST        0x1234
1015
1016 /* Device Register status */
1017 #define DEVREG_SUCCESS                  0x00
1018 #define DEVREG_FAILURE_OUT_OF_RESOURCE          0x01
1019 #define DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED    0x02
1020 #define DEVREG_FAILURE_INVALID_PHY_ID           0x03
1021 #define DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED    0x04
1022 #define DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE     0x05
1023 #define DEVREG_FAILURE_PORT_NOT_VALID_STATE     0x06
1024 #define DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID        0x07
1025
1026 #define GSM_BASE                    0x4F0000
1027 #define SHIFT_REG_64K_MASK              0xffff0000
1028 #define SHIFT_REG_BIT_SHIFT             8
1029 #endif
1030