drivers/scsi/nsp32_io.h

0001 /*
0002  * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
0003  * I/O routine
0004  *
0005  * This software may be used and distributed according to the terms of
0006  * the GNU General Public License.
0007  */
0008
0009 #ifndef _NSP32_IO_H
0010 #define _NSP32_IO_H
0011
0012 static inline void nsp32_write1(unsigned int  base,
0013                 unsigned int  index,
0014                 unsigned char val)
0015 {
0016     outb(val, (base + index));
0017 }
0018
0019 static inline unsigned char nsp32_read1(unsigned int base,
0020                     unsigned int index)
0021 {
0022     return inb(base + index);
0023 }
0024
0025 static inline void nsp32_write2(unsigned int   base,
0026                 unsigned int   index,
0027                 unsigned short val)
0028 {
0029     outw(val, (base + index));
0030 }
0031
0032 static inline unsigned short nsp32_read2(unsigned int base,
0033                      unsigned int index)
0034 {
0035     return inw(base + index);
0036 }
0037
0038 static inline void nsp32_write4(unsigned int  base,
0039                 unsigned int  index,
0040                 unsigned long val)
0041 {
0042     outl(val, (base + index));
0043 }
0044
0045 static inline unsigned long nsp32_read4(unsigned int base,
0046                     unsigned int index)
0047 {
0048     return inl(base + index);
0049 }
0050
0051 /*==============================================*/
0052
0053 static inline void nsp32_mmio_write1(unsigned long base,
0054                      unsigned int  index,
0055                      unsigned char val)
0056 {
0057     volatile unsigned char *ptr;
0058
0059     ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index);
0060
0061     writeb(val, ptr);
0062 }
0063
0064 static inline unsigned char nsp32_mmio_read1(unsigned long base,
0065                          unsigned int  index)
0066 {
0067     volatile unsigned char *ptr;
0068
0069     ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index);
0070
0071     return readb(ptr);
0072 }
0073
0074 static inline void nsp32_mmio_write2(unsigned long  base,
0075                      unsigned int   index,
0076                      unsigned short val)
0077 {
0078     volatile unsigned short *ptr;
0079
0080     ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index);
0081
0082     writew(cpu_to_le16(val), ptr);
0083 }
0084
0085 static inline unsigned short nsp32_mmio_read2(unsigned long base,
0086                           unsigned int  index)
0087 {
0088     volatile unsigned short *ptr;
0089
0090     ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index);
0091
0092     return le16_to_cpu(readw(ptr));
0093 }
0094
0095 static inline void nsp32_mmio_write4(unsigned long base,
0096                      unsigned int  index,
0097                      unsigned long val)
0098 {
0099     volatile unsigned long *ptr;
0100
0101     ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index);
0102
0103     writel(cpu_to_le32(val), ptr);
0104 }
0105
0106 static inline unsigned long nsp32_mmio_read4(unsigned long base,
0107                          unsigned int  index)
0108 {
0109     volatile unsigned long *ptr;
0110
0111     ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index);
0112
0113     return le32_to_cpu(readl(ptr));
0114 }
0115
0116 /*==============================================*/
0117
0118 static inline unsigned char nsp32_index_read1(unsigned int base,
0119                           unsigned int reg)
0120 {
0121     outb(reg, base + INDEX_REG);
0122     return inb(base + DATA_REG_LOW);
0123 }
0124
0125 static inline void nsp32_index_write1(unsigned int  base,
0126                       unsigned int  reg,
0127                       unsigned char val)
0128 {
0129     outb(reg, base + INDEX_REG   );
0130     outb(val, base + DATA_REG_LOW);
0131 }
0132
0133 static inline unsigned short nsp32_index_read2(unsigned int base,
0134                            unsigned int reg)
0135 {
0136     outb(reg, base + INDEX_REG);
0137     return inw(base + DATA_REG_LOW);
0138 }
0139
0140 static inline void nsp32_index_write2(unsigned int   base,
0141                       unsigned int   reg,
0142                       unsigned short val)
0143 {
0144     outb(reg, base + INDEX_REG   );
0145     outw(val, base + DATA_REG_LOW);
0146 }
0147
0148 static inline unsigned long nsp32_index_read4(unsigned int base,
0149                           unsigned int reg)
0150 {
0151     unsigned long h,l;
0152
0153     outb(reg, base + INDEX_REG);
0154     l = inw(base + DATA_REG_LOW);
0155     h = inw(base + DATA_REG_HI );
0156
0157     return ((h << 16) | l);
0158 }
0159
0160 static inline void nsp32_index_write4(unsigned int  base,
0161                       unsigned int  reg,
0162                       unsigned long val)
0163 {
0164     unsigned long h,l;
0165
0166     h = (val & 0xffff0000) >> 16;
0167     l = (val & 0x0000ffff) >>  0;
0168
0169     outb(reg, base + INDEX_REG   );
0170     outw(l,   base + DATA_REG_LOW);
0171     outw(h,   base + DATA_REG_HI );
0172 }
0173
0174 /*==============================================*/
0175
0176 static inline unsigned char nsp32_mmio_index_read1(unsigned long base,
0177                            unsigned int reg)
0178 {
0179     volatile unsigned short *index_ptr, *data_ptr;
0180
0181     index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
0182     data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
0183
0184     writeb(reg, index_ptr);
0185     return readb(data_ptr);
0186 }
0187
0188 static inline void nsp32_mmio_index_write1(unsigned long base,
0189                        unsigned int  reg,
0190                        unsigned char val)
0191 {
0192     volatile unsigned short *index_ptr, *data_ptr;
0193
0194     index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
0195     data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
0196
0197     writeb(reg, index_ptr);
0198     writeb(val, data_ptr );
0199 }
0200
0201 static inline unsigned short nsp32_mmio_index_read2(unsigned long base,
0202                             unsigned int  reg)
0203 {
0204     volatile unsigned short *index_ptr, *data_ptr;
0205
0206     index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
0207     data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
0208
0209     writeb(reg, index_ptr);
0210     return le16_to_cpu(readw(data_ptr));
0211 }
0212
0213 static inline void nsp32_mmio_index_write2(unsigned long  base,
0214                        unsigned int   reg,
0215                        unsigned short val)
0216 {
0217     volatile unsigned short *index_ptr, *data_ptr;
0218
0219     index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
0220     data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
0221
0222     writeb(reg,              index_ptr);
0223     writew(cpu_to_le16(val), data_ptr );
0224 }
0225
0226 /*==============================================*/
0227
0228 static inline void nsp32_multi_read4(unsigned int   base,
0229                      unsigned int   reg,
0230                      void          *buf,
0231                      unsigned long  count)
0232 {
0233     insl(base + reg, buf, count);
0234 }
0235
0236 static inline void nsp32_fifo_read(unsigned int   base,
0237                    void          *buf,
0238                    unsigned long  count)
0239 {
0240     nsp32_multi_read4(base, FIFO_DATA_LOW, buf, count);
0241 }
0242
0243 static inline void nsp32_multi_write4(unsigned int   base,
0244                       unsigned int   reg,
0245                       void          *buf,
0246                       unsigned long  count)
0247 {
0248     outsl(base + reg, buf, count);
0249 }
0250
0251 static inline void nsp32_fifo_write(unsigned int   base,
0252                     void          *buf,
0253                     unsigned long  count)
0254 {
0255     nsp32_multi_write4(base, FIFO_DATA_LOW, buf, count);
0256 }
0257
0258 #endif /* _NSP32_IO_H */
0259 /* end */