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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /******************************************************************************
0003 **  Device driver for the PCI-SCSI NCR538XX controller family.
0004 **
0005 **  Copyright (C) 1994  Wolfgang Stanglmeier
0006 **  Copyright (C) 1998-2001  Gerard Roudier <groudier@free.fr>
0007 **
0008 **
0009 **-----------------------------------------------------------------------------
0010 **
0011 **  This driver has been ported to Linux from the FreeBSD NCR53C8XX driver
0012 **  and is currently maintained by
0013 **
0014 **          Gerard Roudier              <groudier@free.fr>
0015 **
0016 **  Being given that this driver originates from the FreeBSD version, and
0017 **  in order to keep synergy on both, any suggested enhancements and corrections
0018 **  received on Linux are automatically a potential candidate for the FreeBSD 
0019 **  version.
0020 **
0021 **  The original driver has been written for 386bsd and FreeBSD by
0022 **          Wolfgang Stanglmeier        <wolf@cologne.de>
0023 **          Stefan Esser                <se@mi.Uni-Koeln.de>
0024 **
0025 **  And has been ported to NetBSD by
0026 **          Charles M. Hannum           <mycroft@gnu.ai.mit.edu>
0027 **
0028 **  NVRAM detection and reading.
0029 **    Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
0030 **
0031 **  Added support for MIPS big endian systems.
0032 **    Carsten Langgaard, carstenl@mips.com
0033 **    Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
0034 **
0035 **  Added support for HP PARISC big endian systems.
0036 **    Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
0037 **
0038 *******************************************************************************
0039 */
0040 
0041 #ifndef NCR53C8XX_H
0042 #define NCR53C8XX_H
0043 
0044 #include <scsi/scsi_host.h>
0045 
0046 
0047 /*
0048 **  If you want a driver as small as possible, donnot define the 
0049 **  following options.
0050 */
0051 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
0052 #define SCSI_NCR_DEBUG_INFO_SUPPORT
0053 
0054 /*
0055 **  To disable integrity checking, do not define the 
0056 **  following option.
0057 */
0058 #ifdef  CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
0059 #   define SCSI_NCR_ENABLE_INTEGRITY_CHECK
0060 #endif
0061 
0062 /* ---------------------------------------------------------------------
0063 ** Take into account kernel configured parameters.
0064 ** Most of these options can be overridden at startup by a command line.
0065 ** ---------------------------------------------------------------------
0066 */
0067 
0068 /*
0069  * For Ultra2 and Ultra3 SCSI support option, use special features. 
0070  *
0071  * Value (default) means:
0072  *  bit 0 : all features enabled, except:
0073  *      bit 1 : PCI Write And Invalidate.
0074  *      bit 2 : Data Phase Mismatch handling from SCRIPTS.
0075  *
0076  * Use boot options ncr53c8xx=specf:1 if you want all chip features to be 
0077  * enabled by the driver.
0078  */
0079 #define SCSI_NCR_SETUP_SPECIAL_FEATURES     (3)
0080 
0081 #define SCSI_NCR_MAX_SYNC           (80)
0082 
0083 /*
0084  * Allow tags from 2 to 256, default 8
0085  */
0086 #ifdef  CONFIG_SCSI_NCR53C8XX_MAX_TAGS
0087 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
0088 #define SCSI_NCR_MAX_TAGS   (2)
0089 #elif   CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
0090 #define SCSI_NCR_MAX_TAGS   (256)
0091 #else
0092 #define SCSI_NCR_MAX_TAGS   CONFIG_SCSI_NCR53C8XX_MAX_TAGS
0093 #endif
0094 #else
0095 #define SCSI_NCR_MAX_TAGS   (8)
0096 #endif
0097 
0098 /*
0099  * Allow tagged command queuing support if configured with default number 
0100  * of tags set to max (see above).
0101  */
0102 #ifdef  CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
0103 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
0104 #elif   defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
0105 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
0106 #else
0107 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
0108 #endif
0109 
0110 /*
0111  * Immediate arbitration
0112  */
0113 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
0114 #define SCSI_NCR_IARB_SUPPORT
0115 #endif
0116 
0117 /*
0118  * Sync transfer frequency at startup.
0119  * Allow from 5Mhz to 80Mhz default 20 Mhz.
0120  */
0121 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
0122 #define CONFIG_SCSI_NCR53C8XX_SYNC  (20)
0123 #elif   CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
0124 #undef  CONFIG_SCSI_NCR53C8XX_SYNC
0125 #define CONFIG_SCSI_NCR53C8XX_SYNC  SCSI_NCR_MAX_SYNC
0126 #endif
0127 
0128 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
0129 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
0130 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 5
0131 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
0132 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 20
0133 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
0134 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 33
0135 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
0136 #elif   CONFIG_SCSI_NCR53C8XX_SYNC <= 40
0137 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
0138 #else
0139 #define SCSI_NCR_SETUP_DEFAULT_SYNC     (9)
0140 #endif
0141 
0142 /*
0143  * Disallow disconnections at boot-up
0144  */
0145 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
0146 #define SCSI_NCR_SETUP_DISCONNECTION    (0)
0147 #else
0148 #define SCSI_NCR_SETUP_DISCONNECTION    (1)
0149 #endif
0150 
0151 /*
0152  * Force synchronous negotiation for all targets
0153  */
0154 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
0155 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO  (1)
0156 #else
0157 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO  (0)
0158 #endif
0159 
0160 /*
0161  * Disable master parity checking (flawed hardwares need that)
0162  */
0163 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
0164 #define SCSI_NCR_SETUP_MASTER_PARITY    (0)
0165 #else
0166 #define SCSI_NCR_SETUP_MASTER_PARITY    (1)
0167 #endif
0168 
0169 /*
0170  * Disable scsi parity checking (flawed devices may need that)
0171  */
0172 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
0173 #define SCSI_NCR_SETUP_SCSI_PARITY  (0)
0174 #else
0175 #define SCSI_NCR_SETUP_SCSI_PARITY  (1)
0176 #endif
0177 
0178 /*
0179  * Settle time after reset at boot-up
0180  */
0181 #define SCSI_NCR_SETUP_SETTLE_TIME  (2)
0182 
0183 /*
0184 **  Bridge quirks work-around option defaulted to 1.
0185 */
0186 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
0187 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT   1
0188 #endif
0189 
0190 /*
0191 **  Work-around common bridge misbehaviour.
0192 **
0193 **  - Do not flush posted writes in the opposite 
0194 **    direction on read.
0195 **  - May reorder DMA writes to memory.
0196 **
0197 **  This option should not affect performances 
0198 **  significantly, so it is the default.
0199 */
0200 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
0201 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
0202 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
0203 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
0204 
0205 /*
0206 **  Same as option 1, but also deal with 
0207 **  misconfigured interrupts.
0208 **
0209 **  - Edge triggered instead of level sensitive.
0210 **  - No interrupt line connected.
0211 **  - IRQ number misconfigured.
0212 **  
0213 **  If no interrupt is delivered, the driver will 
0214 **  catch the interrupt conditions 10 times per 
0215 **  second. No need to say that this option is 
0216 **  not recommended.
0217 */
0218 #elif   SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
0219 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
0220 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
0221 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
0222 #define SCSI_NCR_PCIQ_BROKEN_INTR
0223 
0224 /*
0225 **  Some bridge designers decided to flush 
0226 **  everything prior to deliver the interrupt.
0227 **  This option tries to deal with such a 
0228 **  behaviour.
0229 */
0230 #elif   SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
0231 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
0232 #endif
0233 
0234 /*
0235 **  Other parameters not configurable with "make config"
0236 **  Avoid to change these constants, unless you know what you are doing.
0237 */
0238 
0239 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
0240 #define SCSI_NCR_MAX_SCATTER    (127)
0241 #define SCSI_NCR_MAX_TARGET (16)
0242 
0243 /*
0244 **   Compute some desirable value for CAN_QUEUE 
0245 **   and CMD_PER_LUN.
0246 **   The driver will use lower values if these 
0247 **   ones appear to be too large.
0248 */
0249 #define SCSI_NCR_CAN_QUEUE  (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
0250 #define SCSI_NCR_CMD_PER_LUN    (SCSI_NCR_MAX_TAGS)
0251 
0252 #define SCSI_NCR_SG_TABLESIZE   (SCSI_NCR_MAX_SCATTER)
0253 #define SCSI_NCR_TIMER_INTERVAL (HZ)
0254 
0255 #define SCSI_NCR_MAX_LUN    (16)
0256 
0257 /*
0258  *  IO functions definition for big/little endian CPU support.
0259  *  For now, the NCR is only supported in little endian addressing mode, 
0260  */
0261 
0262 #ifdef  __BIG_ENDIAN
0263 
0264 #define inw_l2b     inw
0265 #define inl_l2b     inl
0266 #define outw_b2l    outw
0267 #define outl_b2l    outl
0268 
0269 #define readb_raw   readb
0270 #define writeb_raw  writeb
0271 
0272 #if defined(SCSI_NCR_BIG_ENDIAN)
0273 #define readw_l2b   __raw_readw
0274 #define readl_l2b   __raw_readl
0275 #define writew_b2l  __raw_writew
0276 #define writel_b2l  __raw_writel
0277 #define readw_raw   __raw_readw
0278 #define readl_raw   __raw_readl
0279 #define writew_raw  __raw_writew
0280 #define writel_raw  __raw_writel
0281 #else   /* Other big-endian */
0282 #define readw_l2b   readw
0283 #define readl_l2b   readl
0284 #define writew_b2l  writew
0285 #define writel_b2l  writel
0286 #define readw_raw   readw
0287 #define readl_raw   readl
0288 #define writew_raw  writew
0289 #define writel_raw  writel
0290 #endif
0291 
0292 #else   /* little endian */
0293 
0294 #define inw_raw     inw
0295 #define inl_raw     inl
0296 #define outw_raw    outw
0297 #define outl_raw    outl
0298 
0299 #define readb_raw   readb
0300 #define readw_raw   readw
0301 #define readl_raw   readl
0302 #define writeb_raw  writeb
0303 #define writew_raw  writew
0304 #define writel_raw  writel
0305 
0306 #endif
0307 
0308 #if !defined(__hppa__) && !defined(__mips__)
0309 #ifdef  SCSI_NCR_BIG_ENDIAN
0310 #error  "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
0311 #endif
0312 #endif
0313 
0314 #define MEMORY_BARRIER()    mb()
0315 
0316 
0317 /*
0318  *  If the NCR uses big endian addressing mode over the 
0319  *  PCI, actual io register addresses for byte and word 
0320  *  accesses must be changed according to lane routing.
0321  *  Btw, ncr_offb() and ncr_offw() macros only apply to 
0322  *  constants and so donnot generate bloated code.
0323  */
0324 
0325 #if defined(SCSI_NCR_BIG_ENDIAN)
0326 
0327 #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
0328 #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
0329 
0330 #else
0331 
0332 #define ncr_offb(o) (o)
0333 #define ncr_offw(o) (o)
0334 
0335 #endif
0336 
0337 /*
0338  *  If the CPU and the NCR use same endian-ness addressing,
0339  *  no byte reordering is needed for script patching.
0340  *  Macro cpu_to_scr() is to be used for script patching.
0341  *  Macro scr_to_cpu() is to be used for getting a DWORD 
0342  *  from the script.
0343  */
0344 
0345 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
0346 
0347 #define cpu_to_scr(dw)  cpu_to_le32(dw)
0348 #define scr_to_cpu(dw)  le32_to_cpu(dw)
0349 
0350 #elif   defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
0351 
0352 #define cpu_to_scr(dw)  cpu_to_be32(dw)
0353 #define scr_to_cpu(dw)  be32_to_cpu(dw)
0354 
0355 #else
0356 
0357 #define cpu_to_scr(dw)  (dw)
0358 #define scr_to_cpu(dw)  (dw)
0359 
0360 #endif
0361 
0362 /*
0363  *  Access to the controller chip.
0364  *
0365  *  If the CPU and the NCR use same endian-ness addressing,
0366  *  no byte reordering is needed for accessing chip io 
0367  *  registers. Functions suffixed by '_raw' are assumed 
0368  *  to access the chip over the PCI without doing byte 
0369  *  reordering. Functions suffixed by '_l2b' are 
0370  *  assumed to perform little-endian to big-endian byte 
0371  *  reordering, those suffixed by '_b2l' blah, blah,
0372  *  blah, ...
0373  */
0374 
0375 /*
0376  *  MEMORY mapped IO input / output
0377  */
0378 
0379 #define INB_OFF(o)      readb_raw((char __iomem *)np->reg + ncr_offb(o))
0380 #define OUTB_OFF(o, val)    writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
0381 
0382 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
0383 
0384 #define INW_OFF(o)      readw_l2b((char __iomem *)np->reg + ncr_offw(o))
0385 #define INL_OFF(o)      readl_l2b((char __iomem *)np->reg + (o))
0386 
0387 #define OUTW_OFF(o, val)    writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
0388 #define OUTL_OFF(o, val)    writel_b2l((val), (char __iomem *)np->reg + (o))
0389 
0390 #elif   defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
0391 
0392 #define INW_OFF(o)      readw_b2l((char __iomem *)np->reg + ncr_offw(o))
0393 #define INL_OFF(o)      readl_b2l((char __iomem *)np->reg + (o))
0394 
0395 #define OUTW_OFF(o, val)    writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
0396 #define OUTL_OFF(o, val)    writel_l2b((val), (char __iomem *)np->reg + (o))
0397 
0398 #else
0399 
0400 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
0401 /* Only 8 or 32 bit transfers allowed */
0402 #define INW_OFF(o)      (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
0403 #else
0404 #define INW_OFF(o)      readw_raw((char __iomem *)np->reg + ncr_offw(o))
0405 #endif
0406 #define INL_OFF(o)      readl_raw((char __iomem *)np->reg + (o))
0407 
0408 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
0409 /* Only 8 or 32 bit transfers allowed */
0410 #define OUTW_OFF(o, val)    do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
0411 #else
0412 #define OUTW_OFF(o, val)    writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
0413 #endif
0414 #define OUTL_OFF(o, val)    writel_raw((val), (char __iomem *)np->reg + (o))
0415 
0416 #endif
0417 
0418 #define INB(r)      INB_OFF (offsetof(struct ncr_reg,r))
0419 #define INW(r)      INW_OFF (offsetof(struct ncr_reg,r))
0420 #define INL(r)      INL_OFF (offsetof(struct ncr_reg,r))
0421 
0422 #define OUTB(r, val)    OUTB_OFF (offsetof(struct ncr_reg,r), (val))
0423 #define OUTW(r, val)    OUTW_OFF (offsetof(struct ncr_reg,r), (val))
0424 #define OUTL(r, val)    OUTL_OFF (offsetof(struct ncr_reg,r), (val))
0425 
0426 /*
0427  *  Set bit field ON, OFF 
0428  */
0429 
0430 #define OUTONB(r, m)    OUTB(r, INB(r) | (m))
0431 #define OUTOFFB(r, m)   OUTB(r, INB(r) & ~(m))
0432 #define OUTONW(r, m)    OUTW(r, INW(r) | (m))
0433 #define OUTOFFW(r, m)   OUTW(r, INW(r) & ~(m))
0434 #define OUTONL(r, m)    OUTL(r, INL(r) | (m))
0435 #define OUTOFFL(r, m)   OUTL(r, INL(r) & ~(m))
0436 
0437 /*
0438  *  We normally want the chip to have a consistent view
0439  *  of driver internal data structures when we restart it.
0440  *  Thus these macros.
0441  */
0442 #define OUTL_DSP(v)             \
0443     do {                    \
0444         MEMORY_BARRIER();       \
0445         OUTL (nc_dsp, (v));     \
0446     } while (0)
0447 
0448 #define OUTONB_STD()                \
0449     do {                    \
0450         MEMORY_BARRIER();       \
0451         OUTONB (nc_dcntl, (STD|NOCOM)); \
0452     } while (0)
0453 
0454 
0455 /*
0456 **   NCR53C8XX devices features table.
0457 */
0458 struct ncr_chip {
0459     unsigned short  revision_id;
0460     unsigned char   burst_max;  /* log-base-2 of max burst */
0461     unsigned char   offset_max;
0462     unsigned char   nr_divisor;
0463     unsigned int    features;
0464 #define FE_LED0     (1<<0)
0465 #define FE_WIDE     (1<<1)    /* Wide data transfers */
0466 #define FE_ULTRA    (1<<2)    /* Ultra speed 20Mtrans/sec */
0467 #define FE_DBLR     (1<<4)    /* Clock doubler present */
0468 #define FE_QUAD     (1<<5)    /* Clock quadrupler present */
0469 #define FE_ERL      (1<<6)    /* Enable read line */
0470 #define FE_CLSE     (1<<7)    /* Cache line size enable */
0471 #define FE_WRIE     (1<<8)    /* Write & Invalidate enable */
0472 #define FE_ERMP     (1<<9)    /* Enable read multiple */
0473 #define FE_BOF      (1<<10)   /* Burst opcode fetch */
0474 #define FE_DFS      (1<<11)   /* DMA fifo size */
0475 #define FE_PFEN     (1<<12)   /* Prefetch enable */
0476 #define FE_LDSTR    (1<<13)   /* Load/Store supported */
0477 #define FE_RAM      (1<<14)   /* On chip RAM present */
0478 #define FE_VARCLK   (1<<15)   /* SCSI clock may vary */
0479 #define FE_RAM8K    (1<<16)   /* On chip RAM sized 8Kb */
0480 #define FE_64BIT    (1<<17)   /* Have a 64-bit PCI interface */
0481 #define FE_IO256    (1<<18)   /* Requires full 256 bytes in PCI space */
0482 #define FE_NOPM     (1<<19)   /* Scripts handles phase mismatch */
0483 #define FE_LEDC     (1<<20)   /* Hardware control of LED */
0484 #define FE_DIFF     (1<<21)   /* Support Differential SCSI */
0485 #define FE_66MHZ    (1<<23)   /* 66MHz PCI Support */
0486 #define FE_DAC      (1<<24)   /* Support DAC cycles (64 bit addressing) */
0487 #define FE_ISTAT1   (1<<25)   /* Have ISTAT1, MBOX0, MBOX1 registers */
0488 #define FE_DAC_IN_USE   (1<<26)   /* Platform does DAC cycles */
0489 #define FE_EHP      (1<<27)   /* 720: Even host parity */
0490 #define FE_MUX      (1<<28)   /* 720: Multiplexed bus */
0491 #define FE_EA       (1<<29)   /* 720: Enable Ack */
0492 
0493 #define FE_CACHE_SET    (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
0494 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
0495 #define FE_SPECIAL_SET  (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
0496 };
0497 
0498 
0499 /*
0500 **  Driver setup structure.
0501 **
0502 **  This structure is initialized from linux config options.
0503 **  It can be overridden at boot-up by the boot command line.
0504 */
0505 #define SCSI_NCR_MAX_EXCLUDES 8
0506 struct ncr_driver_setup {
0507     u8  master_parity;
0508     u8  scsi_parity;
0509     u8  disconnection;
0510     u8  special_features;
0511     u8  force_sync_nego;
0512     u8  reverse_probe;
0513     u8  pci_fix_up;
0514     u8  use_nvram;
0515     u8  verbose;
0516     u8  default_tags;
0517     u16 default_sync;
0518     u16 debug;
0519     u8  burst_max;
0520     u8  led_pin;
0521     u8  max_wide;
0522     u8  settle_delay;
0523     u8  diff_support;
0524     u8  irqm;
0525     u8  bus_check;
0526     u8  optimize;
0527     u8  recovery;
0528     u8  host_id;
0529     u16 iarb;
0530     u32 excludes[SCSI_NCR_MAX_EXCLUDES];
0531     char    tag_ctrl[100];
0532 };
0533 
0534 /*
0535 **  Initial setup.
0536 **  Can be overridden at startup by a command line.
0537 */
0538 #define SCSI_NCR_DRIVER_SETUP           \
0539 {                       \
0540     SCSI_NCR_SETUP_MASTER_PARITY,       \
0541     SCSI_NCR_SETUP_SCSI_PARITY,     \
0542     SCSI_NCR_SETUP_DISCONNECTION,       \
0543     SCSI_NCR_SETUP_SPECIAL_FEATURES,    \
0544     SCSI_NCR_SETUP_FORCE_SYNC_NEGO,     \
0545     0,                  \
0546     0,                  \
0547     1,                  \
0548     0,                  \
0549     SCSI_NCR_SETUP_DEFAULT_TAGS,        \
0550     SCSI_NCR_SETUP_DEFAULT_SYNC,        \
0551     0x00,                   \
0552     7,                  \
0553     0,                  \
0554     1,                  \
0555     SCSI_NCR_SETUP_SETTLE_TIME,     \
0556     0,                  \
0557     0,                  \
0558     1,                  \
0559     0,                  \
0560     0,                  \
0561     255,                    \
0562     0x00                    \
0563 }
0564 
0565 /*
0566 **  Boot fail safe setup.
0567 **  Override initial setup from boot command line:
0568 **  ncr53c8xx=safe:y
0569 */
0570 #define SCSI_NCR_DRIVER_SAFE_SETUP      \
0571 {                       \
0572     0,                  \
0573     1,                  \
0574     0,                  \
0575     0,                  \
0576     0,                  \
0577     0,                  \
0578     0,                  \
0579     1,                  \
0580     2,                  \
0581     0,                  \
0582     255,                    \
0583     0x00,                   \
0584     255,                    \
0585     0,                  \
0586     0,                  \
0587     10,                 \
0588     1,                  \
0589     1,                  \
0590     1,                  \
0591     0,                  \
0592     0,                  \
0593     255                 \
0594 }
0595 
0596 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
0597 
0598 /*-----------------------------------------------------------------
0599 **
0600 **  The ncr 53c810 register structure.
0601 **
0602 **-----------------------------------------------------------------
0603 */
0604 
0605 struct ncr_reg {
0606 /*00*/  u8  nc_scntl0;    /* full arb., ena parity, par->ATN  */
0607 
0608 /*01*/  u8  nc_scntl1;    /* no reset                         */
0609         #define   ISCON   0x10  /* connected to scsi            */
0610         #define   CRST    0x08  /* force reset                      */
0611         #define   IARB    0x02  /* immediate arbitration            */
0612 
0613 /*02*/  u8  nc_scntl2;    /* no disconnect expected           */
0614     #define   SDU     0x80  /* cmd: disconnect will raise error */
0615     #define   CHM     0x40  /* sta: chained mode                */
0616     #define   WSS     0x08  /* sta: wide scsi send           [W]*/
0617     #define   WSR     0x01  /* sta: wide scsi received       [W]*/
0618 
0619 /*03*/  u8  nc_scntl3;    /* cnf system clock dependent       */
0620     #define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
0621     #define   ULTRA   0x80  /* cmd: ULTRA enable                */
0622                 /* bits 0-2, 7 rsvd for C1010       */
0623 
0624 /*04*/  u8  nc_scid;    /* cnf host adapter scsi address    */
0625     #define   RRE     0x40  /* r/w:e enable response to resel.  */
0626     #define   SRE     0x20  /* r/w:e enable response to select  */
0627 
0628 /*05*/  u8  nc_sxfer;   /* ### Sync speed and count         */
0629                 /* bits 6-7 rsvd for C1010          */
0630 
0631 /*06*/  u8  nc_sdid;    /* ### Destination-ID               */
0632 
0633 /*07*/  u8  nc_gpreg;   /* ??? IO-Pins                      */
0634 
0635 /*08*/  u8  nc_sfbr;    /* ### First byte in phase          */
0636 
0637 /*09*/  u8  nc_socl;
0638     #define   CREQ    0x80  /* r/w: SCSI-REQ                    */
0639     #define   CACK    0x40  /* r/w: SCSI-ACK                    */
0640     #define   CBSY    0x20  /* r/w: SCSI-BSY                    */
0641     #define   CSEL    0x10  /* r/w: SCSI-SEL                    */
0642     #define   CATN    0x08  /* r/w: SCSI-ATN                    */
0643     #define   CMSG    0x04  /* r/w: SCSI-MSG                    */
0644     #define   CC_D    0x02  /* r/w: SCSI-C_D                    */
0645     #define   CI_O    0x01  /* r/w: SCSI-I_O                    */
0646 
0647 /*0a*/  u8  nc_ssid;
0648 
0649 /*0b*/  u8  nc_sbcl;
0650 
0651 /*0c*/  u8  nc_dstat;
0652         #define   DFE     0x80  /* sta: dma fifo empty              */
0653         #define   MDPE    0x40  /* int: master data parity error    */
0654         #define   BF      0x20  /* int: script: bus fault           */
0655         #define   ABRT    0x10  /* int: script: command aborted     */
0656         #define   SSI     0x08  /* int: script: single step         */
0657         #define   SIR     0x04  /* int: script: interrupt instruct. */
0658         #define   IID     0x01  /* int: script: illegal instruct.   */
0659 
0660 /*0d*/  u8  nc_sstat0;
0661         #define   ILF     0x80  /* sta: data in SIDL register lsb   */
0662         #define   ORF     0x40  /* sta: data in SODR register lsb   */
0663         #define   OLF     0x20  /* sta: data in SODL register lsb   */
0664         #define   AIP     0x10  /* sta: arbitration in progress     */
0665         #define   LOA     0x08  /* sta: arbitration lost            */
0666         #define   WOA     0x04  /* sta: arbitration won             */
0667         #define   IRST    0x02  /* sta: scsi reset signal           */
0668         #define   SDP     0x01  /* sta: scsi parity signal          */
0669 
0670 /*0e*/  u8  nc_sstat1;
0671     #define   FF3210  0xf0  /* sta: bytes in the scsi fifo      */
0672 
0673 /*0f*/  u8  nc_sstat2;
0674         #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
0675         #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
0676         #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
0677         #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
0678         #define   LDSC    0x02  /* sta: disconnect & reconnect      */
0679 
0680 /*10*/  u8  nc_dsa; /* --> Base page                    */
0681 /*11*/  u8  nc_dsa1;
0682 /*12*/  u8  nc_dsa2;
0683 /*13*/  u8  nc_dsa3;
0684 
0685 /*14*/  u8  nc_istat;   /* --> Main Command and status      */
0686         #define   CABRT   0x80  /* cmd: abort current operation     */
0687         #define   SRST    0x40  /* mod: reset chip                  */
0688         #define   SIGP    0x20  /* r/w: message from host to ncr    */
0689         #define   SEM     0x10  /* r/w: message between host + ncr  */
0690         #define   CON     0x08  /* sta: connected to scsi           */
0691         #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
0692         #define   SIP     0x02  /* sta: scsi-interrupt              */
0693         #define   DIP     0x01  /* sta: host/script interrupt       */
0694 
0695 /*15*/  u8  nc_istat1;  /* 896 and later cores only */
0696         #define   FLSH    0x04  /* sta: chip is flushing            */
0697         #define   SRUN    0x02  /* sta: scripts are running         */
0698         #define   SIRQD   0x01  /* r/w: disable INT pin             */
0699 
0700 /*16*/  u8  nc_mbox0;   /* 896 and later cores only */
0701 /*17*/  u8  nc_mbox1;   /* 896 and later cores only */
0702 
0703 /*18*/  u8  nc_ctest0;
0704     #define   EHP     0x04  /* 720 even host parity             */
0705 /*19*/  u8  nc_ctest1;
0706 
0707 /*1a*/  u8  nc_ctest2;
0708     #define   CSIGP   0x40
0709                 /* bits 0-2,7 rsvd for C1010        */
0710 
0711 /*1b*/  u8  nc_ctest3;
0712     #define   FLF     0x08  /* cmd: flush dma fifo              */
0713     #define   CLF     0x04  /* cmd: clear dma fifo          */
0714     #define   FM      0x02  /* mod: fetch pin mode              */
0715     #define   WRIE    0x01  /* mod: write and invalidate enable */
0716                 /* bits 4-7 rsvd for C1010          */
0717 
0718 /*1c*/  u32    nc_temp; /* ### Temporary stack              */
0719 
0720 /*20*/  u8  nc_dfifo;
0721 /*21*/  u8  nc_ctest4;
0722     #define   MUX     0x80  /* 720 host bus multiplex mode      */
0723     #define   BDIS    0x80  /* mod: burst disable               */
0724     #define   MPEE    0x08  /* mod: master parity error enable  */
0725 
0726 /*22*/  u8  nc_ctest5;
0727     #define   DFS     0x20  /* mod: dma fifo size               */
0728                 /* bits 0-1, 3-7 rsvd for C1010          */
0729 /*23*/  u8  nc_ctest6;
0730 
0731 /*24*/  u32    nc_dbc;  /* ### Byte count and command       */
0732 /*28*/  u32    nc_dnad; /* ### Next command register        */
0733 /*2c*/  u32    nc_dsp;  /* --> Script Pointer               */
0734 /*30*/  u32    nc_dsps; /* --> Script pointer save/opcode#2 */
0735 
0736 /*34*/  u8  nc_scratcha;  /* Temporary register a            */
0737 /*35*/  u8  nc_scratcha1;
0738 /*36*/  u8  nc_scratcha2;
0739 /*37*/  u8  nc_scratcha3;
0740 
0741 /*38*/  u8  nc_dmode;
0742     #define   BL_2    0x80  /* mod: burst length shift value +2 */
0743     #define   BL_1    0x40  /* mod: burst length shift value +1 */
0744     #define   ERL     0x08  /* mod: enable read line            */
0745     #define   ERMP    0x04  /* mod: enable read multiple        */
0746     #define   BOF     0x02  /* mod: burst op code fetch         */
0747 
0748 /*39*/  u8  nc_dien;
0749 /*3a*/  u8  nc_sbr;
0750 
0751 /*3b*/  u8  nc_dcntl;   /* --> Script execution control     */
0752     #define   CLSE    0x80  /* mod: cache line size enable      */
0753     #define   PFF     0x40  /* cmd: pre-fetch flush             */
0754     #define   PFEN    0x20  /* mod: pre-fetch enable            */
0755     #define   EA      0x20  /* mod: 720 enable-ack              */
0756     #define   SSM     0x10  /* mod: single step mode            */
0757     #define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
0758     #define   STD     0x04  /* cmd: start dma mode              */
0759     #define   IRQD    0x02  /* mod: irq disable                 */
0760     #define   NOCOM   0x01  /* cmd: protect sfbr while reselect */
0761                 /* bits 0-1 rsvd for C1010          */
0762 
0763 /*3c*/  u32 nc_adder;
0764 
0765 /*40*/  u16 nc_sien;    /* -->: interrupt enable            */
0766 /*42*/  u16 nc_sist;    /* <--: interrupt status            */
0767         #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
0768         #define   STO     0x0400/* sta: timeout (select)            */
0769         #define   GEN     0x0200/* sta: timeout (general)           */
0770         #define   HTH     0x0100/* sta: timeout (handshake)         */
0771         #define   MA      0x80  /* sta: phase mismatch              */
0772         #define   CMP     0x40  /* sta: arbitration complete        */
0773         #define   SEL     0x20  /* sta: selected by another device  */
0774         #define   RSL     0x10  /* sta: reselected by another device*/
0775         #define   SGE     0x08  /* sta: gross error (over/underflow)*/
0776         #define   UDC     0x04  /* sta: unexpected disconnect       */
0777         #define   RST     0x02  /* sta: scsi bus reset detected     */
0778         #define   PAR     0x01  /* sta: scsi parity error           */
0779 
0780 /*44*/  u8  nc_slpar;
0781 /*45*/  u8  nc_swide;
0782 /*46*/  u8  nc_macntl;
0783 /*47*/  u8  nc_gpcntl;
0784 /*48*/  u8  nc_stime0;    /* cmd: timeout for select&handshake*/
0785 /*49*/  u8  nc_stime1;    /* cmd: timeout user defined        */
0786 /*4a*/  u16   nc_respid;    /* sta: Reselect-IDs                */
0787 
0788 /*4c*/  u8  nc_stest0;
0789 
0790 /*4d*/  u8  nc_stest1;
0791     #define   SCLK    0x80  /* Use the PCI clock as SCSI clock  */
0792     #define   DBLEN   0x08  /* clock doubler running        */
0793     #define   DBLSEL  0x04  /* clock doubler selected       */
0794   
0795 
0796 /*4e*/  u8  nc_stest2;
0797     #define   ROF     0x40  /* reset scsi offset (after gross error!) */
0798     #define   DIF     0x20  /* 720 SCSI differential mode             */
0799     #define   EXT     0x02  /* extended filtering                     */
0800 
0801 /*4f*/  u8  nc_stest3;
0802     #define   TE     0x80   /* c: tolerAnt enable */
0803     #define   HSC    0x20   /* c: Halt SCSI Clock */
0804     #define   CSF    0x02   /* c: clear scsi fifo */
0805 
0806 /*50*/  u16   nc_sidl;  /* Lowlevel: latched from scsi data */
0807 /*52*/  u8  nc_stest4;
0808     #define   SMODE  0xc0   /* SCSI bus mode      (895/6 only) */
0809     #define    SMODE_HVD 0x40   /* High Voltage Differential       */
0810     #define    SMODE_SE  0x80   /* Single Ended                    */
0811     #define    SMODE_LVD 0xc0   /* Low Voltage Differential        */
0812     #define   LCKFRQ 0x20   /* Frequency Lock (895/6 only)     */
0813                 /* bits 0-5 rsvd for C1010          */
0814 
0815 /*53*/  u8  nc_53_;
0816 /*54*/  u16 nc_sodl;    /* Lowlevel: data out to scsi data  */
0817 /*56*/  u8  nc_ccntl0;  /* Chip Control 0 (896)             */
0818     #define   ENPMJ  0x80   /* Enable Phase Mismatch Jump       */
0819     #define   PMJCTL 0x40   /* Phase Mismatch Jump Control      */
0820     #define   ENNDJ  0x20   /* Enable Non Data PM Jump          */
0821     #define   DISFC  0x10   /* Disable Auto FIFO Clear          */
0822     #define   DILS   0x02   /* Disable Internal Load/Store      */
0823     #define   DPR    0x01   /* Disable Pipe Req                 */
0824 
0825 /*57*/  u8  nc_ccntl1;  /* Chip Control 1 (896)             */
0826     #define   ZMOD   0x80   /* High Impedance Mode              */
0827     #define   DIC    0x10   /* Disable Internal Cycles      */
0828     #define   DDAC   0x08   /* Disable Dual Address Cycle       */
0829     #define   XTIMOD 0x04   /* 64-bit Table Ind. Indexing Mode  */
0830     #define   EXTIBMV 0x02  /* Enable 64-bit Table Ind. BMOV    */
0831     #define   EXDBMV 0x01   /* Enable 64-bit Direct BMOV        */
0832 
0833 /*58*/  u16 nc_sbdl;    /* Lowlevel: data from scsi data    */
0834 /*5a*/  u16 nc_5a_;
0835 
0836 /*5c*/  u8  nc_scr0;    /* Working register B               */
0837 /*5d*/  u8  nc_scr1;    /*                                  */
0838 /*5e*/  u8  nc_scr2;    /*                                  */
0839 /*5f*/  u8  nc_scr3;    /*                                  */
0840 
0841 /*60*/  u8  nc_scrx[64];    /* Working register C-R             */
0842 /*a0*/  u32 nc_mmrs;    /* Memory Move Read Selector        */
0843 /*a4*/  u32 nc_mmws;    /* Memory Move Write Selector       */
0844 /*a8*/  u32 nc_sfs;     /* Script Fetch Selector            */
0845 /*ac*/  u32 nc_drs;     /* DSA Relative Selector            */
0846 /*b0*/  u32 nc_sbms;    /* Static Block Move Selector       */
0847 /*b4*/  u32 nc_dbms;    /* Dynamic Block Move Selector      */
0848 /*b8*/  u32 nc_dnad64;  /* DMA Next Address 64              */
0849 /*bc*/  u16 nc_scntl4;  /* C1010 only                       */
0850     #define   U3EN   0x80   /* Enable Ultra 3                   */
0851     #define   AIPEN  0x40   /* Allow check upper byte lanes     */
0852     #define   XCLKH_DT 0x08 /* Extra clock of data hold on DT
0853                     transfer edge               */
0854     #define   XCLKH_ST 0x04 /* Extra clock of data hold on ST
0855                     transfer edge               */
0856 
0857 /*be*/  u8  nc_aipcntl0;    /* Epat Control 1 C1010 only        */
0858 /*bf*/  u8  nc_aipcntl1;    /* AIP Control C1010_66 Only        */
0859 
0860 /*c0*/  u32 nc_pmjad1;  /* Phase Mismatch Jump Address 1    */
0861 /*c4*/  u32 nc_pmjad2;  /* Phase Mismatch Jump Address 2    */
0862 /*c8*/  u8  nc_rbc;     /* Remaining Byte Count             */
0863 /*c9*/  u8  nc_rbc1;    /*                                  */
0864 /*ca*/  u8  nc_rbc2;    /*                                  */
0865 /*cb*/  u8  nc_rbc3;    /*                                  */
0866 
0867 /*cc*/  u8  nc_ua;      /* Updated Address                  */
0868 /*cd*/  u8  nc_ua1;     /*                                  */
0869 /*ce*/  u8  nc_ua2;     /*                                  */
0870 /*cf*/  u8  nc_ua3;     /*                                  */
0871 /*d0*/  u32 nc_esa;     /* Entry Storage Address            */
0872 /*d4*/  u8  nc_ia;      /* Instruction Address              */
0873 /*d5*/  u8  nc_ia1;
0874 /*d6*/  u8  nc_ia2;
0875 /*d7*/  u8  nc_ia3;
0876 /*d8*/  u32 nc_sbc;     /* SCSI Byte Count (3 bytes only)   */
0877 /*dc*/  u32 nc_csbc;    /* Cumulative SCSI Byte Count       */
0878 
0879                 /* Following for C1010 only         */
0880 /*e0*/  u16 nc_crcpad;  /* CRC Value                        */
0881 /*e2*/  u8  nc_crccntl0;    /* CRC control register             */
0882     #define   SNDCRC  0x10  /* Send CRC Request                 */
0883 /*e3*/  u8  nc_crccntl1;    /* CRC control register             */
0884 /*e4*/  u32 nc_crcdata; /* CRC data register                */ 
0885 /*e8*/  u32 nc_e8_;     /* rsvd                 */
0886 /*ec*/  u32 nc_ec_;     /* rsvd                 */
0887 /*f0*/  u16 nc_dfbc;    /* DMA FIFO byte count              */ 
0888 
0889 };
0890 
0891 /*-----------------------------------------------------------
0892 **
0893 **  Utility macros for the script.
0894 **
0895 **-----------------------------------------------------------
0896 */
0897 
0898 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
0899 #define REG(r) REGJ (nc_, r)
0900 
0901 typedef u32 ncrcmd;
0902 
0903 /*-----------------------------------------------------------
0904 **
0905 **  SCSI phases
0906 **
0907 **  DT phases illegal for ncr driver.
0908 **
0909 **-----------------------------------------------------------
0910 */
0911 
0912 #define SCR_DATA_OUT    0x00000000
0913 #define SCR_DATA_IN 0x01000000
0914 #define SCR_COMMAND 0x02000000
0915 #define SCR_STATUS  0x03000000
0916 #define SCR_DT_DATA_OUT 0x04000000
0917 #define SCR_DT_DATA_IN  0x05000000
0918 #define SCR_MSG_OUT 0x06000000
0919 #define SCR_MSG_IN      0x07000000
0920 
0921 #define SCR_ILG_OUT 0x04000000
0922 #define SCR_ILG_IN  0x05000000
0923 
0924 /*-----------------------------------------------------------
0925 **
0926 **  Data transfer via SCSI.
0927 **
0928 **-----------------------------------------------------------
0929 **
0930 **  MOVE_ABS (LEN)
0931 **  <<start address>>
0932 **
0933 **  MOVE_IND (LEN)
0934 **  <<dnad_offset>>
0935 **
0936 **  MOVE_TBL
0937 **  <<dnad_offset>>
0938 **
0939 **-----------------------------------------------------------
0940 */
0941 
0942 #define OPC_MOVE          0x08000000
0943 
0944 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
0945 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
0946 #define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
0947 
0948 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
0949 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
0950 #define SCR_CHMOV_TBL     (0x10000000)
0951 
0952 struct scr_tblmove {
0953         u32  size;
0954         u32  addr;
0955 };
0956 
0957 /*-----------------------------------------------------------
0958 **
0959 **  Selection
0960 **
0961 **-----------------------------------------------------------
0962 **
0963 **  SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
0964 **  <<alternate_address>>
0965 **
0966 **  SEL_TBL | << dnad_offset>>  [ | REL_JMP]
0967 **  <<alternate_address>>
0968 **
0969 **-----------------------------------------------------------
0970 */
0971 
0972 #define SCR_SEL_ABS 0x40000000
0973 #define SCR_SEL_ABS_ATN 0x41000000
0974 #define SCR_SEL_TBL 0x42000000
0975 #define SCR_SEL_TBL_ATN 0x43000000
0976 
0977 
0978 #ifdef SCSI_NCR_BIG_ENDIAN
0979 struct scr_tblsel {
0980         u8  sel_scntl3;
0981         u8  sel_id;
0982         u8  sel_sxfer;
0983         u8  sel_scntl4; 
0984 };
0985 #else
0986 struct scr_tblsel {
0987         u8  sel_scntl4; 
0988         u8  sel_sxfer;
0989         u8  sel_id;
0990         u8  sel_scntl3;
0991 };
0992 #endif
0993 
0994 #define SCR_JMP_REL     0x04000000
0995 #define SCR_ID(id)  (((u32)(id)) << 16)
0996 
0997 /*-----------------------------------------------------------
0998 **
0999 **  Waiting for Disconnect or Reselect
1000 **
1001 **-----------------------------------------------------------
1002 **
1003 **  WAIT_DISC
1004 **  dummy: <<alternate_address>>
1005 **
1006 **  WAIT_RESEL
1007 **  <<alternate_address>>
1008 **
1009 **-----------------------------------------------------------
1010 */
1011 
1012 #define SCR_WAIT_DISC   0x48000000
1013 #define SCR_WAIT_RESEL  0x50000000
1014 
1015 /*-----------------------------------------------------------
1016 **
1017 **  Bit Set / Reset
1018 **
1019 **-----------------------------------------------------------
1020 **
1021 **  SET (flags {|.. })
1022 **
1023 **  CLR (flags {|.. })
1024 **
1025 **-----------------------------------------------------------
1026 */
1027 
1028 #define SCR_SET(f)     (0x58000000 | (f))
1029 #define SCR_CLR(f)     (0x60000000 | (f))
1030 
1031 #define SCR_CARRY   0x00000400
1032 #define SCR_TRG     0x00000200
1033 #define SCR_ACK     0x00000040
1034 #define SCR_ATN     0x00000008
1035 
1036 
1037 
1038 
1039 /*-----------------------------------------------------------
1040 **
1041 **  Memory to memory move
1042 **
1043 **-----------------------------------------------------------
1044 **
1045 **  COPY (bytecount)
1046 **  << source_address >>
1047 **  << destination_address >>
1048 **
1049 **  SCR_COPY   sets the NO FLUSH option by default.
1050 **  SCR_COPY_F does not set this option.
1051 **
1052 **  For chips which do not support this option,
1053 **  ncr_copy_and_bind() will remove this bit.
1054 **-----------------------------------------------------------
1055 */
1056 
1057 #define SCR_NO_FLUSH 0x01000000
1058 
1059 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1060 #define SCR_COPY_F(n) (0xc0000000 | (n))
1061 
1062 /*-----------------------------------------------------------
1063 **
1064 **  Register move and binary operations
1065 **
1066 **-----------------------------------------------------------
1067 **
1068 **  SFBR_REG (reg, op, data)        reg  = SFBR op data
1069 **  << 0 >>
1070 **
1071 **  REG_SFBR (reg, op, data)        SFBR = reg op data
1072 **  << 0 >>
1073 **
1074 **  REG_REG  (reg, op, data)        reg  = reg op data
1075 **  << 0 >>
1076 **
1077 **-----------------------------------------------------------
1078 **  On 810A, 860, 825A, 875, 895 and 896 chips the content 
1079 **  of SFBR register can be used as data (SCR_SFBR_DATA).
1080 **  The 896 has additional IO registers starting at 
1081 **  offset 0x80. Bit 7 of register offset is stored in 
1082 **  bit 7 of the SCRIPTS instruction first DWORD.
1083 **-----------------------------------------------------------
1084 */
1085 
1086 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80)) 
1087 
1088 #define SCR_SFBR_REG(reg,op,data) \
1089         (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1090 
1091 #define SCR_REG_SFBR(reg,op,data) \
1092         (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1093 
1094 #define SCR_REG_REG(reg,op,data) \
1095         (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1096 
1097 
1098 #define      SCR_LOAD   0x00000000
1099 #define      SCR_SHL    0x01000000
1100 #define      SCR_OR     0x02000000
1101 #define      SCR_XOR    0x03000000
1102 #define      SCR_AND    0x04000000
1103 #define      SCR_SHR    0x05000000
1104 #define      SCR_ADD    0x06000000
1105 #define      SCR_ADDC   0x07000000
1106 
1107 #define      SCR_SFBR_DATA   (0x00800000>>8ul)  /* Use SFBR as data */
1108 
1109 /*-----------------------------------------------------------
1110 **
1111 **  FROM_REG (reg)        SFBR = reg
1112 **  << 0 >>
1113 **
1114 **  TO_REG   (reg)        reg  = SFBR
1115 **  << 0 >>
1116 **
1117 **  LOAD_REG (reg, data)      reg  = <data>
1118 **  << 0 >>
1119 **
1120 **  LOAD_SFBR(data)       SFBR = <data>
1121 **  << 0 >>
1122 **
1123 **-----------------------------------------------------------
1124 */
1125 
1126 #define SCR_FROM_REG(reg) \
1127     SCR_REG_SFBR(reg,SCR_OR,0)
1128 
1129 #define SCR_TO_REG(reg) \
1130     SCR_SFBR_REG(reg,SCR_OR,0)
1131 
1132 #define SCR_LOAD_REG(reg,data) \
1133     SCR_REG_REG(reg,SCR_LOAD,data)
1134 
1135 #define SCR_LOAD_SFBR(data) \
1136         (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1137 
1138 /*-----------------------------------------------------------
1139 **
1140 **  LOAD  from memory   to register.
1141 **  STORE from register to memory.
1142 **
1143 **  Only supported by 810A, 860, 825A, 875, 895 and 896.
1144 **
1145 **-----------------------------------------------------------
1146 **
1147 **  LOAD_ABS (LEN)
1148 **  <<start address>>
1149 **
1150 **  LOAD_REL (LEN)        (DSA relative)
1151 **  <<dsa_offset>>
1152 **
1153 **-----------------------------------------------------------
1154 */
1155 
1156 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1157 #define SCR_NO_FLUSH2   0x02000000
1158 #define SCR_DSA_REL2    0x10000000
1159 
1160 #define SCR_LOAD_R(reg, how, n) \
1161         (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1162 
1163 #define SCR_STORE_R(reg, how, n) \
1164         (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1165 
1166 #define SCR_LOAD_ABS(reg, n)    SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1167 #define SCR_LOAD_REL(reg, n)    SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1168 #define SCR_LOAD_ABS_F(reg, n)  SCR_LOAD_R(reg, 0, n)
1169 #define SCR_LOAD_REL_F(reg, n)  SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1170 
1171 #define SCR_STORE_ABS(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1172 #define SCR_STORE_REL(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1173 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1174 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1175 
1176 
1177 /*-----------------------------------------------------------
1178 **
1179 **  Waiting for Disconnect or Reselect
1180 **
1181 **-----------------------------------------------------------
1182 **
1183 **  JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
1184 **  <<address>>
1185 **
1186 **  JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
1187 **  <<distance>>
1188 **
1189 **  CALL            [ | IFTRUE/IFFALSE ( ... ) ]
1190 **  <<address>>
1191 **
1192 **  CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
1193 **  <<distance>>
1194 **
1195 **  RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
1196 **  <<dummy>>
1197 **
1198 **  INT             [ | IFTRUE/IFFALSE ( ... ) ]
1199 **  <<ident>>
1200 **
1201 **  INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
1202 **  <<ident>>
1203 **
1204 **  Conditions:
1205 **       WHEN (phase)
1206 **       IF   (phase)
1207 **       CARRYSET
1208 **       DATA (data, mask)
1209 **
1210 **-----------------------------------------------------------
1211 */
1212 
1213 #define SCR_NO_OP       0x80000000
1214 #define SCR_JUMP        0x80080000
1215 #define SCR_JUMP64      0x80480000
1216 #define SCR_JUMPR       0x80880000
1217 #define SCR_CALL        0x88080000
1218 #define SCR_CALLR       0x88880000
1219 #define SCR_RETURN      0x90080000
1220 #define SCR_INT         0x98080000
1221 #define SCR_INT_FLY     0x98180000
1222 
1223 #define IFFALSE(arg)   (0x00080000 | (arg))
1224 #define IFTRUE(arg)    (0x00000000 | (arg))
1225 
1226 #define WHEN(phase)    (0x00030000 | (phase))
1227 #define IF(phase)      (0x00020000 | (phase))
1228 
1229 #define DATA(D)        (0x00040000 | ((D) & 0xff))
1230 #define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1231 
1232 #define CARRYSET       (0x00200000)
1233 
1234 /*-----------------------------------------------------------
1235 **
1236 **  SCSI  constants.
1237 **
1238 **-----------------------------------------------------------
1239 */
1240 
1241 /*
1242  * End of ncrreg from FreeBSD
1243  */
1244 
1245 /*
1246     Build a scatter/gather entry.
1247     see sym53c8xx_2/sym_hipd.h for more detailed sym_build_sge()
1248     implementation ;)
1249  */
1250 
1251 #define ncr_build_sge(np, data, badd, len)  \
1252 do {                        \
1253     (data)->addr = cpu_to_scr(badd);    \
1254     (data)->size = cpu_to_scr(len);     \
1255 } while (0)
1256 
1257 /*==========================================================
1258 **
1259 **  Structures used by the detection routine to transmit 
1260 **  device configuration to the attach function.
1261 **
1262 **==========================================================
1263 */
1264 struct ncr_slot {
1265     u_long  base;
1266     u_long  base_2;
1267     u_long  base_c;
1268     u_long  base_2_c;
1269     void __iomem *base_v;
1270     void __iomem *base_2_v;
1271     int irq;
1272 /* port and reg fields to use INB, OUTB macros */
1273     volatile struct ncr_reg __iomem *reg;
1274 };
1275 
1276 /*==========================================================
1277 **
1278 **  Structure used by detection routine to save data on 
1279 **  each detected board for attach.
1280 **
1281 **==========================================================
1282 */
1283 struct ncr_device {
1284     struct device  *dev;
1285     struct ncr_slot  slot;
1286     struct ncr_chip  chip;
1287     u_char host_id;
1288     u8 differential;
1289 };
1290 
1291 /* To keep track of the dma mapping (sg/single) that has been set */
1292 struct ncr_cmd_priv {
1293     int data_mapped;
1294     int data_mapping;
1295 };
1296 
1297 extern struct Scsi_Host *ncr_attach(struct scsi_host_template *tpnt, int unit, struct ncr_device *device);
1298 extern void ncr53c8xx_release(struct Scsi_Host *host);
1299 irqreturn_t ncr53c8xx_intr(int irq, void *dev_id);
1300 extern int ncr53c8xx_init(void);
1301 extern void ncr53c8xx_exit(void);
1302 
1303 #endif /* NCR53C8XX_H */
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