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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
0004  *
0005  * This driver supports the newer, SCSI-based firmware interface only.
0006  *
0007  * Copyright 2018 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
0008  *
0009  * Based on the original DAC960 driver, which has
0010  * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
0011  * Portions Copyright 2002 by Mylex (An IBM Business Unit)
0012  */
0013 
0014 #ifndef _MYRS_H
0015 #define _MYRS_H
0016 
0017 #define MYRS_MAILBOX_TIMEOUT 1000000
0018 
0019 #define MYRS_DCMD_TAG 1
0020 #define MYRS_MCMD_TAG 2
0021 
0022 #define MYRS_LINE_BUFFER_SIZE 128
0023 
0024 #define MYRS_PRIMARY_MONITOR_INTERVAL (10 * HZ)
0025 #define MYRS_SECONDARY_MONITOR_INTERVAL (60 * HZ)
0026 
0027 /* Maximum number of Scatter/Gather Segments supported */
0028 #define MYRS_SG_LIMIT       128
0029 
0030 /*
0031  * Number of Command and Status Mailboxes used by the
0032  * DAC960 V2 Firmware Memory Mailbox Interface.
0033  */
0034 #define MYRS_MAX_CMD_MBOX       512
0035 #define MYRS_MAX_STAT_MBOX      512
0036 
0037 #define MYRS_DCDB_SIZE          16
0038 #define MYRS_SENSE_SIZE         14
0039 
0040 /*
0041  * DAC960 V2 Firmware Command Opcodes.
0042  */
0043 enum myrs_cmd_opcode {
0044     MYRS_CMD_OP_MEMCOPY     = 0x01,
0045     MYRS_CMD_OP_SCSI_10_PASSTHRU    = 0x02,
0046     MYRS_CMD_OP_SCSI_255_PASSTHRU   = 0x03,
0047     MYRS_CMD_OP_SCSI_10     = 0x04,
0048     MYRS_CMD_OP_SCSI_256        = 0x05,
0049     MYRS_CMD_OP_IOCTL       = 0x20,
0050 } __packed;
0051 
0052 /*
0053  * DAC960 V2 Firmware IOCTL Opcodes.
0054  */
0055 enum myrs_ioctl_opcode {
0056     MYRS_IOCTL_GET_CTLR_INFO    = 0x01,
0057     MYRS_IOCTL_GET_LDEV_INFO_VALID  = 0x03,
0058     MYRS_IOCTL_GET_PDEV_INFO_VALID  = 0x05,
0059     MYRS_IOCTL_GET_HEALTH_STATUS    = 0x11,
0060     MYRS_IOCTL_GET_EVENT        = 0x15,
0061     MYRS_IOCTL_START_DISCOVERY  = 0x81,
0062     MYRS_IOCTL_SET_DEVICE_STATE = 0x82,
0063     MYRS_IOCTL_INIT_PDEV_START  = 0x84,
0064     MYRS_IOCTL_INIT_PDEV_STOP   = 0x85,
0065     MYRS_IOCTL_INIT_LDEV_START  = 0x86,
0066     MYRS_IOCTL_INIT_LDEV_STOP   = 0x87,
0067     MYRS_IOCTL_RBLD_DEVICE_START    = 0x88,
0068     MYRS_IOCTL_RBLD_DEVICE_STOP = 0x89,
0069     MYRS_IOCTL_MAKE_CONSISTENT_START = 0x8A,
0070     MYRS_IOCTL_MAKE_CONSISTENT_STOP = 0x8B,
0071     MYRS_IOCTL_CC_START     = 0x8C,
0072     MYRS_IOCTL_CC_STOP      = 0x8D,
0073     MYRS_IOCTL_SET_MEM_MBOX     = 0x8E,
0074     MYRS_IOCTL_RESET_DEVICE     = 0x90,
0075     MYRS_IOCTL_FLUSH_DEVICE_DATA    = 0x91,
0076     MYRS_IOCTL_PAUSE_DEVICE     = 0x92,
0077     MYRS_IOCTL_UNPAUS_EDEVICE   = 0x93,
0078     MYRS_IOCTL_LOCATE_DEVICE    = 0x94,
0079     MYRS_IOCTL_CREATE_CONFIGURATION = 0xC0,
0080     MYRS_IOCTL_DELETE_LDEV      = 0xC1,
0081     MYRS_IOCTL_REPLACE_INTERNALDEVICE = 0xC2,
0082     MYRS_IOCTL_RENAME_LDEV      = 0xC3,
0083     MYRS_IOCTL_ADD_CONFIGURATION    = 0xC4,
0084     MYRS_IOCTL_XLATE_PDEV_TO_LDEV   = 0xC5,
0085     MYRS_IOCTL_CLEAR_CONFIGURATION  = 0xCA,
0086 } __packed;
0087 
0088 /*
0089  * DAC960 V2 Firmware Command Status Codes.
0090  */
0091 #define MYRS_STATUS_SUCCESS         0x00
0092 #define MYRS_STATUS_FAILED          0x02
0093 #define MYRS_STATUS_DEVICE_BUSY         0x08
0094 #define MYRS_STATUS_DEVICE_NON_RESPONSIVE   0x0E
0095 #define MYRS_STATUS_DEVICE_NON_RESPONSIVE2  0x0F
0096 #define MYRS_STATUS_RESERVATION_CONFLICT    0x18
0097 
0098 /*
0099  * DAC960 V2 Firmware Memory Type structure.
0100  */
0101 struct myrs_mem_type {
0102     enum {
0103         MYRS_MEMTYPE_RESERVED   = 0x00,
0104         MYRS_MEMTYPE_DRAM   = 0x01,
0105         MYRS_MEMTYPE_EDRAM  = 0x02,
0106         MYRS_MEMTYPE_EDO    = 0x03,
0107         MYRS_MEMTYPE_SDRAM  = 0x04,
0108         MYRS_MEMTYPE_LAST   = 0x1F,
0109     } __packed mem_type:5;  /* Byte 0 Bits 0-4 */
0110     unsigned rsvd:1;            /* Byte 0 Bit 5 */
0111     unsigned mem_parity:1;          /* Byte 0 Bit 6 */
0112     unsigned mem_ecc:1;         /* Byte 0 Bit 7 */
0113 };
0114 
0115 /*
0116  * DAC960 V2 Firmware Processor Type structure.
0117  */
0118 enum myrs_cpu_type {
0119     MYRS_CPUTYPE_i960CA = 0x01,
0120     MYRS_CPUTYPE_i960RD = 0x02,
0121     MYRS_CPUTYPE_i960RN = 0x03,
0122     MYRS_CPUTYPE_i960RP = 0x04,
0123     MYRS_CPUTYPE_NorthBay   = 0x05,
0124     MYRS_CPUTYPE_StrongArm  = 0x06,
0125     MYRS_CPUTYPE_i960RM = 0x07,
0126 } __packed;
0127 
0128 /*
0129  * DAC960 V2 Firmware Get Controller Info reply structure.
0130  */
0131 struct myrs_ctlr_info {
0132     unsigned char rsvd1;                /* Byte 0 */
0133     enum {
0134         MYRS_SCSI_BUS   = 0x00,
0135         MYRS_Fibre_BUS  = 0x01,
0136         MYRS_PCI_BUS    = 0x03
0137     } __packed bus; /* Byte 1 */
0138     enum {
0139         MYRS_CTLR_DAC960E   = 0x01,
0140         MYRS_CTLR_DAC960M   = 0x08,
0141         MYRS_CTLR_DAC960PD  = 0x10,
0142         MYRS_CTLR_DAC960PL  = 0x11,
0143         MYRS_CTLR_DAC960PU  = 0x12,
0144         MYRS_CTLR_DAC960PE  = 0x13,
0145         MYRS_CTLR_DAC960PG  = 0x14,
0146         MYRS_CTLR_DAC960PJ  = 0x15,
0147         MYRS_CTLR_DAC960PTL0    = 0x16,
0148         MYRS_CTLR_DAC960PR  = 0x17,
0149         MYRS_CTLR_DAC960PRL = 0x18,
0150         MYRS_CTLR_DAC960PT  = 0x19,
0151         MYRS_CTLR_DAC1164P  = 0x1A,
0152         MYRS_CTLR_DAC960PTL1    = 0x1B,
0153         MYRS_CTLR_EXR2000P  = 0x1C,
0154         MYRS_CTLR_EXR3000P  = 0x1D,
0155         MYRS_CTLR_ACCELERAID352 = 0x1E,
0156         MYRS_CTLR_ACCELERAID170 = 0x1F,
0157         MYRS_CTLR_ACCELERAID160 = 0x20,
0158         MYRS_CTLR_DAC960S   = 0x60,
0159         MYRS_CTLR_DAC960SU  = 0x61,
0160         MYRS_CTLR_DAC960SX  = 0x62,
0161         MYRS_CTLR_DAC960SF  = 0x63,
0162         MYRS_CTLR_DAC960SS  = 0x64,
0163         MYRS_CTLR_DAC960FL  = 0x65,
0164         MYRS_CTLR_DAC960LL  = 0x66,
0165         MYRS_CTLR_DAC960FF  = 0x67,
0166         MYRS_CTLR_DAC960HP  = 0x68,
0167         MYRS_CTLR_RAIDBRICK = 0x69,
0168         MYRS_CTLR_METEOR_FL = 0x6A,
0169         MYRS_CTLR_METEOR_FF = 0x6B
0170     } __packed ctlr_type;   /* Byte 2 */
0171     unsigned char rsvd2;            /* Byte 3 */
0172     unsigned short bus_speed_mhz;       /* Bytes 4-5 */
0173     unsigned char bus_width;        /* Byte 6 */
0174     unsigned char flash_code;       /* Byte 7 */
0175     unsigned char ports_present;        /* Byte 8 */
0176     unsigned char rsvd3[7];         /* Bytes 9-15 */
0177     unsigned char bus_name[16];     /* Bytes 16-31 */
0178     unsigned char ctlr_name[16];        /* Bytes 32-47 */
0179     unsigned char rsvd4[16];        /* Bytes 48-63 */
0180     /* Firmware Release Information */
0181     unsigned char fw_major_version;     /* Byte 64 */
0182     unsigned char fw_minor_version;     /* Byte 65 */
0183     unsigned char fw_turn_number;       /* Byte 66 */
0184     unsigned char fw_build_number;      /* Byte 67 */
0185     unsigned char fw_release_day;       /* Byte 68 */
0186     unsigned char fw_release_month;     /* Byte 69 */
0187     unsigned char fw_release_year_hi;   /* Byte 70 */
0188     unsigned char fw_release_year_lo;   /* Byte 71 */
0189     /* Hardware Release Information */
0190     unsigned char hw_rev;           /* Byte 72 */
0191     unsigned char rsvd5[3];         /* Bytes 73-75 */
0192     unsigned char hw_release_day;       /* Byte 76 */
0193     unsigned char hw_release_month;     /* Byte 77 */
0194     unsigned char hw_release_year_hi;   /* Byte 78 */
0195     unsigned char hw_release_year_lo;   /* Byte 79 */
0196     /* Hardware Manufacturing Information */
0197     unsigned char manuf_batch_num;      /* Byte 80 */
0198     unsigned char rsvd6;            /* Byte 81 */
0199     unsigned char manuf_plant_num;      /* Byte 82 */
0200     unsigned char rsvd7;            /* Byte 83 */
0201     unsigned char hw_manuf_day;     /* Byte 84 */
0202     unsigned char hw_manuf_month;       /* Byte 85 */
0203     unsigned char hw_manuf_year_hi;     /* Byte 86 */
0204     unsigned char hw_manuf_year_lo;     /* Byte 87 */
0205     unsigned char max_pd_per_xld;       /* Byte 88 */
0206     unsigned char max_ild_per_xld;      /* Byte 89 */
0207     unsigned short nvram_size_kb;       /* Bytes 90-91 */
0208     unsigned char max_xld;          /* Byte 92 */
0209     unsigned char rsvd8[3];         /* Bytes 93-95 */
0210     /* Unique Information per Controller */
0211     unsigned char serial_number[16];    /* Bytes 96-111 */
0212     unsigned char rsvd9[16];        /* Bytes 112-127 */
0213     /* Vendor Information */
0214     unsigned char rsvd10[3];        /* Bytes 128-130 */
0215     unsigned char oem_code;         /* Byte 131 */
0216     unsigned char vendor[16];       /* Bytes 132-147 */
0217     /* Other Physical/Controller/Operation Information */
0218     unsigned char bbu_present:1;        /* Byte 148 Bit 0 */
0219     unsigned char cluster_mode:1;       /* Byte 148 Bit 1 */
0220     unsigned char rsvd11:6;         /* Byte 148 Bits 2-7 */
0221     unsigned char rsvd12[3];        /* Bytes 149-151 */
0222     /* Physical Device Scan Information */
0223     unsigned char pscan_active:1;       /* Byte 152 Bit 0 */
0224     unsigned char rsvd13:7;         /* Byte 152 Bits 1-7 */
0225     unsigned char pscan_chan;       /* Byte 153 */
0226     unsigned char pscan_target;     /* Byte 154 */
0227     unsigned char pscan_lun;        /* Byte 155 */
0228     /* Maximum Command Data Transfer Sizes */
0229     unsigned short max_transfer_size;   /* Bytes 156-157 */
0230     unsigned short max_sge;         /* Bytes 158-159 */
0231     /* Logical/Physical Device Counts */
0232     unsigned short ldev_present;        /* Bytes 160-161 */
0233     unsigned short ldev_critical;       /* Bytes 162-163 */
0234     unsigned short ldev_offline;        /* Bytes 164-165 */
0235     unsigned short pdev_present;        /* Bytes 166-167 */
0236     unsigned short pdisk_present;       /* Bytes 168-169 */
0237     unsigned short pdisk_critical;      /* Bytes 170-171 */
0238     unsigned short pdisk_offline;       /* Bytes 172-173 */
0239     unsigned short max_tcq;         /* Bytes 174-175 */
0240     /* Channel and Target ID Information */
0241     unsigned char physchan_present;     /* Byte 176 */
0242     unsigned char virtchan_present;     /* Byte 177 */
0243     unsigned char physchan_max;     /* Byte 178 */
0244     unsigned char virtchan_max;     /* Byte 179 */
0245     unsigned char max_targets[16];      /* Bytes 180-195 */
0246     unsigned char rsvd14[12];       /* Bytes 196-207 */
0247     /* Memory/Cache Information */
0248     unsigned short mem_size_mb;     /* Bytes 208-209 */
0249     unsigned short cache_size_mb;       /* Bytes 210-211 */
0250     unsigned int valid_cache_bytes;     /* Bytes 212-215 */
0251     unsigned int dirty_cache_bytes;     /* Bytes 216-219 */
0252     unsigned short mem_speed_mhz;       /* Bytes 220-221 */
0253     unsigned char mem_data_width;       /* Byte 222 */
0254     struct myrs_mem_type mem_type;      /* Byte 223 */
0255     unsigned char cache_mem_type_name[16];  /* Bytes 224-239 */
0256     /* Execution Memory Information */
0257     unsigned short exec_mem_size_mb;    /* Bytes 240-241 */
0258     unsigned short exec_l2_cache_size_mb;   /* Bytes 242-243 */
0259     unsigned char rsvd15[8];        /* Bytes 244-251 */
0260     unsigned short exec_mem_speed_mhz;  /* Bytes 252-253 */
0261     unsigned char exec_mem_data_width;  /* Byte 254 */
0262     struct myrs_mem_type exec_mem_type; /* Byte 255 */
0263     unsigned char exec_mem_type_name[16];   /* Bytes 256-271 */
0264     /* CPU Type Information */
0265     struct {                /* Bytes 272-335 */
0266         unsigned short cpu_speed_mhz;
0267         enum myrs_cpu_type cpu_type;
0268         unsigned char cpu_count;
0269         unsigned char rsvd16[12];
0270         unsigned char cpu_name[16];
0271     } __packed cpu[2];
0272     /* Debugging/Profiling/Command Time Tracing Information */
0273     unsigned short cur_prof_page_num;   /* Bytes 336-337 */
0274     unsigned short num_prof_waiters;    /* Bytes 338-339 */
0275     unsigned short cur_trace_page_num;  /* Bytes 340-341 */
0276     unsigned short num_trace_waiters;   /* Bytes 342-343 */
0277     unsigned char rsvd18[8];        /* Bytes 344-351 */
0278     /* Error Counters on Physical Devices */
0279     unsigned short pdev_bus_resets;     /* Bytes 352-353 */
0280     unsigned short pdev_parity_errors;  /* Bytes 355-355 */
0281     unsigned short pdev_soft_errors;    /* Bytes 356-357 */
0282     unsigned short pdev_cmds_failed;    /* Bytes 358-359 */
0283     unsigned short pdev_misc_errors;    /* Bytes 360-361 */
0284     unsigned short pdev_cmd_timeouts;   /* Bytes 362-363 */
0285     unsigned short pdev_sel_timeouts;   /* Bytes 364-365 */
0286     unsigned short pdev_retries_done;   /* Bytes 366-367 */
0287     unsigned short pdev_aborts_done;    /* Bytes 368-369 */
0288     unsigned short pdev_host_aborts_done;   /* Bytes 370-371 */
0289     unsigned short pdev_predicted_failures; /* Bytes 372-373 */
0290     unsigned short pdev_host_cmds_failed;   /* Bytes 374-375 */
0291     unsigned short pdev_hard_errors;    /* Bytes 376-377 */
0292     unsigned char rsvd19[6];        /* Bytes 378-383 */
0293     /* Error Counters on Logical Devices */
0294     unsigned short ldev_soft_errors;    /* Bytes 384-385 */
0295     unsigned short ldev_cmds_failed;    /* Bytes 386-387 */
0296     unsigned short ldev_host_aborts_done;   /* Bytes 388-389 */
0297     unsigned char rsvd20[2];        /* Bytes 390-391 */
0298     /* Error Counters on Controller */
0299     unsigned short ctlr_mem_errors;     /* Bytes 392-393 */
0300     unsigned short ctlr_host_aborts_done;   /* Bytes 394-395 */
0301     unsigned char rsvd21[4];        /* Bytes 396-399 */
0302     /* Long Duration Activity Information */
0303     unsigned short bg_init_active;      /* Bytes 400-401 */
0304     unsigned short ldev_init_active;    /* Bytes 402-403 */
0305     unsigned short pdev_init_active;    /* Bytes 404-405 */
0306     unsigned short cc_active;       /* Bytes 406-407 */
0307     unsigned short rbld_active;     /* Bytes 408-409 */
0308     unsigned short exp_active;      /* Bytes 410-411 */
0309     unsigned short patrol_active;       /* Bytes 412-413 */
0310     unsigned char rsvd22[2];        /* Bytes 414-415 */
0311     /* Flash ROM Information */
0312     unsigned char flash_type;       /* Byte 416 */
0313     unsigned char rsvd23;           /* Byte 417 */
0314     unsigned short flash_size_MB;       /* Bytes 418-419 */
0315     unsigned int flash_limit;       /* Bytes 420-423 */
0316     unsigned int flash_count;       /* Bytes 424-427 */
0317     unsigned char rsvd24[4];        /* Bytes 428-431 */
0318     unsigned char flash_type_name[16];  /* Bytes 432-447 */
0319     /* Firmware Run Time Information */
0320     unsigned char rbld_rate;        /* Byte 448 */
0321     unsigned char bg_init_rate;     /* Byte 449 */
0322     unsigned char fg_init_rate;     /* Byte 450 */
0323     unsigned char cc_rate;          /* Byte 451 */
0324     unsigned char rsvd25[4];        /* Bytes 452-455 */
0325     unsigned int max_dp;            /* Bytes 456-459 */
0326     unsigned int free_dp;           /* Bytes 460-463 */
0327     unsigned int max_iop;           /* Bytes 464-467 */
0328     unsigned int free_iop;          /* Bytes 468-471 */
0329     unsigned short max_combined_len;    /* Bytes 472-473 */
0330     unsigned short num_cfg_groups;      /* Bytes 474-475 */
0331     unsigned installation_abort_status:1;   /* Byte 476 Bit 0 */
0332     unsigned maint_mode_status:1;       /* Byte 476 Bit 1 */
0333     unsigned rsvd26:6;          /* Byte 476 Bits 2-7 */
0334     unsigned char rsvd27[6];        /* Bytes 477-511 */
0335     unsigned char rsvd28[512];      /* Bytes 512-1023 */
0336 };
0337 
0338 /*
0339  * DAC960 V2 Firmware Device State type.
0340  */
0341 enum myrs_devstate {
0342     MYRS_DEVICE_UNCONFIGURED    = 0x00,
0343     MYRS_DEVICE_ONLINE      = 0x01,
0344     MYRS_DEVICE_REBUILD     = 0x03,
0345     MYRS_DEVICE_MISSING     = 0x04,
0346     MYRS_DEVICE_SUSPECTED_CRITICAL  = 0x05,
0347     MYRS_DEVICE_OFFLINE     = 0x08,
0348     MYRS_DEVICE_CRITICAL        = 0x09,
0349     MYRS_DEVICE_SUSPECTED_DEAD  = 0x0C,
0350     MYRS_DEVICE_COMMANDED_OFFLINE   = 0x10,
0351     MYRS_DEVICE_STANDBY     = 0x21,
0352     MYRS_DEVICE_INVALID_STATE   = 0xFF,
0353 } __packed;
0354 
0355 /*
0356  * DAC960 V2 RAID Levels
0357  */
0358 enum myrs_raid_level {
0359     MYRS_RAID_LEVEL0    = 0x0,     /* RAID 0 */
0360     MYRS_RAID_LEVEL1    = 0x1,     /* RAID 1 */
0361     MYRS_RAID_LEVEL3    = 0x3,     /* RAID 3 right asymmetric parity */
0362     MYRS_RAID_LEVEL5    = 0x5,     /* RAID 5 right asymmetric parity */
0363     MYRS_RAID_LEVEL6    = 0x6,     /* RAID 6 (Mylex RAID 6) */
0364     MYRS_RAID_JBOD      = 0x7,     /* RAID 7 (JBOD) */
0365     MYRS_RAID_NEWSPAN   = 0x8,     /* New Mylex SPAN */
0366     MYRS_RAID_LEVEL3F   = 0x9,     /* RAID 3 fixed parity */
0367     MYRS_RAID_LEVEL3L   = 0xb,     /* RAID 3 left symmetric parity */
0368     MYRS_RAID_SPAN      = 0xc,     /* current spanning implementation */
0369     MYRS_RAID_LEVEL5L   = 0xd,     /* RAID 5 left symmetric parity */
0370     MYRS_RAID_LEVELE    = 0xe,     /* RAID E (concatenation) */
0371     MYRS_RAID_PHYSICAL  = 0xf,     /* physical device */
0372 } __packed;
0373 
0374 enum myrs_stripe_size {
0375     MYRS_STRIPE_SIZE_0  = 0x0,  /* no stripe (RAID 1, RAID 7, etc) */
0376     MYRS_STRIPE_SIZE_512B   = 0x1,
0377     MYRS_STRIPE_SIZE_1K = 0x2,
0378     MYRS_STRIPE_SIZE_2K = 0x3,
0379     MYRS_STRIPE_SIZE_4K = 0x4,
0380     MYRS_STRIPE_SIZE_8K = 0x5,
0381     MYRS_STRIPE_SIZE_16K    = 0x6,
0382     MYRS_STRIPE_SIZE_32K    = 0x7,
0383     MYRS_STRIPE_SIZE_64K    = 0x8,
0384     MYRS_STRIPE_SIZE_128K   = 0x9,
0385     MYRS_STRIPE_SIZE_256K   = 0xa,
0386     MYRS_STRIPE_SIZE_512K   = 0xb,
0387     MYRS_STRIPE_SIZE_1M = 0xc,
0388 } __packed;
0389 
0390 enum myrs_cacheline_size {
0391     MYRS_CACHELINE_ZERO = 0x0,  /* caching cannot be enabled */
0392     MYRS_CACHELINE_512B = 0x1,
0393     MYRS_CACHELINE_1K   = 0x2,
0394     MYRS_CACHELINE_2K   = 0x3,
0395     MYRS_CACHELINE_4K   = 0x4,
0396     MYRS_CACHELINE_8K   = 0x5,
0397     MYRS_CACHELINE_16K  = 0x6,
0398     MYRS_CACHELINE_32K  = 0x7,
0399     MYRS_CACHELINE_64K  = 0x8,
0400 } __packed;
0401 
0402 /*
0403  * DAC960 V2 Firmware Get Logical Device Info reply structure.
0404  */
0405 struct myrs_ldev_info {
0406     unsigned char ctlr;         /* Byte 0 */
0407     unsigned char channel;          /* Byte 1 */
0408     unsigned char target;           /* Byte 2 */
0409     unsigned char lun;          /* Byte 3 */
0410     enum myrs_devstate dev_state;       /* Byte 4 */
0411     unsigned char raid_level;       /* Byte 5 */
0412     enum myrs_stripe_size stripe_size;  /* Byte 6 */
0413     enum myrs_cacheline_size cacheline_size; /* Byte 7 */
0414     struct {
0415         enum {
0416             MYRS_READCACHE_DISABLED     = 0x0,
0417             MYRS_READCACHE_ENABLED      = 0x1,
0418             MYRS_READAHEAD_ENABLED      = 0x2,
0419             MYRS_INTELLIGENT_READAHEAD_ENABLED = 0x3,
0420             MYRS_READCACHE_LAST     = 0x7,
0421         } __packed rce:3; /* Byte 8 Bits 0-2 */
0422         enum {
0423             MYRS_WRITECACHE_DISABLED    = 0x0,
0424             MYRS_LOGICALDEVICE_RO       = 0x1,
0425             MYRS_WRITECACHE_ENABLED     = 0x2,
0426             MYRS_INTELLIGENT_WRITECACHE_ENABLED = 0x3,
0427             MYRS_WRITECACHE_LAST        = 0x7,
0428         } __packed wce:3; /* Byte 8 Bits 3-5 */
0429         unsigned rsvd1:1;       /* Byte 8 Bit 6 */
0430         unsigned ldev_init_done:1;  /* Byte 8 Bit 7 */
0431     } ldev_control;             /* Byte 8 */
0432     /* Logical Device Operations Status */
0433     unsigned char cc_active:1;      /* Byte 9 Bit 0 */
0434     unsigned char rbld_active:1;        /* Byte 9 Bit 1 */
0435     unsigned char bg_init_active:1;     /* Byte 9 Bit 2 */
0436     unsigned char fg_init_active:1;     /* Byte 9 Bit 3 */
0437     unsigned char migration_active:1;   /* Byte 9 Bit 4 */
0438     unsigned char patrol_active:1;      /* Byte 9 Bit 5 */
0439     unsigned char rsvd2:2;          /* Byte 9 Bits 6-7 */
0440     unsigned char raid5_writeupdate;    /* Byte 10 */
0441     unsigned char raid5_algo;       /* Byte 11 */
0442     unsigned short ldev_num;        /* Bytes 12-13 */
0443     /* BIOS Info */
0444     unsigned char bios_disabled:1;      /* Byte 14 Bit 0 */
0445     unsigned char cdrom_boot:1;     /* Byte 14 Bit 1 */
0446     unsigned char drv_coercion:1;       /* Byte 14 Bit 2 */
0447     unsigned char write_same_disabled:1;    /* Byte 14 Bit 3 */
0448     unsigned char hba_mode:1;       /* Byte 14 Bit 4 */
0449     enum {
0450         MYRS_GEOMETRY_128_32    = 0x0,
0451         MYRS_GEOMETRY_255_63    = 0x1,
0452         MYRS_GEOMETRY_RSVD1 = 0x2,
0453         MYRS_GEOMETRY_RSVD2 = 0x3
0454     } __packed drv_geom:2;  /* Byte 14 Bits 5-6 */
0455     unsigned char super_ra_enabled:1;   /* Byte 14 Bit 7 */
0456     unsigned char rsvd3;            /* Byte 15 */
0457     /* Error Counters */
0458     unsigned short soft_errs;       /* Bytes 16-17 */
0459     unsigned short cmds_failed;     /* Bytes 18-19 */
0460     unsigned short cmds_aborted;        /* Bytes 20-21 */
0461     unsigned short deferred_write_errs; /* Bytes 22-23 */
0462     unsigned int rsvd4;         /* Bytes 24-27 */
0463     unsigned int rsvd5;         /* Bytes 28-31 */
0464     /* Device Size Information */
0465     unsigned short rsvd6;           /* Bytes 32-33 */
0466     unsigned short devsize_bytes;       /* Bytes 34-35 */
0467     unsigned int orig_devsize;      /* Bytes 36-39 */
0468     unsigned int cfg_devsize;       /* Bytes 40-43 */
0469     unsigned int rsvd7;         /* Bytes 44-47 */
0470     unsigned char ldev_name[32];        /* Bytes 48-79 */
0471     unsigned char inquiry[36];      /* Bytes 80-115 */
0472     unsigned char rsvd8[12];        /* Bytes 116-127 */
0473     u64 last_read_lba;          /* Bytes 128-135 */
0474     u64 last_write_lba;         /* Bytes 136-143 */
0475     u64 cc_lba;             /* Bytes 144-151 */
0476     u64 rbld_lba;               /* Bytes 152-159 */
0477     u64 bg_init_lba;            /* Bytes 160-167 */
0478     u64 fg_init_lba;            /* Bytes 168-175 */
0479     u64 migration_lba;          /* Bytes 176-183 */
0480     u64 patrol_lba;             /* Bytes 184-191 */
0481     unsigned char rsvd9[64];        /* Bytes 192-255 */
0482 };
0483 
0484 /*
0485  * DAC960 V2 Firmware Get Physical Device Info reply structure.
0486  */
0487 struct myrs_pdev_info {
0488     unsigned char rsvd1;            /* Byte 0 */
0489     unsigned char channel;          /* Byte 1 */
0490     unsigned char target;           /* Byte 2 */
0491     unsigned char lun;          /* Byte 3 */
0492     /* Configuration Status Bits */
0493     unsigned char pdev_fault_tolerant:1;    /* Byte 4 Bit 0 */
0494     unsigned char pdev_connected:1;     /* Byte 4 Bit 1 */
0495     unsigned char pdev_local_to_ctlr:1; /* Byte 4 Bit 2 */
0496     unsigned char rsvd2:5;          /* Byte 4 Bits 3-7 */
0497     /* Multiple Host/Controller Status Bits */
0498     unsigned char remote_host_dead:1;   /* Byte 5 Bit 0 */
0499     unsigned char remove_ctlr_dead:1;   /* Byte 5 Bit 1 */
0500     unsigned char rsvd3:6;          /* Byte 5 Bits 2-7 */
0501     enum myrs_devstate dev_state;       /* Byte 6 */
0502     unsigned char nego_data_width;      /* Byte 7 */
0503     unsigned short nego_sync_rate;      /* Bytes 8-9 */
0504     /* Multiported Physical Device Information */
0505     unsigned char num_ports;        /* Byte 10 */
0506     unsigned char drv_access_bitmap;    /* Byte 11 */
0507     unsigned int rsvd4;         /* Bytes 12-15 */
0508     unsigned char ip_address[16];       /* Bytes 16-31 */
0509     unsigned short max_tags;        /* Bytes 32-33 */
0510     /* Physical Device Operations Status */
0511     unsigned char cc_in_progress:1;     /* Byte 34 Bit 0 */
0512     unsigned char rbld_in_progress:1;   /* Byte 34 Bit 1 */
0513     unsigned char makecc_in_progress:1; /* Byte 34 Bit 2 */
0514     unsigned char pdevinit_in_progress:1;   /* Byte 34 Bit 3 */
0515     unsigned char migration_in_progress:1;  /* Byte 34 Bit 4 */
0516     unsigned char patrol_in_progress:1; /* Byte 34 Bit 5 */
0517     unsigned char rsvd5:2;          /* Byte 34 Bits 6-7 */
0518     unsigned char long_op_status;       /* Byte 35 */
0519     unsigned char parity_errs;      /* Byte 36 */
0520     unsigned char soft_errs;        /* Byte 37 */
0521     unsigned char hard_errs;        /* Byte 38 */
0522     unsigned char misc_errs;        /* Byte 39 */
0523     unsigned char cmd_timeouts;     /* Byte 40 */
0524     unsigned char retries;          /* Byte 41 */
0525     unsigned char aborts;           /* Byte 42 */
0526     unsigned char pred_failures;        /* Byte 43 */
0527     unsigned int rsvd6;         /* Bytes 44-47 */
0528     unsigned short rsvd7;           /* Bytes 48-49 */
0529     unsigned short devsize_bytes;       /* Bytes 50-51 */
0530     unsigned int orig_devsize;      /* Bytes 52-55 */
0531     unsigned int cfg_devsize;       /* Bytes 56-59 */
0532     unsigned int rsvd8;         /* Bytes 60-63 */
0533     unsigned char pdev_name[16];        /* Bytes 64-79 */
0534     unsigned char rsvd9[16];        /* Bytes 80-95 */
0535     unsigned char rsvd10[32];       /* Bytes 96-127 */
0536     unsigned char inquiry[36];      /* Bytes 128-163 */
0537     unsigned char rsvd11[20];       /* Bytes 164-183 */
0538     unsigned char rsvd12[8];        /* Bytes 184-191 */
0539     u64 last_read_lba;          /* Bytes 192-199 */
0540     u64 last_write_lba;         /* Bytes 200-207 */
0541     u64 cc_lba;             /* Bytes 208-215 */
0542     u64 rbld_lba;               /* Bytes 216-223 */
0543     u64 makecc_lba;             /* Bytes 224-231 */
0544     u64 devinit_lba;            /* Bytes 232-239 */
0545     u64 migration_lba;          /* Bytes 240-247 */
0546     u64 patrol_lba;             /* Bytes 248-255 */
0547     unsigned char rsvd13[256];      /* Bytes 256-511 */
0548 };
0549 
0550 /*
0551  * DAC960 V2 Firmware Health Status Buffer structure.
0552  */
0553 struct myrs_fwstat {
0554     unsigned int uptime_usecs;      /* Bytes 0-3 */
0555     unsigned int uptime_msecs;      /* Bytes 4-7 */
0556     unsigned int seconds;           /* Bytes 8-11 */
0557     unsigned char rsvd1[4];         /* Bytes 12-15 */
0558     unsigned int epoch;         /* Bytes 16-19 */
0559     unsigned char rsvd2[4];         /* Bytes 20-23 */
0560     unsigned int dbg_msgbuf_idx;        /* Bytes 24-27 */
0561     unsigned int coded_msgbuf_idx;      /* Bytes 28-31 */
0562     unsigned int cur_timetrace_page;    /* Bytes 32-35 */
0563     unsigned int cur_prof_page;     /* Bytes 36-39 */
0564     unsigned int next_evseq;        /* Bytes 40-43 */
0565     unsigned char rsvd3[4];         /* Bytes 44-47 */
0566     unsigned char rsvd4[16];        /* Bytes 48-63 */
0567     unsigned char rsvd5[64];        /* Bytes 64-127 */
0568 };
0569 
0570 /*
0571  * DAC960 V2 Firmware Get Event reply structure.
0572  */
0573 struct myrs_event {
0574     unsigned int ev_seq;            /* Bytes 0-3 */
0575     unsigned int ev_time;           /* Bytes 4-7 */
0576     unsigned int ev_code;           /* Bytes 8-11 */
0577     unsigned char rsvd1;            /* Byte 12 */
0578     unsigned char channel;          /* Byte 13 */
0579     unsigned char target;           /* Byte 14 */
0580     unsigned char lun;          /* Byte 15 */
0581     unsigned int rsvd2;         /* Bytes 16-19 */
0582     unsigned int ev_parm;           /* Bytes 20-23 */
0583     unsigned char sense_data[40];       /* Bytes 24-63 */
0584 };
0585 
0586 /*
0587  * DAC960 V2 Firmware Command Control Bits structure.
0588  */
0589 struct myrs_cmd_ctrl {
0590     unsigned char fua:1;            /* Byte 0 Bit 0 */
0591     unsigned char disable_pgout:1;      /* Byte 0 Bit 1 */
0592     unsigned char rsvd1:1;          /* Byte 0 Bit 2 */
0593     unsigned char add_sge_mem:1;        /* Byte 0 Bit 3 */
0594     unsigned char dma_ctrl_to_host:1;   /* Byte 0 Bit 4 */
0595     unsigned char rsvd2:1;          /* Byte 0 Bit 5 */
0596     unsigned char no_autosense:1;       /* Byte 0 Bit 6 */
0597     unsigned char disc_prohibited:1;    /* Byte 0 Bit 7 */
0598 };
0599 
0600 /*
0601  * DAC960 V2 Firmware Command Timeout structure.
0602  */
0603 struct myrs_cmd_tmo {
0604     unsigned char tmo_val:6;            /* Byte 0 Bits 0-5 */
0605     enum {
0606         MYRS_TMO_SCALE_SECONDS  = 0,
0607         MYRS_TMO_SCALE_MINUTES  = 1,
0608         MYRS_TMO_SCALE_HOURS    = 2,
0609         MYRS_TMO_SCALE_RESERVED = 3
0610     } __packed tmo_scale:2;     /* Byte 0 Bits 6-7 */
0611 };
0612 
0613 /*
0614  * DAC960 V2 Firmware Physical Device structure.
0615  */
0616 struct myrs_pdev {
0617     unsigned char lun;          /* Byte 0 */
0618     unsigned char target;           /* Byte 1 */
0619     unsigned char channel:3;        /* Byte 2 Bits 0-2 */
0620     unsigned char ctlr:5;           /* Byte 2 Bits 3-7 */
0621 } __packed;
0622 
0623 /*
0624  * DAC960 V2 Firmware Logical Device structure.
0625  */
0626 struct myrs_ldev {
0627     unsigned short ldev_num;        /* Bytes 0-1 */
0628     unsigned char rsvd:3;           /* Byte 2 Bits 0-2 */
0629     unsigned char ctlr:5;           /* Byte 2 Bits 3-7 */
0630 } __packed;
0631 
0632 /*
0633  * DAC960 V2 Firmware Operation Device type.
0634  */
0635 enum myrs_opdev {
0636     MYRS_PHYSICAL_DEVICE    = 0x00,
0637     MYRS_RAID_DEVICE    = 0x01,
0638     MYRS_PHYSICAL_CHANNEL   = 0x02,
0639     MYRS_RAID_CHANNEL   = 0x03,
0640     MYRS_PHYSICAL_CONTROLLER = 0x04,
0641     MYRS_RAID_CONTROLLER    = 0x05,
0642     MYRS_CONFIGURATION_GROUP = 0x10,
0643     MYRS_ENCLOSURE      = 0x11,
0644 } __packed;
0645 
0646 /*
0647  * DAC960 V2 Firmware Translate Physical To Logical Device structure.
0648  */
0649 struct myrs_devmap {
0650     unsigned short ldev_num;        /* Bytes 0-1 */
0651     unsigned short rsvd;            /* Bytes 2-3 */
0652     unsigned char prev_boot_ctlr;       /* Byte 4 */
0653     unsigned char prev_boot_channel;    /* Byte 5 */
0654     unsigned char prev_boot_target;     /* Byte 6 */
0655     unsigned char prev_boot_lun;        /* Byte 7 */
0656 };
0657 
0658 /*
0659  * DAC960 V2 Firmware Scatter/Gather List Entry structure.
0660  */
0661 struct myrs_sge {
0662     u64 sge_addr;           /* Bytes 0-7 */
0663     u64 sge_count;          /* Bytes 8-15 */
0664 };
0665 
0666 /*
0667  * DAC960 V2 Firmware Data Transfer Memory Address structure.
0668  */
0669 union myrs_sgl {
0670     struct myrs_sge sge[2]; /* Bytes 0-31 */
0671     struct {
0672         unsigned short sge0_len;    /* Bytes 0-1 */
0673         unsigned short sge1_len;    /* Bytes 2-3 */
0674         unsigned short sge2_len;    /* Bytes 4-5 */
0675         unsigned short rsvd;        /* Bytes 6-7 */
0676         u64 sge0_addr;          /* Bytes 8-15 */
0677         u64 sge1_addr;          /* Bytes 16-23 */
0678         u64 sge2_addr;          /* Bytes 24-31 */
0679     } ext;
0680 };
0681 
0682 /*
0683  * 64 Byte DAC960 V2 Firmware Command Mailbox structure.
0684  */
0685 union myrs_cmd_mbox {
0686     unsigned int words[16];             /* Words 0-15 */
0687     struct {
0688         unsigned short id;          /* Bytes 0-1 */
0689         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0690         struct myrs_cmd_ctrl control;       /* Byte 3 */
0691         u32 dma_size:24;            /* Bytes 4-6 */
0692         unsigned char dma_num;          /* Byte 7 */
0693         u64 sense_addr;             /* Bytes 8-15 */
0694         unsigned int rsvd1:24;          /* Bytes 16-18 */
0695         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0696         unsigned char sense_len;        /* Byte 20 */
0697         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0698         unsigned char rsvd2[10];        /* Bytes 22-31 */
0699         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0700     } common;
0701     struct {
0702         unsigned short id;          /* Bytes 0-1 */
0703         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0704         struct myrs_cmd_ctrl control;       /* Byte 3 */
0705         u32 dma_size;               /* Bytes 4-7 */
0706         u64 sense_addr;             /* Bytes 8-15 */
0707         struct myrs_pdev pdev;          /* Bytes 16-18 */
0708         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0709         unsigned char sense_len;        /* Byte 20 */
0710         unsigned char cdb_len;          /* Byte 21 */
0711         unsigned char cdb[10];          /* Bytes 22-31 */
0712         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0713     } SCSI_10;
0714     struct {
0715         unsigned short id;          /* Bytes 0-1 */
0716         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0717         struct myrs_cmd_ctrl control;       /* Byte 3 */
0718         u32 dma_size;               /* Bytes 4-7 */
0719         u64 sense_addr;             /* Bytes 8-15 */
0720         struct myrs_pdev pdev;          /* Bytes 16-18 */
0721         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0722         unsigned char sense_len;        /* Byte 20 */
0723         unsigned char cdb_len;          /* Byte 21 */
0724         unsigned short rsvd;            /* Bytes 22-23 */
0725         u64 cdb_addr;               /* Bytes 24-31 */
0726         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0727     } SCSI_255;
0728     struct {
0729         unsigned short id;          /* Bytes 0-1 */
0730         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0731         struct myrs_cmd_ctrl control;       /* Byte 3 */
0732         u32 dma_size:24;            /* Bytes 4-6 */
0733         unsigned char dma_num;          /* Byte 7 */
0734         u64 sense_addr;             /* Bytes 8-15 */
0735         unsigned short rsvd1;           /* Bytes 16-17 */
0736         unsigned char ctlr_num;         /* Byte 18 */
0737         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0738         unsigned char sense_len;        /* Byte 20 */
0739         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0740         unsigned char rsvd2[10];        /* Bytes 22-31 */
0741         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0742     } ctlr_info;
0743     struct {
0744         unsigned short id;          /* Bytes 0-1 */
0745         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0746         struct myrs_cmd_ctrl control;       /* Byte 3 */
0747         u32 dma_size:24;            /* Bytes 4-6 */
0748         unsigned char dma_num;          /* Byte 7 */
0749         u64 sense_addr;             /* Bytes 8-15 */
0750         struct myrs_ldev ldev;          /* Bytes 16-18 */
0751         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0752         unsigned char sense_len;        /* Byte 20 */
0753         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0754         unsigned char rsvd[10];         /* Bytes 22-31 */
0755         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0756     } ldev_info;
0757     struct {
0758         unsigned short id;          /* Bytes 0-1 */
0759         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0760         struct myrs_cmd_ctrl control;       /* Byte 3 */
0761         u32 dma_size:24;            /* Bytes 4-6 */
0762         unsigned char dma_num;          /* Byte 7 */
0763         u64 sense_addr;             /* Bytes 8-15 */
0764         struct myrs_pdev pdev;          /* Bytes 16-18 */
0765         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0766         unsigned char sense_len;        /* Byte 20 */
0767         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0768         unsigned char rsvd[10];         /* Bytes 22-31 */
0769         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0770     } pdev_info;
0771     struct {
0772         unsigned short id;          /* Bytes 0-1 */
0773         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0774         struct myrs_cmd_ctrl control;       /* Byte 3 */
0775         u32 dma_size:24;            /* Bytes 4-6 */
0776         unsigned char dma_num;          /* Byte 7 */
0777         u64 sense_addr;             /* Bytes 8-15 */
0778         unsigned short evnum_upper;     /* Bytes 16-17 */
0779         unsigned char ctlr_num;         /* Byte 18 */
0780         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0781         unsigned char sense_len;        /* Byte 20 */
0782         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0783         unsigned short evnum_lower;     /* Bytes 22-23 */
0784         unsigned char rsvd[8];          /* Bytes 24-31 */
0785         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0786     } get_event;
0787     struct {
0788         unsigned short id;          /* Bytes 0-1 */
0789         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0790         struct myrs_cmd_ctrl control;       /* Byte 3 */
0791         u32 dma_size:24;            /* Bytes 4-6 */
0792         unsigned char dma_num;          /* Byte 7 */
0793         u64 sense_addr;             /* Bytes 8-15 */
0794         union {
0795             struct myrs_ldev ldev;      /* Bytes 16-18 */
0796             struct myrs_pdev pdev;      /* Bytes 16-18 */
0797         };
0798         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0799         unsigned char sense_len;        /* Byte 20 */
0800         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0801         enum myrs_devstate state;       /* Byte 22 */
0802         unsigned char rsvd[9];          /* Bytes 23-31 */
0803         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0804     } set_devstate;
0805     struct {
0806         unsigned short id;          /* Bytes 0-1 */
0807         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0808         struct myrs_cmd_ctrl control;       /* Byte 3 */
0809         u32 dma_size:24;            /* Bytes 4-6 */
0810         unsigned char dma_num;          /* Byte 7 */
0811         u64 sense_addr;             /* Bytes 8-15 */
0812         struct myrs_ldev ldev;          /* Bytes 16-18 */
0813         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0814         unsigned char sense_len;        /* Byte 20 */
0815         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0816         unsigned char restore_consistency:1;    /* Byte 22 Bit 0 */
0817         unsigned char initialized_area_only:1;  /* Byte 22 Bit 1 */
0818         unsigned char rsvd1:6;          /* Byte 22 Bits 2-7 */
0819         unsigned char rsvd2[9];         /* Bytes 23-31 */
0820         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0821     } cc;
0822     struct {
0823         unsigned short id;          /* Bytes 0-1 */
0824         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0825         struct myrs_cmd_ctrl control;       /* Byte 3 */
0826         unsigned char first_cmd_mbox_size_kb;   /* Byte 4 */
0827         unsigned char first_stat_mbox_size_kb;  /* Byte 5 */
0828         unsigned char second_cmd_mbox_size_kb;  /* Byte 6 */
0829         unsigned char second_stat_mbox_size_kb; /* Byte 7 */
0830         u64 sense_addr;             /* Bytes 8-15 */
0831         unsigned int rsvd1:24;          /* Bytes 16-18 */
0832         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0833         unsigned char sense_len;        /* Byte 20 */
0834         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0835         unsigned char fwstat_buf_size_kb;   /* Byte 22 */
0836         unsigned char rsvd2;            /* Byte 23 */
0837         u64 fwstat_buf_addr;            /* Bytes 24-31 */
0838         u64 first_cmd_mbox_addr;        /* Bytes 32-39 */
0839         u64 first_stat_mbox_addr;       /* Bytes 40-47 */
0840         u64 second_cmd_mbox_addr;       /* Bytes 48-55 */
0841         u64 second_stat_mbox_addr;      /* Bytes 56-63 */
0842     } set_mbox;
0843     struct {
0844         unsigned short id;          /* Bytes 0-1 */
0845         enum myrs_cmd_opcode opcode;        /* Byte 2 */
0846         struct myrs_cmd_ctrl control;       /* Byte 3 */
0847         u32 dma_size:24;            /* Bytes 4-6 */
0848         unsigned char dma_num;          /* Byte 7 */
0849         u64 sense_addr;             /* Bytes 8-15 */
0850         struct myrs_pdev pdev;          /* Bytes 16-18 */
0851         struct myrs_cmd_tmo tmo;        /* Byte 19 */
0852         unsigned char sense_len;        /* Byte 20 */
0853         enum myrs_ioctl_opcode ioctl_opcode;    /* Byte 21 */
0854         enum myrs_opdev opdev;          /* Byte 22 */
0855         unsigned char rsvd[9];          /* Bytes 23-31 */
0856         union myrs_sgl dma_addr;        /* Bytes 32-63 */
0857     } dev_op;
0858 };
0859 
0860 /*
0861  * DAC960 V2 Firmware Controller Status Mailbox structure.
0862  */
0863 struct myrs_stat_mbox {
0864     unsigned short id;      /* Bytes 0-1 */
0865     unsigned char status;       /* Byte 2 */
0866     unsigned char sense_len;    /* Byte 3 */
0867     int residual;           /* Bytes 4-7 */
0868 };
0869 
0870 struct myrs_cmdblk {
0871     union myrs_cmd_mbox mbox;
0872     unsigned char status;
0873     unsigned char sense_len;
0874     int residual;
0875     struct completion *complete;
0876     struct myrs_sge *sgl;
0877     dma_addr_t sgl_addr;
0878     unsigned char *dcdb;
0879     dma_addr_t dcdb_dma;
0880     unsigned char *sense;
0881     dma_addr_t sense_addr;
0882 };
0883 
0884 /*
0885  * DAC960 Driver Controller structure.
0886  */
0887 struct myrs_hba {
0888     void __iomem *io_base;
0889     void __iomem *mmio_base;
0890     phys_addr_t io_addr;
0891     phys_addr_t pci_addr;
0892     unsigned int irq;
0893 
0894     unsigned char model_name[28];
0895     unsigned char fw_version[12];
0896 
0897     struct Scsi_Host *host;
0898     struct pci_dev *pdev;
0899 
0900     unsigned int epoch;
0901     unsigned int next_evseq;
0902     /* Monitor flags */
0903     bool needs_update;
0904     bool disable_enc_msg;
0905 
0906     struct workqueue_struct *work_q;
0907     char work_q_name[20];
0908     struct delayed_work monitor_work;
0909     unsigned long primary_monitor_time;
0910     unsigned long secondary_monitor_time;
0911 
0912     spinlock_t queue_lock;
0913 
0914     struct dma_pool *sg_pool;
0915     struct dma_pool *sense_pool;
0916     struct dma_pool *dcdb_pool;
0917 
0918     void (*write_cmd_mbox)(union myrs_cmd_mbox *next_mbox,
0919                    union myrs_cmd_mbox *cmd_mbox);
0920     void (*get_cmd_mbox)(void __iomem *base);
0921     void (*disable_intr)(void __iomem *base);
0922     void (*reset)(void __iomem *base);
0923 
0924     dma_addr_t cmd_mbox_addr;
0925     size_t cmd_mbox_size;
0926     union myrs_cmd_mbox *first_cmd_mbox;
0927     union myrs_cmd_mbox *last_cmd_mbox;
0928     union myrs_cmd_mbox *next_cmd_mbox;
0929     union myrs_cmd_mbox *prev_cmd_mbox1;
0930     union myrs_cmd_mbox *prev_cmd_mbox2;
0931 
0932     dma_addr_t stat_mbox_addr;
0933     size_t stat_mbox_size;
0934     struct myrs_stat_mbox *first_stat_mbox;
0935     struct myrs_stat_mbox *last_stat_mbox;
0936     struct myrs_stat_mbox *next_stat_mbox;
0937 
0938     struct myrs_cmdblk dcmd_blk;
0939     struct myrs_cmdblk mcmd_blk;
0940     struct mutex dcmd_mutex;
0941 
0942     struct myrs_fwstat *fwstat_buf;
0943     dma_addr_t fwstat_addr;
0944 
0945     struct myrs_ctlr_info *ctlr_info;
0946     struct mutex cinfo_mutex;
0947 
0948     struct myrs_event *event_buf;
0949 };
0950 
0951 typedef unsigned char (*enable_mbox_t)(void __iomem *base, dma_addr_t addr);
0952 typedef int (*myrs_hwinit_t)(struct pci_dev *pdev,
0953                  struct myrs_hba *c, void __iomem *base);
0954 
0955 struct myrs_privdata {
0956     myrs_hwinit_t       hw_init;
0957     irq_handler_t       irq_handler;
0958     unsigned int        mmio_size;
0959 };
0960 
0961 /*
0962  * DAC960 GEM Series Controller Interface Register Offsets.
0963  */
0964 
0965 #define DAC960_GEM_mmio_size    0x600
0966 
0967 enum DAC960_GEM_reg_offset {
0968     DAC960_GEM_IDB_READ_OFFSET  = 0x214,
0969     DAC960_GEM_IDB_CLEAR_OFFSET = 0x218,
0970     DAC960_GEM_ODB_READ_OFFSET  = 0x224,
0971     DAC960_GEM_ODB_CLEAR_OFFSET = 0x228,
0972     DAC960_GEM_IRQSTS_OFFSET    = 0x208,
0973     DAC960_GEM_IRQMASK_READ_OFFSET  = 0x22C,
0974     DAC960_GEM_IRQMASK_CLEAR_OFFSET = 0x230,
0975     DAC960_GEM_CMDMBX_OFFSET    = 0x510,
0976     DAC960_GEM_CMDSTS_OFFSET    = 0x518,
0977     DAC960_GEM_ERRSTS_READ_OFFSET   = 0x224,
0978     DAC960_GEM_ERRSTS_CLEAR_OFFSET  = 0x228,
0979 };
0980 
0981 /*
0982  * DAC960 GEM Series Inbound Door Bell Register.
0983  */
0984 #define DAC960_GEM_IDB_HWMBOX_NEW_CMD   0x01
0985 #define DAC960_GEM_IDB_HWMBOX_ACK_STS   0x02
0986 #define DAC960_GEM_IDB_GEN_IRQ      0x04
0987 #define DAC960_GEM_IDB_CTRL_RESET   0x08
0988 #define DAC960_GEM_IDB_MMBOX_NEW_CMD    0x10
0989 
0990 #define DAC960_GEM_IDB_HWMBOX_FULL  0x01
0991 #define DAC960_GEM_IDB_INIT_IN_PROGRESS 0x02
0992 
0993 /*
0994  * DAC960 GEM Series Outbound Door Bell Register.
0995  */
0996 #define DAC960_GEM_ODB_HWMBOX_ACK_IRQ   0x01
0997 #define DAC960_GEM_ODB_MMBOX_ACK_IRQ    0x02
0998 #define DAC960_GEM_ODB_HWMBOX_STS_AVAIL 0x01
0999 #define DAC960_GEM_ODB_MMBOX_STS_AVAIL  0x02
1000 
1001 /*
1002  * DAC960 GEM Series Interrupt Mask Register.
1003  */
1004 #define DAC960_GEM_IRQMASK_HWMBOX_IRQ   0x01
1005 #define DAC960_GEM_IRQMASK_MMBOX_IRQ    0x02
1006 
1007 /*
1008  * DAC960 GEM Series Error Status Register.
1009  */
1010 #define DAC960_GEM_ERRSTS_PENDING   0x20
1011 
1012 /*
1013  * dma_addr_writeql is provided to write dma_addr_t types
1014  * to a 64-bit pci address space register.  The controller
1015  * will accept having the register written as two 32-bit
1016  * values.
1017  *
1018  * In HIGHMEM kernels, dma_addr_t is a 64-bit value.
1019  * without HIGHMEM,  dma_addr_t is a 32-bit value.
1020  *
1021  * The compiler should always fix up the assignment
1022  * to u.wq appropriately, depending upon the size of
1023  * dma_addr_t.
1024  */
1025 static inline
1026 void dma_addr_writeql(dma_addr_t addr, void __iomem *write_address)
1027 {
1028     union {
1029         u64 wq;
1030         uint wl[2];
1031     } u;
1032 
1033     u.wq = addr;
1034 
1035     writel(u.wl[0], write_address);
1036     writel(u.wl[1], write_address + 4);
1037 }
1038 
1039 /*
1040  * DAC960 BA Series Controller Interface Register Offsets.
1041  */
1042 
1043 #define DAC960_BA_mmio_size     0x80
1044 
1045 enum DAC960_BA_reg_offset {
1046     DAC960_BA_IRQSTS_OFFSET = 0x30,
1047     DAC960_BA_IRQMASK_OFFSET = 0x34,
1048     DAC960_BA_CMDMBX_OFFSET = 0x50,
1049     DAC960_BA_CMDSTS_OFFSET = 0x58,
1050     DAC960_BA_IDB_OFFSET    = 0x60,
1051     DAC960_BA_ODB_OFFSET    = 0x61,
1052     DAC960_BA_ERRSTS_OFFSET = 0x63,
1053 };
1054 
1055 /*
1056  * DAC960 BA Series Inbound Door Bell Register.
1057  */
1058 #define DAC960_BA_IDB_HWMBOX_NEW_CMD    0x01
1059 #define DAC960_BA_IDB_HWMBOX_ACK_STS    0x02
1060 #define DAC960_BA_IDB_GEN_IRQ       0x04
1061 #define DAC960_BA_IDB_CTRL_RESET    0x08
1062 #define DAC960_BA_IDB_MMBOX_NEW_CMD 0x10
1063 
1064 #define DAC960_BA_IDB_HWMBOX_EMPTY  0x01
1065 #define DAC960_BA_IDB_INIT_DONE     0x02
1066 
1067 /*
1068  * DAC960 BA Series Outbound Door Bell Register.
1069  */
1070 #define DAC960_BA_ODB_HWMBOX_ACK_IRQ    0x01
1071 #define DAC960_BA_ODB_MMBOX_ACK_IRQ 0x02
1072 
1073 #define DAC960_BA_ODB_HWMBOX_STS_AVAIL  0x01
1074 #define DAC960_BA_ODB_MMBOX_STS_AVAIL   0x02
1075 
1076 /*
1077  * DAC960 BA Series Interrupt Mask Register.
1078  */
1079 #define DAC960_BA_IRQMASK_DISABLE_IRQ   0x04
1080 #define DAC960_BA_IRQMASK_DISABLEW_I2O  0x08
1081 
1082 /*
1083  * DAC960 BA Series Error Status Register.
1084  */
1085 #define DAC960_BA_ERRSTS_PENDING    0x04
1086 
1087 /*
1088  * DAC960 LP Series Controller Interface Register Offsets.
1089  */
1090 
1091 #define DAC960_LP_mmio_size     0x80
1092 
1093 enum DAC960_LP_reg_offset {
1094     DAC960_LP_CMDMBX_OFFSET = 0x10,
1095     DAC960_LP_CMDSTS_OFFSET = 0x18,
1096     DAC960_LP_IDB_OFFSET    = 0x20,
1097     DAC960_LP_ODB_OFFSET    = 0x2C,
1098     DAC960_LP_ERRSTS_OFFSET = 0x2E,
1099     DAC960_LP_IRQSTS_OFFSET = 0x30,
1100     DAC960_LP_IRQMASK_OFFSET = 0x34,
1101 };
1102 
1103 /*
1104  * DAC960 LP Series Inbound Door Bell Register.
1105  */
1106 #define DAC960_LP_IDB_HWMBOX_NEW_CMD    0x01
1107 #define DAC960_LP_IDB_HWMBOX_ACK_STS    0x02
1108 #define DAC960_LP_IDB_GEN_IRQ       0x04
1109 #define DAC960_LP_IDB_CTRL_RESET    0x08
1110 #define DAC960_LP_IDB_MMBOX_NEW_CMD 0x10
1111 
1112 #define DAC960_LP_IDB_HWMBOX_FULL   0x01
1113 #define DAC960_LP_IDB_INIT_IN_PROGRESS  0x02
1114 
1115 /*
1116  * DAC960 LP Series Outbound Door Bell Register.
1117  */
1118 #define DAC960_LP_ODB_HWMBOX_ACK_IRQ    0x01
1119 #define DAC960_LP_ODB_MMBOX_ACK_IRQ 0x02
1120 
1121 #define DAC960_LP_ODB_HWMBOX_STS_AVAIL  0x01
1122 #define DAC960_LP_ODB_MMBOX_STS_AVAIL   0x02
1123 
1124 /*
1125  * DAC960 LP Series Interrupt Mask Register.
1126  */
1127 #define DAC960_LP_IRQMASK_DISABLE_IRQ   0x04
1128 
1129 /*
1130  * DAC960 LP Series Error Status Register.
1131  */
1132 #define DAC960_LP_ERRSTS_PENDING    0x04
1133 
1134 #endif /* _MYRS_H */
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