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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Linux Driver for Mylex DAC960/AcceleRAID/eXtremeRAID PCI RAID Controllers
0004  *
0005  * Copyright 2017 Hannes Reinecke, SUSE Linux GmbH <hare@suse.com>
0006  *
0007  * Based on the original DAC960 driver,
0008  * Copyright 1998-2001 by Leonard N. Zubkoff <lnz@dandelion.com>
0009  * Portions Copyright 2002 by Mylex (An IBM Business Unit)
0010  *
0011  */
0012 
0013 #ifndef MYRB_H
0014 #define MYRB_H
0015 
0016 #define MYRB_MAX_LDEVS          32
0017 #define MYRB_MAX_CHANNELS       3
0018 #define MYRB_MAX_TARGETS        16
0019 #define MYRB_MAX_PHYSICAL_DEVICES   45
0020 #define MYRB_SCATTER_GATHER_LIMIT   32
0021 #define MYRB_CMD_MBOX_COUNT     256
0022 #define MYRB_STAT_MBOX_COUNT        1024
0023 
0024 #define MYRB_BLKSIZE_BITS       9
0025 #define MYRB_MAILBOX_TIMEOUT        1000000
0026 
0027 #define MYRB_DCMD_TAG           1
0028 #define MYRB_MCMD_TAG           2
0029 
0030 #define MYRB_PRIMARY_MONITOR_INTERVAL (10 * HZ)
0031 #define MYRB_SECONDARY_MONITOR_INTERVAL (60 * HZ)
0032 
0033 /*
0034  * DAC960 V1 Firmware Command Opcodes.
0035  */
0036 enum myrb_cmd_opcode {
0037     /* I/O Commands */
0038     MYRB_CMD_READ_EXTENDED =    0x33,
0039     MYRB_CMD_WRITE_EXTENDED =   0x34,
0040     MYRB_CMD_READAHEAD_EXTENDED =   0x35,
0041     MYRB_CMD_READ_EXTENDED_SG = 0xB3,
0042     MYRB_CMD_WRITE_EXTENDED_SG =    0xB4,
0043     MYRB_CMD_READ =         0x36,
0044     MYRB_CMD_READ_SG =      0xB6,
0045     MYRB_CMD_WRITE =        0x37,
0046     MYRB_CMD_WRITE_SG =     0xB7,
0047     MYRB_CMD_DCDB =         0x04,
0048     MYRB_CMD_DCDB_SG =      0x84,
0049     MYRB_CMD_FLUSH =        0x0A,
0050     /* Controller Status Related Commands */
0051     MYRB_CMD_ENQUIRY =      0x53,
0052     MYRB_CMD_ENQUIRY2 =     0x1C,
0053     MYRB_CMD_GET_LDRV_ELEMENT = 0x55,
0054     MYRB_CMD_GET_LDEV_INFO =    0x19,
0055     MYRB_CMD_IOPORTREAD =       0x39,
0056     MYRB_CMD_IOPORTWRITE =      0x3A,
0057     MYRB_CMD_GET_SD_STATS =     0x3E,
0058     MYRB_CMD_GET_PD_STATS =     0x3F,
0059     MYRB_CMD_EVENT_LOG_OPERATION =  0x72,
0060     /* Device Related Commands */
0061     MYRB_CMD_START_DEVICE =     0x10,
0062     MYRB_CMD_GET_DEVICE_STATE = 0x50,
0063     MYRB_CMD_STOP_CHANNEL =     0x13,
0064     MYRB_CMD_START_CHANNEL =    0x12,
0065     MYRB_CMD_RESET_CHANNEL =    0x1A,
0066     /* Commands Associated with Data Consistency and Errors */
0067     MYRB_CMD_REBUILD =      0x09,
0068     MYRB_CMD_REBUILD_ASYNC =    0x16,
0069     MYRB_CMD_CHECK_CONSISTENCY =    0x0F,
0070     MYRB_CMD_CHECK_CONSISTENCY_ASYNC = 0x1E,
0071     MYRB_CMD_REBUILD_STAT =     0x0C,
0072     MYRB_CMD_GET_REBUILD_PROGRESS = 0x27,
0073     MYRB_CMD_REBUILD_CONTROL =  0x1F,
0074     MYRB_CMD_READ_BADBLOCK_TABLE =  0x0B,
0075     MYRB_CMD_READ_BADDATA_TABLE =   0x25,
0076     MYRB_CMD_CLEAR_BADDATA_TABLE =  0x26,
0077     MYRB_CMD_GET_ERROR_TABLE =  0x17,
0078     MYRB_CMD_ADD_CAPACITY_ASYNC =   0x2A,
0079     MYRB_CMD_BGI_CONTROL =      0x2B,
0080     /* Configuration Related Commands */
0081     MYRB_CMD_READ_CONFIG2 =     0x3D,
0082     MYRB_CMD_WRITE_CONFIG2 =    0x3C,
0083     MYRB_CMD_READ_CONFIG_ONDISK =   0x4A,
0084     MYRB_CMD_WRITE_CONFIG_ONDISK =  0x4B,
0085     MYRB_CMD_READ_CONFIG =      0x4E,
0086     MYRB_CMD_READ_BACKUP_CONFIG =   0x4D,
0087     MYRB_CMD_WRITE_CONFIG =     0x4F,
0088     MYRB_CMD_ADD_CONFIG =       0x4C,
0089     MYRB_CMD_READ_CONFIG_LABEL =    0x48,
0090     MYRB_CMD_WRITE_CONFIG_LABEL =   0x49,
0091     /* Firmware Upgrade Related Commands */
0092     MYRB_CMD_LOAD_IMAGE =       0x20,
0093     MYRB_CMD_STORE_IMAGE =      0x21,
0094     MYRB_CMD_PROGRAM_IMAGE =    0x22,
0095     /* Diagnostic Commands */
0096     MYRB_CMD_SET_DIAGNOSTIC_MODE =  0x31,
0097     MYRB_CMD_RUN_DIAGNOSTIC =   0x32,
0098     /* Subsystem Service Commands */
0099     MYRB_CMD_GET_SUBSYS_DATA =  0x70,
0100     MYRB_CMD_SET_SUBSYS_PARAM = 0x71,
0101     /* Version 2.xx Firmware Commands */
0102     MYRB_CMD_ENQUIRY_OLD =      0x05,
0103     MYRB_CMD_GET_DEVICE_STATE_OLD = 0x14,
0104     MYRB_CMD_READ_OLD =     0x02,
0105     MYRB_CMD_WRITE_OLD =        0x03,
0106     MYRB_CMD_READ_SG_OLD =      0x82,
0107     MYRB_CMD_WRITE_SG_OLD =     0x83
0108 } __packed;
0109 
0110 /*
0111  * DAC960 V1 Firmware Command Status Codes.
0112  */
0113 #define MYRB_STATUS_SUCCESS         0x0000  /* Common */
0114 #define MYRB_STATUS_CHECK_CONDITION     0x0002  /* Common */
0115 #define MYRB_STATUS_NO_DEVICE           0x0102  /* Common */
0116 #define MYRB_STATUS_INVALID_ADDRESS     0x0105  /* Common */
0117 #define MYRB_STATUS_INVALID_PARAM       0x0105  /* Common */
0118 #define MYRB_STATUS_IRRECOVERABLE_DATA_ERROR    0x0001  /* I/O */
0119 #define MYRB_STATUS_LDRV_NONEXISTENT_OR_OFFLINE 0x0002  /* I/O */
0120 #define MYRB_STATUS_ACCESS_BEYOND_END_OF_LDRV   0x0105  /* I/O */
0121 #define MYRB_STATUS_BAD_DATA            0x010C  /* I/O */
0122 #define MYRB_STATUS_DEVICE_BUSY         0x0008  /* DCDB */
0123 #define MYRB_STATUS_DEVICE_NONRESPONSIVE    0x000E  /* DCDB */
0124 #define MYRB_STATUS_COMMAND_TERMINATED      0x000F  /* DCDB */
0125 #define MYRB_STATUS_START_DEVICE_FAILED     0x0002  /* Device */
0126 #define MYRB_STATUS_INVALID_CHANNEL_OR_TARGET   0x0105  /* Device */
0127 #define MYRB_STATUS_CHANNEL_BUSY        0x0106  /* Device */
0128 #define MYRB_STATUS_OUT_OF_MEMORY       0x0107  /* Device */
0129 #define MYRB_STATUS_CHANNEL_NOT_STOPPED     0x0002  /* Device */
0130 #define MYRB_STATUS_ATTEMPT_TO_RBLD_ONLINE_DRIVE 0x0002 /* Consistency */
0131 #define MYRB_STATUS_RBLD_BADBLOCKS      0x0003  /* Consistency */
0132 #define MYRB_STATUS_RBLD_NEW_DISK_FAILED    0x0004  /* Consistency */
0133 #define MYRB_STATUS_RBLD_OR_CHECK_INPROGRESS    0x0106  /* Consistency */
0134 #define MYRB_STATUS_DEPENDENT_DISK_DEAD     0x0002  /* Consistency */
0135 #define MYRB_STATUS_INCONSISTENT_BLOCKS     0x0003  /* Consistency */
0136 #define MYRB_STATUS_INVALID_OR_NONREDUNDANT_LDRV 0x0105 /* Consistency */
0137 #define MYRB_STATUS_NO_RBLD_OR_CHECK_INPROGRESS 0x0105  /* Consistency */
0138 #define MYRB_STATUS_RBLD_IN_PROGRESS_DATA_VALID 0x0000  /* Consistency */
0139 #define MYRB_STATUS_RBLD_FAILED_LDEV_FAILURE    0x0002  /* Consistency */
0140 #define MYRB_STATUS_RBLD_FAILED_BADBLOCKS   0x0003  /* Consistency */
0141 #define MYRB_STATUS_RBLD_FAILED_NEW_DRIVE_FAILED 0x0004 /* Consistency */
0142 #define MYRB_STATUS_RBLD_SUCCESS        0x0100  /* Consistency */
0143 #define MYRB_STATUS_RBLD_SUCCESS_TERMINATED 0x0107  /* Consistency */
0144 #define MYRB_STATUS_RBLD_NOT_CHECKED        0x0108  /* Consistency */
0145 #define MYRB_STATUS_BGI_SUCCESS         0x0100  /* Consistency */
0146 #define MYRB_STATUS_BGI_ABORTED         0x0005  /* Consistency */
0147 #define MYRB_STATUS_NO_BGI_INPROGRESS       0x0105  /* Consistency */
0148 #define MYRB_STATUS_ADD_CAPACITY_INPROGRESS 0x0004  /* Consistency */
0149 #define MYRB_STATUS_ADD_CAPACITY_FAILED_OR_SUSPENDED 0x00F4 /* Consistency */
0150 #define MYRB_STATUS_CONFIG2_CSUM_ERROR      0x0002  /* Configuration */
0151 #define MYRB_STATUS_CONFIGURATION_SUSPENDED 0x0106  /* Configuration */
0152 #define MYRB_STATUS_FAILED_TO_CONFIGURE_NVRAM   0x0105  /* Configuration */
0153 #define MYRB_STATUS_CONFIGURATION_NOT_SAVED 0x0106  /* Configuration */
0154 #define MYRB_STATUS_SUBSYS_NOTINSTALLED     0x0001  /* Subsystem */
0155 #define MYRB_STATUS_SUBSYS_FAILED       0x0002  /* Subsystem */
0156 #define MYRB_STATUS_SUBSYS_BUSY         0x0106  /* Subsystem */
0157 #define MYRB_STATUS_SUBSYS_TIMEOUT      0x0108  /* Subsystem */
0158 
0159 /*
0160  * DAC960 V1 Firmware Enquiry Command reply structure.
0161  */
0162 struct myrb_enquiry {
0163     unsigned char ldev_count;           /* Byte 0 */
0164     unsigned int rsvd1:24;              /* Bytes 1-3 */
0165     unsigned int ldev_sizes[32];            /* Bytes 4-131 */
0166     unsigned short flash_age;           /* Bytes 132-133 */
0167     struct {
0168         unsigned char deferred:1;       /* Byte 134 Bit 0 */
0169         unsigned char low_bat:1;        /* Byte 134 Bit 1 */
0170         unsigned char rsvd2:6;          /* Byte 134 Bits 2-7 */
0171     } status;
0172     unsigned char rsvd3:8;              /* Byte 135 */
0173     unsigned char fw_minor_version;         /* Byte 136 */
0174     unsigned char fw_major_version;         /* Byte 137 */
0175     enum {
0176         MYRB_NO_STDBY_RBLD_OR_CHECK_IN_PROGRESS =   0x00,
0177         MYRB_STDBY_RBLD_IN_PROGRESS =           0x01,
0178         MYRB_BG_RBLD_IN_PROGRESS =          0x02,
0179         MYRB_BG_CHECK_IN_PROGRESS =         0x03,
0180         MYRB_STDBY_RBLD_COMPLETED_WITH_ERROR =      0xFF,
0181         MYRB_BG_RBLD_OR_CHECK_FAILED_DRIVE_FAILED = 0xF0,
0182         MYRB_BG_RBLD_OR_CHECK_FAILED_LDEV_FAILED =  0xF1,
0183         MYRB_BG_RBLD_OR_CHECK_FAILED_OTHER =        0xF2,
0184         MYRB_BG_RBLD_OR_CHECK_SUCCESS_TERMINATED =  0xF3
0185     } __packed rbld;        /* Byte 138 */
0186     unsigned char max_tcq;              /* Byte 139 */
0187     unsigned char ldev_offline;         /* Byte 140 */
0188     unsigned char rsvd4:8;              /* Byte 141 */
0189     unsigned short ev_seq;              /* Bytes 142-143 */
0190     unsigned char ldev_critical;            /* Byte 144 */
0191     unsigned int rsvd5:24;              /* Bytes 145-147 */
0192     unsigned char pdev_dead;            /* Byte 148 */
0193     unsigned char rsvd6:8;              /* Byte 149 */
0194     unsigned char rbld_count;           /* Byte 150 */
0195     struct {
0196         unsigned char rsvd7:3;          /* Byte 151 Bits 0-2 */
0197         unsigned char bbu_present:1;        /* Byte 151 Bit 3 */
0198         unsigned char rsvd8:4;          /* Byte 151 Bits 4-7 */
0199     } misc;
0200     struct {
0201         unsigned char target;
0202         unsigned char channel;
0203     } dead_drives[21];              /* Bytes 152-194 */
0204     unsigned char rsvd9[62];            /* Bytes 195-255 */
0205 } __packed;
0206 
0207 /*
0208  * DAC960 V1 Firmware Enquiry2 Command reply structure.
0209  */
0210 struct myrb_enquiry2 {
0211     struct {
0212         enum {
0213             DAC960_V1_P_PD_PU =         0x01,
0214             DAC960_V1_PL =              0x02,
0215             DAC960_V1_PG =              0x10,
0216             DAC960_V1_PJ =              0x11,
0217             DAC960_V1_PR =              0x12,
0218             DAC960_V1_PT =              0x13,
0219             DAC960_V1_PTL0 =            0x14,
0220             DAC960_V1_PRL =             0x15,
0221             DAC960_V1_PTL1 =            0x16,
0222             DAC960_V1_1164P =           0x20
0223         } __packed sub_model;       /* Byte 0 */
0224         unsigned char actual_channels;          /* Byte 1 */
0225         enum {
0226             MYRB_5_CHANNEL_BOARD =      0x01,
0227             MYRB_3_CHANNEL_BOARD =      0x02,
0228             MYRB_2_CHANNEL_BOARD =      0x03,
0229             MYRB_3_CHANNEL_ASIC_DAC =   0x04
0230         } __packed model;       /* Byte 2 */
0231         enum {
0232             MYRB_EISA_CONTROLLER =      0x01,
0233             MYRB_MCA_CONTROLLER =       0x02,
0234             MYRB_PCI_CONTROLLER =       0x03,
0235             MYRB_SCSI_TO_SCSI =     0x08
0236         } __packed controller;  /* Byte 3 */
0237     } hw;                       /* Bytes 0-3 */
0238     /* MajorVersion.MinorVersion-FirmwareType-TurnID */
0239     struct {
0240         unsigned char major_version;        /* Byte 4 */
0241         unsigned char minor_version;        /* Byte 5 */
0242         unsigned char turn_id;          /* Byte 6 */
0243         char firmware_type;         /* Byte 7 */
0244     } fw;                       /* Bytes 4-7 */
0245     unsigned int rsvd1;             /* Byte 8-11 */
0246     unsigned char cfg_chan;             /* Byte 12 */
0247     unsigned char cur_chan;             /* Byte 13 */
0248     unsigned char max_targets;          /* Byte 14 */
0249     unsigned char max_tcq;              /* Byte 15 */
0250     unsigned char max_ldev;             /* Byte 16 */
0251     unsigned char max_arms;             /* Byte 17 */
0252     unsigned char max_spans;            /* Byte 18 */
0253     unsigned char rsvd2;                /* Byte 19 */
0254     unsigned int rsvd3;             /* Bytes 20-23 */
0255     unsigned int mem_size;              /* Bytes 24-27 */
0256     unsigned int cache_size;            /* Bytes 28-31 */
0257     unsigned int flash_size;            /* Bytes 32-35 */
0258     unsigned int nvram_size;            /* Bytes 36-39 */
0259     struct {
0260         enum {
0261             MYRB_RAM_TYPE_DRAM =        0x0,
0262             MYRB_RAM_TYPE_EDO =         0x1,
0263             MYRB_RAM_TYPE_SDRAM =       0x2,
0264             MYRB_RAM_TYPE_Last =        0x7
0265         } __packed ram:3;   /* Byte 40 Bits 0-2 */
0266         enum {
0267             MYRB_ERR_CORR_None =    0x0,
0268             MYRB_ERR_CORR_Parity =  0x1,
0269             MYRB_ERR_CORR_ECC =     0x2,
0270             MYRB_ERR_CORR_Last =    0x7
0271         } __packed ec:3;    /* Byte 40 Bits 3-5 */
0272         unsigned char fast_page:1;      /* Byte 40 Bit 6 */
0273         unsigned char low_power:1;      /* Byte 40 Bit 7 */
0274         unsigned char rsvd4;            /* Bytes 41 */
0275     } mem_type;
0276     unsigned short clock_speed;         /* Bytes 42-43 */
0277     unsigned short mem_speed;           /* Bytes 44-45 */
0278     unsigned short hw_speed;            /* Bytes 46-47 */
0279     unsigned char rsvd5[12];            /* Bytes 48-59 */
0280     unsigned short max_cmds;            /* Bytes 60-61 */
0281     unsigned short max_sge;             /* Bytes 62-63 */
0282     unsigned short max_drv_cmds;            /* Bytes 64-65 */
0283     unsigned short max_io_desc;         /* Bytes 66-67 */
0284     unsigned short max_sectors;         /* Bytes 68-69 */
0285     unsigned char latency;              /* Byte 70 */
0286     unsigned char rsvd6;                /* Byte 71 */
0287     unsigned char scsi_tmo;             /* Byte 72 */
0288     unsigned char rsvd7;                /* Byte 73 */
0289     unsigned short min_freelines;           /* Bytes 74-75 */
0290     unsigned char rsvd8[8];             /* Bytes 76-83 */
0291     unsigned char rbld_rate_const;          /* Byte 84 */
0292     unsigned char rsvd9[11];            /* Byte 85-95 */
0293     unsigned short pdrv_block_size;         /* Bytes 96-97 */
0294     unsigned short ldev_block_size;         /* Bytes 98-99 */
0295     unsigned short max_blocks_per_cmd;      /* Bytes 100-101 */
0296     unsigned short block_factor;            /* Bytes 102-103 */
0297     unsigned short cacheline_size;          /* Bytes 104-105 */
0298     struct {
0299         enum {
0300             MYRB_WIDTH_NARROW_8BIT =        0x0,
0301             MYRB_WIDTH_WIDE_16BIT =         0x1,
0302             MYRB_WIDTH_WIDE_32BIT =         0x2
0303         } __packed bus_width:2; /* Byte 106 Bits 0-1 */
0304         enum {
0305             MYRB_SCSI_SPEED_FAST =          0x0,
0306             MYRB_SCSI_SPEED_ULTRA =         0x1,
0307             MYRB_SCSI_SPEED_ULTRA2 =        0x2
0308         } __packed bus_speed:2; /* Byte 106 Bits 2-3 */
0309         unsigned char differential:1;       /* Byte 106 Bit 4 */
0310         unsigned char rsvd10:3;         /* Byte 106 Bits 5-7 */
0311     } scsi_cap;
0312     unsigned char rsvd11[5];            /* Byte 107-111 */
0313     unsigned short fw_build;            /* Bytes 112-113 */
0314     enum {
0315         MYRB_FAULT_AEMI =               0x01,
0316         MYRB_FAULT_OEM1 =               0x02,
0317         MYRB_FAULT_OEM2 =               0x04,
0318         MYRB_FAULT_OEM3 =               0x08,
0319         MYRB_FAULT_CONNER =             0x10,
0320         MYRB_FAULT_SAFTE =              0x20
0321     } __packed fault_mgmt;      /* Byte 114 */
0322     unsigned char rsvd12;               /* Byte 115 */
0323     struct {
0324         unsigned int clustering:1;      /* Byte 116 Bit 0 */
0325         unsigned int online_RAID_expansion:1;   /* Byte 116 Bit 1 */
0326         unsigned int readahead:1;       /* Byte 116 Bit 2 */
0327         unsigned int bgi:1;         /* Byte 116 Bit 3 */
0328         unsigned int rsvd13:28;         /* Bytes 116-119 */
0329     } fw_features;
0330     unsigned char rsvd14[8];            /* Bytes 120-127 */
0331 } __packed;
0332 
0333 /*
0334  * DAC960 V1 Firmware Logical Drive State type.
0335  */
0336 enum myrb_devstate {
0337     MYRB_DEVICE_DEAD =      0x00,
0338     MYRB_DEVICE_WO =        0x02,
0339     MYRB_DEVICE_ONLINE =        0x03,
0340     MYRB_DEVICE_CRITICAL =      0x04,
0341     MYRB_DEVICE_STANDBY =       0x10,
0342     MYRB_DEVICE_OFFLINE =       0xFF
0343 } __packed;
0344 
0345 /*
0346  * DAC960 V1 RAID Levels
0347  */
0348 enum myrb_raidlevel {
0349     MYRB_RAID_LEVEL0 =      0x0,     /* RAID 0 */
0350     MYRB_RAID_LEVEL1 =      0x1,     /* RAID 1 */
0351     MYRB_RAID_LEVEL3 =      0x3,     /* RAID 3 */
0352     MYRB_RAID_LEVEL5 =      0x5,     /* RAID 5 */
0353     MYRB_RAID_LEVEL6 =      0x6,     /* RAID 6 */
0354     MYRB_RAID_JBOD =        0x7,     /* RAID 7 (JBOD) */
0355 } __packed;
0356 
0357 /*
0358  * DAC960 V1 Firmware Logical Drive Information structure.
0359  */
0360 struct myrb_ldev_info {
0361     unsigned int size;              /* Bytes 0-3 */
0362     enum myrb_devstate state;           /* Byte 4 */
0363     unsigned int raid_level:7;          /* Byte 5 Bits 0-6 */
0364     unsigned int wb_enabled:1;          /* Byte 5 Bit 7 */
0365     unsigned int rsvd:16;               /* Bytes 6-7 */
0366 };
0367 
0368 /*
0369  * DAC960 V1 Firmware Perform Event Log Operation Types.
0370  */
0371 #define DAC960_V1_GetEventLogEntry      0x00
0372 
0373 /*
0374  * DAC960 V1 Firmware Get Event Log Entry Command reply structure.
0375  */
0376 struct myrb_log_entry {
0377     unsigned char msg_type;         /* Byte 0 */
0378     unsigned char msg_len;          /* Byte 1 */
0379     unsigned char target:5;         /* Byte 2 Bits 0-4 */
0380     unsigned char channel:3;        /* Byte 2 Bits 5-7 */
0381     unsigned char lun:6;            /* Byte 3 Bits 0-5 */
0382     unsigned char rsvd1:2;          /* Byte 3 Bits 6-7 */
0383     unsigned short seq_num;         /* Bytes 4-5 */
0384     unsigned char sense[26];        /* Bytes 6-31 */
0385 };
0386 
0387 /*
0388  * DAC960 V1 Firmware Get Device State Command reply structure.
0389  * The structure is padded by 2 bytes for compatibility with Version 2.xx
0390  * Firmware.
0391  */
0392 struct myrb_pdev_state {
0393     unsigned int present:1;         /* Byte 0 Bit 0 */
0394     unsigned int :7;                /* Byte 0 Bits 1-7 */
0395     enum {
0396         MYRB_TYPE_OTHER =           0x0,
0397         MYRB_TYPE_DISK =            0x1,
0398         MYRB_TYPE_TAPE =            0x2,
0399         MYRB_TYPE_CDROM_OR_WORM =       0x3
0400     } __packed devtype:2;       /* Byte 1 Bits 0-1 */
0401     unsigned int rsvd1:1;               /* Byte 1 Bit 2 */
0402     unsigned int fast20:1;              /* Byte 1 Bit 3 */
0403     unsigned int sync:1;                /* Byte 1 Bit 4 */
0404     unsigned int fast:1;                /* Byte 1 Bit 5 */
0405     unsigned int wide:1;                /* Byte 1 Bit 6 */
0406     unsigned int tcq_supported:1;           /* Byte 1 Bit 7 */
0407     enum myrb_devstate state;           /* Byte 2 */
0408     unsigned int rsvd2:8;               /* Byte 3 */
0409     unsigned int sync_multiplier;           /* Byte 4 */
0410     unsigned int sync_offset:5;         /* Byte 5 Bits 0-4 */
0411     unsigned int rsvd3:3;               /* Byte 5 Bits 5-7 */
0412     unsigned int size;              /* Bytes 6-9 */
0413     unsigned int rsvd4:16;          /* Bytes 10-11 */
0414 } __packed;
0415 
0416 /*
0417  * DAC960 V1 Firmware Get Rebuild Progress Command reply structure.
0418  */
0419 struct myrb_rbld_progress {
0420     unsigned int ldev_num;              /* Bytes 0-3 */
0421     unsigned int ldev_size;             /* Bytes 4-7 */
0422     unsigned int blocks_left;           /* Bytes 8-11 */
0423 };
0424 
0425 /*
0426  * DAC960 V1 Firmware Background Initialization Status Command reply structure.
0427  */
0428 struct myrb_bgi_status {
0429     unsigned int ldev_size;             /* Bytes 0-3 */
0430     unsigned int blocks_done;           /* Bytes 4-7 */
0431     unsigned char rsvd1[12];            /* Bytes 8-19 */
0432     unsigned int ldev_num;              /* Bytes 20-23 */
0433     unsigned char raid_level;           /* Byte 24 */
0434     enum {
0435         MYRB_BGI_INVALID =  0x00,
0436         MYRB_BGI_STARTED =  0x02,
0437         MYRB_BGI_INPROGRESS =   0x04,
0438         MYRB_BGI_SUSPENDED =    0x05,
0439         MYRB_BGI_CANCELLED =    0x06
0440     } __packed status;      /* Byte 25 */
0441     unsigned char rsvd2[6];             /* Bytes 26-31 */
0442 };
0443 
0444 /*
0445  * DAC960 V1 Firmware Error Table Entry structure.
0446  */
0447 struct myrb_error_entry {
0448     unsigned char parity_err;           /* Byte 0 */
0449     unsigned char soft_err;             /* Byte 1 */
0450     unsigned char hard_err;             /* Byte 2 */
0451     unsigned char misc_err;             /* Byte 3 */
0452 };
0453 
0454 /*
0455  * DAC960 V1 Firmware Read Config2 Command reply structure.
0456  */
0457 struct myrb_config2 {
0458     unsigned rsvd1:1;               /* Byte 0 Bit 0 */
0459     unsigned active_negation:1;         /* Byte 0 Bit 1 */
0460     unsigned rsvd2:5;               /* Byte 0 Bits 2-6 */
0461     unsigned no_rescan_on_reset_during_scan:1;  /* Byte 0 Bit 7 */
0462     unsigned StorageWorks_support:1;        /* Byte 1 Bit 0 */
0463     unsigned HewlettPackard_support:1;      /* Byte 1 Bit 1 */
0464     unsigned no_disconnect_on_first_command:1;  /* Byte 1 Bit 2 */
0465     unsigned rsvd3:2;               /* Byte 1 Bits 3-4 */
0466     unsigned AEMI_ARM:1;                /* Byte 1 Bit 5 */
0467     unsigned AEMI_OFM:1;                /* Byte 1 Bit 6 */
0468     unsigned rsvd4:1;               /* Byte 1 Bit 7 */
0469     enum {
0470         MYRB_OEMID_MYLEX =      0x00,
0471         MYRB_OEMID_IBM =        0x08,
0472         MYRB_OEMID_HP =         0x0A,
0473         MYRB_OEMID_DEC =        0x0C,
0474         MYRB_OEMID_SIEMENS =        0x10,
0475         MYRB_OEMID_INTEL =      0x12
0476     } __packed OEMID;       /* Byte 2 */
0477     unsigned char oem_model_number;         /* Byte 3 */
0478     unsigned char physical_sector;          /* Byte 4 */
0479     unsigned char logical_sector;           /* Byte 5 */
0480     unsigned char block_factor;         /* Byte 6 */
0481     unsigned readahead_enabled:1;           /* Byte 7 Bit 0 */
0482     unsigned low_BIOS_delay:1;          /* Byte 7 Bit 1 */
0483     unsigned rsvd5:2;               /* Byte 7 Bits 2-3 */
0484     unsigned restrict_reassign_to_one_sector:1; /* Byte 7 Bit 4 */
0485     unsigned rsvd6:1;               /* Byte 7 Bit 5 */
0486     unsigned FUA_during_write_recovery:1;       /* Byte 7 Bit 6 */
0487     unsigned enable_LeftSymmetricRAID5Algorithm:1;  /* Byte 7 Bit 7 */
0488     unsigned char default_rebuild_rate;     /* Byte 8 */
0489     unsigned char rsvd7;                /* Byte 9 */
0490     unsigned char blocks_per_cacheline;     /* Byte 10 */
0491     unsigned char blocks_per_stripe;        /* Byte 11 */
0492     struct {
0493         enum {
0494             MYRB_SPEED_ASYNC =      0x0,
0495             MYRB_SPEED_SYNC_8MHz =      0x1,
0496             MYRB_SPEED_SYNC_5MHz =      0x2,
0497             MYRB_SPEED_SYNC_10_OR_20MHz =   0x3
0498         } __packed speed:2; /* Byte 11 Bits 0-1 */
0499         unsigned force_8bit:1;          /* Byte 11 Bit 2 */
0500         unsigned disable_fast20:1;      /* Byte 11 Bit 3 */
0501         unsigned rsvd8:3;           /* Byte 11 Bits 4-6 */
0502         unsigned enable_tcq:1;          /* Byte 11 Bit 7 */
0503     } __packed channelparam[6]; /* Bytes 12-17 */
0504     unsigned char SCSIInitiatorID;          /* Byte 18 */
0505     unsigned char rsvd9;                /* Byte 19 */
0506     enum {
0507         MYRB_STARTUP_CONTROLLER_SPINUP =    0x00,
0508         MYRB_STARTUP_POWERON_SPINUP =       0x01
0509     } __packed startup;     /* Byte 20 */
0510     unsigned char simultaneous_device_spinup_count; /* Byte 21 */
0511     unsigned char seconds_delay_between_spinups;    /* Byte 22 */
0512     unsigned char rsvd10[29];           /* Bytes 23-51 */
0513     unsigned BIOS_disabled:1;           /* Byte 52 Bit 0 */
0514     unsigned CDROM_boot_enabled:1;          /* Byte 52 Bit 1 */
0515     unsigned rsvd11:3;              /* Byte 52 Bits 2-4 */
0516     enum {
0517         MYRB_GEOM_128_32 =      0x0,
0518         MYRB_GEOM_255_63 =      0x1,
0519         MYRB_GEOM_RESERVED1 =       0x2,
0520         MYRB_GEOM_RESERVED2 =       0x3
0521     } __packed drive_geometry:2;    /* Byte 52 Bits 5-6 */
0522     unsigned rsvd12:1;              /* Byte 52 Bit 7 */
0523     unsigned char rsvd13[9];            /* Bytes 53-61 */
0524     unsigned short csum;                /* Bytes 62-63 */
0525 };
0526 
0527 /*
0528  * DAC960 V1 Firmware DCDB request structure.
0529  */
0530 struct myrb_dcdb {
0531     unsigned target:4;               /* Byte 0 Bits 0-3 */
0532     unsigned channel:4;              /* Byte 0 Bits 4-7 */
0533     enum {
0534         MYRB_DCDB_XFER_NONE =       0,
0535         MYRB_DCDB_XFER_DEVICE_TO_SYSTEM = 1,
0536         MYRB_DCDB_XFER_SYSTEM_TO_DEVICE = 2,
0537         MYRB_DCDB_XFER_ILLEGAL =    3
0538     } __packed data_xfer:2;             /* Byte 1 Bits 0-1 */
0539     unsigned early_status:1;            /* Byte 1 Bit 2 */
0540     unsigned rsvd1:1;               /* Byte 1 Bit 3 */
0541     enum {
0542         MYRB_DCDB_TMO_24_HRS =  0,
0543         MYRB_DCDB_TMO_10_SECS = 1,
0544         MYRB_DCDB_TMO_60_SECS = 2,
0545         MYRB_DCDB_TMO_10_MINS = 3
0546     } __packed timeout:2;               /* Byte 1 Bits 4-5 */
0547     unsigned no_autosense:1;            /* Byte 1 Bit 6 */
0548     unsigned allow_disconnect:1;            /* Byte 1 Bit 7 */
0549     unsigned short xfer_len_lo;         /* Bytes 2-3 */
0550     u32 dma_addr;                   /* Bytes 4-7 */
0551     unsigned char cdb_len:4;            /* Byte 8 Bits 0-3 */
0552     unsigned char xfer_len_hi4:4;           /* Byte 8 Bits 4-7 */
0553     unsigned char sense_len;            /* Byte 9 */
0554     unsigned char cdb[12];              /* Bytes 10-21 */
0555     unsigned char sense[64];            /* Bytes 22-85 */
0556     unsigned char status;               /* Byte 86 */
0557     unsigned char rsvd2;                /* Byte 87 */
0558 };
0559 
0560 /*
0561  * DAC960 V1 Firmware Scatter/Gather List Type 1 32 Bit Address
0562  *32 Bit Byte Count structure.
0563  */
0564 struct myrb_sge {
0565     u32 sge_addr;       /* Bytes 0-3 */
0566     u32 sge_count;      /* Bytes 4-7 */
0567 };
0568 
0569 /*
0570  * 13 Byte DAC960 V1 Firmware Command Mailbox structure.
0571  * Bytes 13-15 are not used.  The structure is padded to 16 bytes for
0572  * efficient access.
0573  */
0574 union myrb_cmd_mbox {
0575     unsigned int words[4];              /* Words 0-3 */
0576     unsigned char bytes[16];            /* Bytes 0-15 */
0577     struct {
0578         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0579         unsigned char id;           /* Byte 1 */
0580         unsigned char rsvd[14];         /* Bytes 2-15 */
0581     } __packed common;
0582     struct {
0583         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0584         unsigned char id;           /* Byte 1 */
0585         unsigned char rsvd1[6];         /* Bytes 2-7 */
0586         u32 addr;               /* Bytes 8-11 */
0587         unsigned char rsvd2[4];         /* Bytes 12-15 */
0588     } __packed type3;
0589     struct {
0590         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0591         unsigned char id;           /* Byte 1 */
0592         unsigned char optype;           /* Byte 2 */
0593         unsigned char rsvd1[5];         /* Bytes 3-7 */
0594         u32 addr;               /* Bytes 8-11 */
0595         unsigned char rsvd2[4];         /* Bytes 12-15 */
0596     } __packed type3B;
0597     struct {
0598         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0599         unsigned char id;           /* Byte 1 */
0600         unsigned char rsvd1[5];         /* Bytes 2-6 */
0601         unsigned char ldev_num:6;       /* Byte 7 Bits 0-6 */
0602         unsigned char auto_restore:1;       /* Byte 7 Bit 7 */
0603         unsigned char rsvd2[8];         /* Bytes 8-15 */
0604     } __packed type3C;
0605     struct {
0606         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0607         unsigned char id;           /* Byte 1 */
0608         unsigned char channel;          /* Byte 2 */
0609         unsigned char target;           /* Byte 3 */
0610         enum myrb_devstate state;       /* Byte 4 */
0611         unsigned char rsvd1[3];         /* Bytes 5-7 */
0612         u32 addr;               /* Bytes 8-11 */
0613         unsigned char rsvd2[4];         /* Bytes 12-15 */
0614     } __packed type3D;
0615     struct {
0616         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0617         unsigned char id;           /* Byte 1 */
0618         unsigned char optype;           /* Byte 2 */
0619         unsigned char opqual;           /* Byte 3 */
0620         unsigned short ev_seq;          /* Bytes 4-5 */
0621         unsigned char rsvd1[2];         /* Bytes 6-7 */
0622         u32 addr;               /* Bytes 8-11 */
0623         unsigned char rsvd2[4];         /* Bytes 12-15 */
0624     } __packed type3E;
0625     struct {
0626         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0627         unsigned char id;           /* Byte 1 */
0628         unsigned char rsvd1[2];         /* Bytes 2-3 */
0629         unsigned char rbld_rate;        /* Byte 4 */
0630         unsigned char rsvd2[3];         /* Bytes 5-7 */
0631         u32 addr;               /* Bytes 8-11 */
0632         unsigned char rsvd3[4];         /* Bytes 12-15 */
0633     } __packed type3R;
0634     struct {
0635         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0636         unsigned char id;           /* Byte 1 */
0637         unsigned short xfer_len;        /* Bytes 2-3 */
0638         unsigned int lba;           /* Bytes 4-7 */
0639         u32 addr;               /* Bytes 8-11 */
0640         unsigned char ldev_num;         /* Byte 12 */
0641         unsigned char rsvd[3];          /* Bytes 13-15 */
0642     } __packed type4;
0643     struct {
0644         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0645         unsigned char id;           /* Byte 1 */
0646         struct {
0647             unsigned short xfer_len:11; /* Bytes 2-3 */
0648             unsigned char ldev_num:5;   /* Byte 3 Bits 3-7 */
0649         } __packed ld;
0650         unsigned int lba;           /* Bytes 4-7 */
0651         u32 addr;               /* Bytes 8-11 */
0652         unsigned char sg_count:6;       /* Byte 12 Bits 0-5 */
0653         enum {
0654             MYRB_SGL_ADDR32_COUNT32 = 0x0,
0655             MYRB_SGL_ADDR32_COUNT16 = 0x1,
0656             MYRB_SGL_COUNT32_ADDR32 = 0x2,
0657             MYRB_SGL_COUNT16_ADDR32 = 0x3
0658         } __packed sg_type:2;   /* Byte 12 Bits 6-7 */
0659         unsigned char rsvd[3];          /* Bytes 13-15 */
0660     } __packed type5;
0661     struct {
0662         enum myrb_cmd_opcode opcode;        /* Byte 0 */
0663         unsigned char id;           /* Byte 1 */
0664         unsigned char opcode2;          /* Byte 2 */
0665         unsigned char rsvd1:8;          /* Byte 3 */
0666         u32 cmd_mbox_addr;          /* Bytes 4-7 */
0667         u32 stat_mbox_addr;         /* Bytes 8-11 */
0668         unsigned char rsvd2[4];         /* Bytes 12-15 */
0669     } __packed typeX;
0670 };
0671 
0672 /*
0673  * DAC960 V1 Firmware Controller Status Mailbox structure.
0674  */
0675 struct myrb_stat_mbox {
0676     unsigned char id;       /* Byte 0 */
0677     unsigned char rsvd:7;       /* Byte 1 Bits 0-6 */
0678     unsigned char valid:1;          /* Byte 1 Bit 7 */
0679     unsigned short status;      /* Bytes 2-3 */
0680 };
0681 
0682 struct myrb_cmdblk {
0683     union myrb_cmd_mbox mbox;
0684     unsigned short status;
0685     struct completion *completion;
0686     struct myrb_dcdb *dcdb;
0687     dma_addr_t dcdb_addr;
0688     struct myrb_sge *sgl;
0689     dma_addr_t sgl_addr;
0690 };
0691 
0692 struct myrb_hba {
0693     unsigned int ldev_block_size;
0694     unsigned char ldev_geom_heads;
0695     unsigned char ldev_geom_sectors;
0696     unsigned char bus_width;
0697     unsigned short stripe_size;
0698     unsigned short segment_size;
0699     unsigned short new_ev_seq;
0700     unsigned short old_ev_seq;
0701     bool dual_mode_interface;
0702     bool bgi_status_supported;
0703     bool safte_enabled;
0704     bool need_ldev_info;
0705     bool need_err_info;
0706     bool need_rbld;
0707     bool need_cc_status;
0708     bool need_bgi_status;
0709     bool rbld_first;
0710 
0711     struct pci_dev *pdev;
0712     struct Scsi_Host *host;
0713 
0714     struct workqueue_struct *work_q;
0715     char work_q_name[20];
0716     struct delayed_work monitor_work;
0717     unsigned long primary_monitor_time;
0718     unsigned long secondary_monitor_time;
0719 
0720     struct dma_pool *sg_pool;
0721     struct dma_pool *dcdb_pool;
0722 
0723     spinlock_t queue_lock;
0724 
0725     void (*qcmd)(struct myrb_hba *cs, struct myrb_cmdblk *cmd_blk);
0726     void (*write_cmd_mbox)(union myrb_cmd_mbox *next_mbox,
0727                    union myrb_cmd_mbox *cmd_mbox);
0728     void (*get_cmd_mbox)(void __iomem *base);
0729     void (*disable_intr)(void __iomem *base);
0730     void (*reset)(void __iomem *base);
0731 
0732     unsigned int ctlr_num;
0733     unsigned char model_name[20];
0734     unsigned char fw_version[12];
0735 
0736     unsigned int irq;
0737     phys_addr_t io_addr;
0738     phys_addr_t pci_addr;
0739     void __iomem *io_base;
0740     void __iomem *mmio_base;
0741 
0742     size_t cmd_mbox_size;
0743     dma_addr_t cmd_mbox_addr;
0744     union myrb_cmd_mbox *first_cmd_mbox;
0745     union myrb_cmd_mbox *last_cmd_mbox;
0746     union myrb_cmd_mbox *next_cmd_mbox;
0747     union myrb_cmd_mbox *prev_cmd_mbox1;
0748     union myrb_cmd_mbox *prev_cmd_mbox2;
0749 
0750     size_t stat_mbox_size;
0751     dma_addr_t stat_mbox_addr;
0752     struct myrb_stat_mbox *first_stat_mbox;
0753     struct myrb_stat_mbox *last_stat_mbox;
0754     struct myrb_stat_mbox *next_stat_mbox;
0755 
0756     struct myrb_cmdblk dcmd_blk;
0757     struct myrb_cmdblk mcmd_blk;
0758     struct mutex dcmd_mutex;
0759 
0760     struct myrb_enquiry *enquiry;
0761     dma_addr_t enquiry_addr;
0762 
0763     struct myrb_error_entry *err_table;
0764     dma_addr_t err_table_addr;
0765 
0766     unsigned short last_rbld_status;
0767 
0768     struct myrb_ldev_info *ldev_info_buf;
0769     dma_addr_t ldev_info_addr;
0770 
0771     struct myrb_bgi_status bgi_status;
0772 
0773     struct mutex dma_mutex;
0774 };
0775 
0776 /*
0777  * DAC960 LA Series Controller Interface Register Offsets.
0778  */
0779 #define DAC960_LA_mmio_size     0x80
0780 
0781 enum DAC960_LA_reg_offset {
0782     DAC960_LA_IRQMASK_OFFSET    = 0x34,
0783     DAC960_LA_CMDOP_OFFSET      = 0x50,
0784     DAC960_LA_CMDID_OFFSET      = 0x51,
0785     DAC960_LA_MBOX2_OFFSET      = 0x52,
0786     DAC960_LA_MBOX3_OFFSET      = 0x53,
0787     DAC960_LA_MBOX4_OFFSET      = 0x54,
0788     DAC960_LA_MBOX5_OFFSET      = 0x55,
0789     DAC960_LA_MBOX6_OFFSET      = 0x56,
0790     DAC960_LA_MBOX7_OFFSET      = 0x57,
0791     DAC960_LA_MBOX8_OFFSET      = 0x58,
0792     DAC960_LA_MBOX9_OFFSET      = 0x59,
0793     DAC960_LA_MBOX10_OFFSET     = 0x5A,
0794     DAC960_LA_MBOX11_OFFSET     = 0x5B,
0795     DAC960_LA_MBOX12_OFFSET     = 0x5C,
0796     DAC960_LA_STSID_OFFSET      = 0x5D,
0797     DAC960_LA_STS_OFFSET        = 0x5E,
0798     DAC960_LA_IDB_OFFSET        = 0x60,
0799     DAC960_LA_ODB_OFFSET        = 0x61,
0800     DAC960_LA_ERRSTS_OFFSET     = 0x63,
0801 };
0802 
0803 /*
0804  * DAC960 LA Series Inbound Door Bell Register.
0805  */
0806 #define DAC960_LA_IDB_HWMBOX_NEW_CMD 0x01
0807 #define DAC960_LA_IDB_HWMBOX_ACK_STS 0x02
0808 #define DAC960_LA_IDB_GEN_IRQ 0x04
0809 #define DAC960_LA_IDB_CTRL_RESET 0x08
0810 #define DAC960_LA_IDB_MMBOX_NEW_CMD 0x10
0811 
0812 #define DAC960_LA_IDB_HWMBOX_EMPTY 0x01
0813 #define DAC960_LA_IDB_INIT_DONE 0x02
0814 
0815 /*
0816  * DAC960 LA Series Outbound Door Bell Register.
0817  */
0818 #define DAC960_LA_ODB_HWMBOX_ACK_IRQ 0x01
0819 #define DAC960_LA_ODB_MMBOX_ACK_IRQ 0x02
0820 #define DAC960_LA_ODB_HWMBOX_STS_AVAIL 0x01
0821 #define DAC960_LA_ODB_MMBOX_STS_AVAIL 0x02
0822 
0823 /*
0824  * DAC960 LA Series Interrupt Mask Register.
0825  */
0826 #define DAC960_LA_IRQMASK_DISABLE_IRQ 0x04
0827 
0828 /*
0829  * DAC960 LA Series Error Status Register.
0830  */
0831 #define DAC960_LA_ERRSTS_PENDING 0x02
0832 
0833 /*
0834  * DAC960 PG Series Controller Interface Register Offsets.
0835  */
0836 #define DAC960_PG_mmio_size     0x2000
0837 
0838 enum DAC960_PG_reg_offset {
0839     DAC960_PG_IDB_OFFSET        = 0x0020,
0840     DAC960_PG_ODB_OFFSET        = 0x002C,
0841     DAC960_PG_IRQMASK_OFFSET    = 0x0034,
0842     DAC960_PG_CMDOP_OFFSET      = 0x1000,
0843     DAC960_PG_CMDID_OFFSET      = 0x1001,
0844     DAC960_PG_MBOX2_OFFSET      = 0x1002,
0845     DAC960_PG_MBOX3_OFFSET      = 0x1003,
0846     DAC960_PG_MBOX4_OFFSET      = 0x1004,
0847     DAC960_PG_MBOX5_OFFSET      = 0x1005,
0848     DAC960_PG_MBOX6_OFFSET      = 0x1006,
0849     DAC960_PG_MBOX7_OFFSET      = 0x1007,
0850     DAC960_PG_MBOX8_OFFSET      = 0x1008,
0851     DAC960_PG_MBOX9_OFFSET      = 0x1009,
0852     DAC960_PG_MBOX10_OFFSET     = 0x100A,
0853     DAC960_PG_MBOX11_OFFSET     = 0x100B,
0854     DAC960_PG_MBOX12_OFFSET     = 0x100C,
0855     DAC960_PG_STSID_OFFSET      = 0x1018,
0856     DAC960_PG_STS_OFFSET        = 0x101A,
0857     DAC960_PG_ERRSTS_OFFSET     = 0x103F,
0858 };
0859 
0860 /*
0861  * DAC960 PG Series Inbound Door Bell Register.
0862  */
0863 #define DAC960_PG_IDB_HWMBOX_NEW_CMD 0x01
0864 #define DAC960_PG_IDB_HWMBOX_ACK_STS 0x02
0865 #define DAC960_PG_IDB_GEN_IRQ 0x04
0866 #define DAC960_PG_IDB_CTRL_RESET 0x08
0867 #define DAC960_PG_IDB_MMBOX_NEW_CMD 0x10
0868 
0869 #define DAC960_PG_IDB_HWMBOX_FULL 0x01
0870 #define DAC960_PG_IDB_INIT_IN_PROGRESS 0x02
0871 
0872 /*
0873  * DAC960 PG Series Outbound Door Bell Register.
0874  */
0875 #define DAC960_PG_ODB_HWMBOX_ACK_IRQ 0x01
0876 #define DAC960_PG_ODB_MMBOX_ACK_IRQ 0x02
0877 #define DAC960_PG_ODB_HWMBOX_STS_AVAIL 0x01
0878 #define DAC960_PG_ODB_MMBOX_STS_AVAIL 0x02
0879 
0880 /*
0881  * DAC960 PG Series Interrupt Mask Register.
0882  */
0883 #define DAC960_PG_IRQMASK_MSI_MASK1 0x03
0884 #define DAC960_PG_IRQMASK_DISABLE_IRQ 0x04
0885 #define DAC960_PG_IRQMASK_MSI_MASK2 0xF8
0886 
0887 /*
0888  * DAC960 PG Series Error Status Register.
0889  */
0890 #define DAC960_PG_ERRSTS_PENDING 0x04
0891 
0892 /*
0893  * DAC960 PD Series Controller Interface Register Offsets.
0894  */
0895 #define DAC960_PD_mmio_size     0x80
0896 
0897 enum DAC960_PD_reg_offset {
0898     DAC960_PD_CMDOP_OFFSET      = 0x00,
0899     DAC960_PD_CMDID_OFFSET      = 0x01,
0900     DAC960_PD_MBOX2_OFFSET      = 0x02,
0901     DAC960_PD_MBOX3_OFFSET      = 0x03,
0902     DAC960_PD_MBOX4_OFFSET      = 0x04,
0903     DAC960_PD_MBOX5_OFFSET      = 0x05,
0904     DAC960_PD_MBOX6_OFFSET      = 0x06,
0905     DAC960_PD_MBOX7_OFFSET      = 0x07,
0906     DAC960_PD_MBOX8_OFFSET      = 0x08,
0907     DAC960_PD_MBOX9_OFFSET      = 0x09,
0908     DAC960_PD_MBOX10_OFFSET     = 0x0A,
0909     DAC960_PD_MBOX11_OFFSET     = 0x0B,
0910     DAC960_PD_MBOX12_OFFSET     = 0x0C,
0911     DAC960_PD_STSID_OFFSET      = 0x0D,
0912     DAC960_PD_STS_OFFSET        = 0x0E,
0913     DAC960_PD_ERRSTS_OFFSET     = 0x3F,
0914     DAC960_PD_IDB_OFFSET        = 0x40,
0915     DAC960_PD_ODB_OFFSET        = 0x41,
0916     DAC960_PD_IRQEN_OFFSET      = 0x43,
0917 };
0918 
0919 /*
0920  * DAC960 PD Series Inbound Door Bell Register.
0921  */
0922 #define DAC960_PD_IDB_HWMBOX_NEW_CMD 0x01
0923 #define DAC960_PD_IDB_HWMBOX_ACK_STS 0x02
0924 #define DAC960_PD_IDB_GEN_IRQ 0x04
0925 #define DAC960_PD_IDB_CTRL_RESET 0x08
0926 
0927 #define DAC960_PD_IDB_HWMBOX_FULL 0x01
0928 #define DAC960_PD_IDB_INIT_IN_PROGRESS 0x02
0929 
0930 /*
0931  * DAC960 PD Series Outbound Door Bell Register.
0932  */
0933 #define DAC960_PD_ODB_HWMBOX_ACK_IRQ 0x01
0934 #define DAC960_PD_ODB_HWMBOX_STS_AVAIL 0x01
0935 
0936 /*
0937  * DAC960 PD Series Interrupt Enable Register.
0938  */
0939 #define DAC960_PD_IRQMASK_ENABLE_IRQ 0x01
0940 
0941 /*
0942  * DAC960 PD Series Error Status Register.
0943  */
0944 #define DAC960_PD_ERRSTS_PENDING 0x04
0945 
0946 typedef int (*myrb_hw_init_t)(struct pci_dev *pdev,
0947                   struct myrb_hba *cb, void __iomem *base);
0948 typedef unsigned short (*mbox_mmio_init_t)(struct pci_dev *pdev,
0949                        void __iomem *base,
0950                        union myrb_cmd_mbox *mbox);
0951 
0952 struct myrb_privdata {
0953     myrb_hw_init_t      hw_init;
0954     irq_handler_t       irq_handler;
0955     unsigned int        mmio_size;
0956 };
0957 
0958 #endif /* MYRB_H */
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