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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Marvell 88SE64xx/88SE94xx const head file
0004  *
0005  * Copyright 2007 Red Hat, Inc.
0006  * Copyright 2008 Marvell. <kewei@marvell.com>
0007  * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
0008 */
0009 
0010 #ifndef _MV_DEFS_H_
0011 #define _MV_DEFS_H_
0012 
0013 #define PCI_DEVICE_ID_ARECA_1300    0x1300
0014 #define PCI_DEVICE_ID_ARECA_1320    0x1320
0015 
0016 enum chip_flavors {
0017     chip_6320,
0018     chip_6440,
0019     chip_6485,
0020     chip_9480,
0021     chip_9180,
0022     chip_9445,
0023     chip_9485,
0024     chip_1300,
0025     chip_1320
0026 };
0027 
0028 /* driver compile-time configuration */
0029 enum driver_configuration {
0030     MVS_TX_RING_SZ      = 1024, /* TX ring size (12-bit) */
0031     MVS_RX_RING_SZ      = 1024, /* RX ring size (12-bit) */
0032                     /* software requires power-of-2
0033                        ring size */
0034     MVS_SOC_SLOTS       = 64,
0035     MVS_SOC_TX_RING_SZ  = MVS_SOC_SLOTS * 2,
0036     MVS_SOC_RX_RING_SZ  = MVS_SOC_SLOTS * 2,
0037 
0038     MVS_SLOT_BUF_SZ     = 8192, /* cmd tbl + IU + status + PRD */
0039     MVS_SSP_CMD_SZ      = 64,   /* SSP command table buffer size */
0040     MVS_ATA_CMD_SZ      = 96,   /* SATA command table buffer size */
0041     MVS_OAF_SZ      = 64,   /* Open address frame buffer size */
0042     MVS_QUEUE_SIZE      = 64,   /* Support Queue depth */
0043     MVS_SOC_CAN_QUEUE   = MVS_SOC_SLOTS - 2,
0044 };
0045 
0046 /* unchangeable hardware details */
0047 enum hardware_details {
0048     MVS_MAX_PHYS        = 8,    /* max. possible phys */
0049     MVS_MAX_PORTS       = 8,    /* max. possible ports */
0050     MVS_SOC_PHYS        = 4,    /* soc phys */
0051     MVS_SOC_PORTS       = 4,    /* soc phys */
0052     MVS_MAX_DEVICES = 1024, /* max supported device */
0053 };
0054 
0055 /* peripheral registers (BAR2) */
0056 enum peripheral_registers {
0057     SPI_CTL         = 0x10, /* EEPROM control */
0058     SPI_CMD         = 0x14, /* EEPROM command */
0059     SPI_DATA        = 0x18, /* EEPROM data */
0060 };
0061 
0062 enum peripheral_register_bits {
0063     TWSI_RDY        = (1U << 7),    /* EEPROM interface ready */
0064     TWSI_RD         = (1U << 4),    /* EEPROM read access */
0065 
0066     SPI_ADDR_MASK       = 0x3ffff,  /* bits 17:0 */
0067 };
0068 
0069 enum hw_register_bits {
0070     /* MVS_GBL_CTL */
0071     INT_EN          = (1U << 1),    /* Global int enable */
0072     HBA_RST         = (1U << 0),    /* HBA reset */
0073 
0074     /* MVS_GBL_INT_STAT */
0075     INT_XOR         = (1U << 4),    /* XOR engine event */
0076     INT_SAS_SATA        = (1U << 0),    /* SAS/SATA event */
0077 
0078     /* MVS_GBL_PORT_TYPE */         /* shl for ports 1-3 */
0079     SATA_TARGET     = (1U << 16),   /* port0 SATA target enable */
0080     MODE_AUTO_DET_PORT7 = (1U << 15),   /* port0 SAS/SATA autodetect */
0081     MODE_AUTO_DET_PORT6 = (1U << 14),
0082     MODE_AUTO_DET_PORT5 = (1U << 13),
0083     MODE_AUTO_DET_PORT4 = (1U << 12),
0084     MODE_AUTO_DET_PORT3 = (1U << 11),
0085     MODE_AUTO_DET_PORT2 = (1U << 10),
0086     MODE_AUTO_DET_PORT1 = (1U << 9),
0087     MODE_AUTO_DET_PORT0 = (1U << 8),
0088     MODE_AUTO_DET_EN    =   MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
0089                 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
0090                 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
0091                 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
0092     MODE_SAS_PORT7_MASK = (1U << 7),  /* port0 SAS(1), SATA(0) mode */
0093     MODE_SAS_PORT6_MASK = (1U << 6),
0094     MODE_SAS_PORT5_MASK = (1U << 5),
0095     MODE_SAS_PORT4_MASK = (1U << 4),
0096     MODE_SAS_PORT3_MASK = (1U << 3),
0097     MODE_SAS_PORT2_MASK = (1U << 2),
0098     MODE_SAS_PORT1_MASK = (1U << 1),
0099     MODE_SAS_PORT0_MASK = (1U << 0),
0100     MODE_SAS_SATA   =   MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
0101                 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
0102                 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
0103                 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
0104 
0105                 /* SAS_MODE value may be
0106                  * dictated (in hw) by values
0107                  * of SATA_TARGET & AUTO_DET
0108                  */
0109 
0110     /* MVS_TX_CFG */
0111     TX_EN           = (1U << 16),   /* Enable TX */
0112     TX_RING_SZ_MASK     = 0xfff,    /* TX ring size, bits 11:0 */
0113 
0114     /* MVS_RX_CFG */
0115     RX_EN           = (1U << 16),   /* Enable RX */
0116     RX_RING_SZ_MASK     = 0xfff,    /* RX ring size, bits 11:0 */
0117 
0118     /* MVS_INT_COAL */
0119     COAL_EN         = (1U << 16),   /* Enable int coalescing */
0120 
0121     /* MVS_INT_STAT, MVS_INT_MASK */
0122     CINT_I2C        = (1U << 31),   /* I2C event */
0123     CINT_SW0        = (1U << 30),   /* software event 0 */
0124     CINT_SW1        = (1U << 29),   /* software event 1 */
0125     CINT_PRD_BC     = (1U << 28),   /* PRD BC err for read cmd */
0126     CINT_DMA_PCIE       = (1U << 27),   /* DMA to PCIE timeout */
0127     CINT_MEM        = (1U << 26),   /* int mem parity err */
0128     CINT_I2C_SLAVE      = (1U << 25),   /* slave I2C event */
0129     CINT_NON_SPEC_NCQ_ERROR = (1U << 25),   /* Non specific NCQ error */
0130     CINT_SRS        = (1U << 3),    /* SRS event */
0131     CINT_CI_STOP        = (1U << 1),    /* cmd issue stopped */
0132     CINT_DONE       = (1U << 0),    /* cmd completion */
0133 
0134                         /* shl for ports 1-3 */
0135     CINT_PORT_STOPPED   = (1U << 16),   /* port0 stopped */
0136     CINT_PORT       = (1U << 8),    /* port0 event */
0137     CINT_PORT_MASK_OFFSET   = 8,
0138     CINT_PORT_MASK      = (0xFF << CINT_PORT_MASK_OFFSET),
0139     CINT_PHY_MASK_OFFSET    = 4,
0140     CINT_PHY_MASK       = (0x0F << CINT_PHY_MASK_OFFSET),
0141 
0142     /* TX (delivery) ring bits */
0143     TXQ_CMD_SHIFT       = 29,
0144     TXQ_CMD_SSP     = 1,        /* SSP protocol */
0145     TXQ_CMD_SMP     = 2,        /* SMP protocol */
0146     TXQ_CMD_STP     = 3,        /* STP/SATA protocol */
0147     TXQ_CMD_SSP_FREE_LIST   = 4,        /* add to SSP target free list */
0148     TXQ_CMD_SLOT_RESET  = 7,        /* reset command slot */
0149     TXQ_MODE_I      = (1U << 28),   /* mode: 0=target,1=initiator */
0150     TXQ_MODE_TARGET     = 0,
0151     TXQ_MODE_INITIATOR  = 1,
0152     TXQ_PRIO_HI     = (1U << 27),   /* priority: 0=normal, 1=high */
0153     TXQ_PRI_NORMAL      = 0,
0154     TXQ_PRI_HIGH        = 1,
0155     TXQ_SRS_SHIFT       = 20,       /* SATA register set */
0156     TXQ_SRS_MASK        = 0x7f,
0157     TXQ_PHY_SHIFT       = 12,       /* PHY bitmap */
0158     TXQ_PHY_MASK        = 0xff,
0159     TXQ_SLOT_MASK       = 0xfff,    /* slot number */
0160 
0161     /* RX (completion) ring bits */
0162     RXQ_GOOD        = (1U << 23),   /* Response good */
0163     RXQ_SLOT_RESET      = (1U << 21),   /* Slot reset complete */
0164     RXQ_CMD_RX      = (1U << 20),   /* target cmd received */
0165     RXQ_ATTN        = (1U << 19),   /* attention */
0166     RXQ_RSP         = (1U << 18),   /* response frame xfer'd */
0167     RXQ_ERR         = (1U << 17),   /* err info rec xfer'd */
0168     RXQ_DONE        = (1U << 16),   /* cmd complete */
0169     RXQ_SLOT_MASK       = 0xfff,    /* slot number */
0170 
0171     /* mvs_cmd_hdr bits */
0172     MCH_PRD_LEN_SHIFT   = 16,       /* 16-bit PRD table len */
0173     MCH_SSP_FR_TYPE_SHIFT   = 13,       /* SSP frame type */
0174 
0175                         /* SSP initiator only */
0176     MCH_SSP_FR_CMD      = 0x0,      /* COMMAND frame */
0177 
0178                         /* SSP initiator or target */
0179     MCH_SSP_FR_TASK     = 0x1,      /* TASK frame */
0180 
0181                         /* SSP target only */
0182     MCH_SSP_FR_XFER_RDY = 0x4,      /* XFER_RDY frame */
0183     MCH_SSP_FR_RESP     = 0x5,      /* RESPONSE frame */
0184     MCH_SSP_FR_READ     = 0x6,      /* Read DATA frame(s) */
0185     MCH_SSP_FR_READ_RESP    = 0x7,      /* ditto, plus RESPONSE */
0186 
0187     MCH_SSP_MODE_PASSTHRU   = 1,
0188     MCH_SSP_MODE_NORMAL = 0,
0189     MCH_PASSTHRU        = (1U << 12),   /* pass-through (SSP) */
0190     MCH_FBURST      = (1U << 11),   /* first burst (SSP) */
0191     MCH_CHK_LEN     = (1U << 10),   /* chk xfer len (SSP) */
0192     MCH_RETRY       = (1U << 9),    /* tport layer retry (SSP) */
0193     MCH_PROTECTION      = (1U << 8),    /* protection info rec (SSP) */
0194     MCH_RESET       = (1U << 7),    /* Reset (STP/SATA) */
0195     MCH_FPDMA       = (1U << 6),    /* First party DMA (STP/SATA) */
0196     MCH_ATAPI       = (1U << 5),    /* ATAPI (STP/SATA) */
0197     MCH_BIST        = (1U << 4),    /* BIST activate (STP/SATA) */
0198     MCH_PMP_MASK        = 0xf,      /* PMP from cmd FIS (STP/SATA)*/
0199 
0200     CCTL_RST        = (1U << 5),    /* port logic reset */
0201 
0202                         /* 0(LSB first), 1(MSB first) */
0203     CCTL_ENDIAN_DATA    = (1U << 3),    /* PRD data */
0204     CCTL_ENDIAN_RSP     = (1U << 2),    /* response frame */
0205     CCTL_ENDIAN_OPEN    = (1U << 1),    /* open address frame */
0206     CCTL_ENDIAN_CMD     = (1U << 0),    /* command table */
0207 
0208     /* MVS_Px_SER_CTLSTAT (per-phy control) */
0209     PHY_SSP_RST     = (1U << 3),    /* reset SSP link layer */
0210     PHY_BCAST_CHG       = (1U << 2),    /* broadcast(change) notif */
0211     PHY_RST_HARD        = (1U << 1),    /* hard reset + phy reset */
0212     PHY_RST         = (1U << 0),    /* phy reset */
0213     PHY_READY_MASK      = (1U << 20),
0214 
0215     /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
0216     PHYEV_DEC_ERR       = (1U << 24),   /* Phy Decoding Error */
0217     PHYEV_DCDR_ERR      = (1U << 23),   /* STP Deocder Error */
0218     PHYEV_CRC_ERR       = (1U << 22),   /* STP CRC Error */
0219     PHYEV_UNASSOC_FIS   = (1U << 19),   /* unassociated FIS rx'd */
0220     PHYEV_AN        = (1U << 18),   /* SATA async notification */
0221     PHYEV_BIST_ACT      = (1U << 17),   /* BIST activate FIS */
0222     PHYEV_SIG_FIS       = (1U << 16),   /* signature FIS */
0223     PHYEV_POOF      = (1U << 12),   /* phy ready from 1 -> 0 */
0224     PHYEV_IU_BIG        = (1U << 11),   /* IU too long err */
0225     PHYEV_IU_SMALL      = (1U << 10),   /* IU too short err */
0226     PHYEV_UNK_TAG       = (1U << 9),    /* unknown tag */
0227     PHYEV_BROAD_CH      = (1U << 8),    /* broadcast(CHANGE) */
0228     PHYEV_COMWAKE       = (1U << 7),    /* COMWAKE rx'd */
0229     PHYEV_PORT_SEL      = (1U << 6),    /* port selector present */
0230     PHYEV_HARD_RST      = (1U << 5),    /* hard reset rx'd */
0231     PHYEV_ID_TMOUT      = (1U << 4),    /* identify timeout */
0232     PHYEV_ID_FAIL       = (1U << 3),    /* identify failed */
0233     PHYEV_ID_DONE       = (1U << 2),    /* identify done */
0234     PHYEV_HARD_RST_DONE = (1U << 1),    /* hard reset done */
0235     PHYEV_RDY_CH        = (1U << 0),    /* phy ready changed state */
0236 
0237     /* MVS_PCS */
0238     PCS_EN_SATA_REG_SHIFT   = (16),     /* Enable SATA Register Set */
0239     PCS_EN_PORT_XMT_SHIFT   = (12),     /* Enable Port Transmit */
0240     PCS_EN_PORT_XMT_SHIFT2  = (8),      /* For 6485 */
0241     PCS_SATA_RETRY      = (1U << 8),    /* retry ctl FIS on R_ERR */
0242     PCS_RSP_RX_EN       = (1U << 7),    /* raw response rx */
0243     PCS_SATA_RETRY_2    = (1U << 6),    /* For 9180 */
0244     PCS_SELF_CLEAR      = (1U << 5),    /* self-clearing int mode */
0245     PCS_FIS_RX_EN       = (1U << 4),    /* FIS rx enable */
0246     PCS_CMD_STOP_ERR    = (1U << 3),    /* cmd stop-on-err enable */
0247     PCS_CMD_RST     = (1U << 1),    /* reset cmd issue */
0248     PCS_CMD_EN      = (1U << 0),    /* enable cmd issue */
0249 
0250     /* Port n Attached Device Info */
0251     PORT_DEV_SSP_TRGT   = (1U << 19),
0252     PORT_DEV_SMP_TRGT   = (1U << 18),
0253     PORT_DEV_STP_TRGT   = (1U << 17),
0254     PORT_DEV_SSP_INIT   = (1U << 11),
0255     PORT_DEV_SMP_INIT   = (1U << 10),
0256     PORT_DEV_STP_INIT   = (1U << 9),
0257     PORT_PHY_ID_MASK    = (0xFFU << 24),
0258     PORT_SSP_TRGT_MASK  = (0x1U << 19),
0259     PORT_SSP_INIT_MASK  = (0x1U << 11),
0260     PORT_DEV_TRGT_MASK  = (0x7U << 17),
0261     PORT_DEV_INIT_MASK  = (0x7U << 9),
0262     PORT_DEV_TYPE_MASK  = (0x7U << 0),
0263 
0264     /* Port n PHY Status */
0265     PHY_RDY         = (1U << 2),
0266     PHY_DW_SYNC     = (1U << 1),
0267     PHY_OOB_DTCTD       = (1U << 0),
0268 
0269     /* VSR */
0270     /* PHYMODE 6 (CDB) */
0271     PHY_MODE6_LATECLK   = (1U << 29),   /* Lock Clock */
0272     PHY_MODE6_DTL_SPEED = (1U << 27),   /* Digital Loop Speed */
0273     PHY_MODE6_FC_ORDER  = (1U << 26),   /* Fibre Channel Mode Order*/
0274     PHY_MODE6_MUCNT_EN  = (1U << 24),   /* u Count Enable */
0275     PHY_MODE6_SEL_MUCNT_LEN = (1U << 22),   /* Training Length Select */
0276     PHY_MODE6_SELMUPI   = (1U << 20),   /* Phase Multi Select (init) */
0277     PHY_MODE6_SELMUPF   = (1U << 18),   /* Phase Multi Select (final) */
0278     PHY_MODE6_SELMUFF   = (1U << 16),   /* Freq Loop Multi Sel(final) */
0279     PHY_MODE6_SELMUFI   = (1U << 14),   /* Freq Loop Multi Sel(init) */
0280     PHY_MODE6_FREEZE_LOOP   = (1U << 12),   /* Freeze Rx CDR Loop */
0281     PHY_MODE6_INT_RXFOFFS   = (1U << 3),    /* Rx CDR Freq Loop Enable */
0282     PHY_MODE6_FRC_RXFOFFS   = (1U << 2),    /* Initial Rx CDR Offset */
0283     PHY_MODE6_STAU_0D8  = (1U << 1),    /* Rx CDR Freq Loop Saturate */
0284     PHY_MODE6_RXSAT_DIS = (1U << 0),    /* Saturate Ctl */
0285 };
0286 
0287 /* SAS/SATA configuration port registers, aka phy registers */
0288 enum sas_sata_config_port_regs {
0289     PHYR_IDENTIFY       = 0x00, /* info for IDENTIFY frame */
0290     PHYR_ADDR_LO        = 0x04, /* my SAS address (low) */
0291     PHYR_ADDR_HI        = 0x08, /* my SAS address (high) */
0292     PHYR_ATT_DEV_INFO   = 0x0C, /* attached device info */
0293     PHYR_ATT_ADDR_LO    = 0x10, /* attached dev SAS addr (low) */
0294     PHYR_ATT_ADDR_HI    = 0x14, /* attached dev SAS addr (high) */
0295     PHYR_SATA_CTL       = 0x18, /* SATA control */
0296     PHYR_PHY_STAT       = 0x1C, /* PHY status */
0297     PHYR_SATA_SIG0  = 0x20, /*port SATA signature FIS(Byte 0-3) */
0298     PHYR_SATA_SIG1  = 0x24, /*port SATA signature FIS(Byte 4-7) */
0299     PHYR_SATA_SIG2  = 0x28, /*port SATA signature FIS(Byte 8-11) */
0300     PHYR_SATA_SIG3  = 0x2c, /*port SATA signature FIS(Byte 12-15) */
0301     PHYR_R_ERR_COUNT    = 0x30, /* port R_ERR count register */
0302     PHYR_CRC_ERR_COUNT  = 0x34, /* port CRC error count register */
0303     PHYR_WIDE_PORT  = 0x38, /* wide port participating */
0304     PHYR_CURRENT0       = 0x80, /* current connection info 0 */
0305     PHYR_CURRENT1       = 0x84, /* current connection info 1 */
0306     PHYR_CURRENT2       = 0x88, /* current connection info 2 */
0307     CONFIG_ID_FRAME0       = 0x100, /* Port device ID frame register 0 */
0308     CONFIG_ID_FRAME1       = 0x104, /* Port device ID frame register 1 */
0309     CONFIG_ID_FRAME2       = 0x108, /* Port device ID frame register 2 */
0310     CONFIG_ID_FRAME3       = 0x10c, /* Port device ID frame register 3 */
0311     CONFIG_ID_FRAME4       = 0x110, /* Port device ID frame register 4 */
0312     CONFIG_ID_FRAME5       = 0x114, /* Port device ID frame register 5 */
0313     CONFIG_ID_FRAME6       = 0x118, /* Port device ID frame register 6 */
0314     CONFIG_ATT_ID_FRAME0   = 0x11c, /* attached ID frame register 0 */
0315     CONFIG_ATT_ID_FRAME1   = 0x120, /* attached ID frame register 1 */
0316     CONFIG_ATT_ID_FRAME2   = 0x124, /* attached ID frame register 2 */
0317     CONFIG_ATT_ID_FRAME3   = 0x128, /* attached ID frame register 3 */
0318     CONFIG_ATT_ID_FRAME4   = 0x12c, /* attached ID frame register 4 */
0319     CONFIG_ATT_ID_FRAME5   = 0x130, /* attached ID frame register 5 */
0320     CONFIG_ATT_ID_FRAME6   = 0x134, /* attached ID frame register 6 */
0321 };
0322 
0323 enum sas_cmd_port_registers {
0324     CMD_CMRST_OOB_DET   = 0x100, /* COMRESET OOB detect register */
0325     CMD_CMWK_OOB_DET    = 0x104, /* COMWAKE OOB detect register */
0326     CMD_CMSAS_OOB_DET   = 0x108, /* COMSAS OOB detect register */
0327     CMD_BRST_OOB_DET    = 0x10c, /* burst OOB detect register */
0328     CMD_OOB_SPACE   = 0x110, /* OOB space control register */
0329     CMD_OOB_BURST   = 0x114, /* OOB burst control register */
0330     CMD_PHY_TIMER       = 0x118, /* PHY timer control register */
0331     CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
0332     CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
0333     CMD_SAS_CTL0        = 0x124, /* SAS control register 0 */
0334     CMD_SAS_CTL1        = 0x128, /* SAS control register 1 */
0335     CMD_SAS_CTL2        = 0x12c, /* SAS control register 2 */
0336     CMD_SAS_CTL3        = 0x130, /* SAS control register 3 */
0337     CMD_ID_TEST     = 0x134, /* ID test register */
0338     CMD_PL_TIMER        = 0x138, /* PL timer register */
0339     CMD_WD_TIMER        = 0x13c, /* WD timer register */
0340     CMD_PORT_SEL_COUNT  = 0x140, /* port selector count register */
0341     CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
0342     CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
0343     CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
0344     CMD_PORT_MEM_CTL0   = 0x150, /* Port Memory Control 0 */
0345     CMD_PORT_MEM_CTL1   = 0x154, /* Port Memory Control 1 */
0346     CMD_SATA_PORT_MEM_CTL0  = 0x158, /* SATA Port Memory Control 0 */
0347     CMD_SATA_PORT_MEM_CTL1  = 0x15c, /* SATA Port Memory Control 1 */
0348     CMD_XOR_MEM_BIST_CTL    = 0x160, /* XOR Memory BIST Control */
0349     CMD_XOR_MEM_BIST_STAT   = 0x164, /* XOR Memroy BIST Status */
0350     CMD_DMA_MEM_BIST_CTL    = 0x168, /* DMA Memory BIST Control */
0351     CMD_DMA_MEM_BIST_STAT   = 0x16c, /* DMA Memory BIST Status */
0352     CMD_PORT_MEM_BIST_CTL   = 0x170, /* Port Memory BIST Control */
0353     CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
0354     CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
0355     CMD_STP_MEM_BIST_CTL    = 0x17c, /* STP Memory BIST Control */
0356     CMD_STP_MEM_BIST_STAT0  = 0x180, /* STP Memory BIST Status 0 */
0357     CMD_STP_MEM_BIST_STAT1  = 0x184, /* STP Memory BIST Status 1 */
0358     CMD_RESET_COUNT     = 0x188, /* Reset Count */
0359     CMD_MONTR_DATA_SEL  = 0x18C, /* Monitor Data/Select */
0360     CMD_PLL_PHY_CONFIG  = 0x190, /* PLL/PHY Configuration */
0361     CMD_PHY_CTL     = 0x194, /* PHY Control and Status */
0362     CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
0363     CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
0364     CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
0365     CMD_APP_ERR_CONFIG  = 0x1A4, /* Application Error Configuration */
0366     CMD_PND_FIFO_CTL0   = 0x1A8, /* Pending FIFO Control 0 */
0367     CMD_HOST_CTL        = 0x1AC, /* Host Control Status */
0368     CMD_HOST_WR_DATA    = 0x1B0, /* Host Write Data */
0369     CMD_HOST_RD_DATA    = 0x1B4, /* Host Read Data */
0370     CMD_PHY_MODE_21     = 0x1B8, /* Phy Mode 21 */
0371     CMD_SL_MODE0        = 0x1BC, /* SL Mode 0 */
0372     CMD_SL_MODE1        = 0x1C0, /* SL Mode 1 */
0373     CMD_PND_FIFO_CTL1   = 0x1C4, /* Pending FIFO Control 1 */
0374     CMD_PORT_LAYER_TIMER1   = 0x1E0, /* Port Layer Timer 1 */
0375     CMD_LINK_TIMER      = 0x1E4, /* Link Timer */
0376 };
0377 
0378 enum mvs_info_flags {
0379     MVF_PHY_PWR_FIX = (1U << 1),    /* bug workaround */
0380     MVF_FLAG_SOC        = (1U << 2),    /* SoC integrated controllers */
0381 };
0382 
0383 enum mvs_event_flags {
0384     PHY_PLUG_EVENT      = (3U),
0385     PHY_PLUG_IN     = (1U << 0),    /* phy plug in */
0386     PHY_PLUG_OUT        = (1U << 1),    /* phy plug out */
0387     EXP_BRCT_CHG        = (1U << 2),    /* broadcast change */
0388 };
0389 
0390 enum mvs_port_type {
0391     PORT_TGT_MASK   =  (1U << 5),
0392     PORT_INIT_PORT  =  (1U << 4),
0393     PORT_TGT_PORT   =  (1U << 3),
0394     PORT_INIT_TGT_PORT = (PORT_INIT_PORT | PORT_TGT_PORT),
0395     PORT_TYPE_SAS   =  (1U << 1),
0396     PORT_TYPE_SATA  =  (1U << 0),
0397 };
0398 
0399 /* Command Table Format */
0400 enum ct_format {
0401     /* SSP */
0402     SSP_F_H     =  0x00,
0403     SSP_F_IU    =  0x18,
0404     SSP_F_MAX   =  0x4D,
0405     /* STP */
0406     STP_CMD_FIS =  0x00,
0407     STP_ATAPI_CMD   =  0x40,
0408     STP_F_MAX   =  0x10,
0409     /* SMP */
0410     SMP_F_T     =  0x00,
0411     SMP_F_DEP   =  0x01,
0412     SMP_F_MAX   =  0x101,
0413 };
0414 
0415 enum status_buffer {
0416     SB_EIR_OFF  =  0x00,    /* Error Information Record */
0417     SB_RFB_OFF  =  0x08,    /* Response Frame Buffer */
0418     SB_RFB_MAX  =  0x400,   /* RFB size*/
0419 };
0420 
0421 enum error_info_rec {
0422     CMD_ISS_STPD    = (1U << 31),   /* Cmd Issue Stopped */
0423     CMD_PI_ERR  = (1U << 30),   /* Protection info error.  see flags2 */
0424     RSP_OVER    = (1U << 29),   /* rsp buffer overflow */
0425     RETRY_LIM   = (1U << 28),   /* FIS/frame retry limit exceeded */
0426     UNK_FIS     = (1U << 27),   /* unknown FIS */
0427     DMA_TERM    = (1U << 26),   /* DMA terminate primitive rx'd */
0428     SYNC_ERR    = (1U << 25),   /* SYNC rx'd during frame xmit */
0429     TFILE_ERR   = (1U << 24),   /* SATA taskfile Error bit set */
0430     R_ERR       = (1U << 23),   /* SATA returned R_ERR prim */
0431     RD_OFS      = (1U << 20),   /* Read DATA frame invalid offset */
0432     XFER_RDY_OFS    = (1U << 19),   /* XFER_RDY offset error */
0433     UNEXP_XFER_RDY  = (1U << 18),   /* unexpected XFER_RDY error */
0434     DATA_OVER_UNDER = (1U << 16),   /* data overflow/underflow */
0435     INTERLOCK   = (1U << 15),   /* interlock error */
0436     NAK     = (1U << 14),   /* NAK rx'd */
0437     ACK_NAK_TO  = (1U << 13),   /* ACK/NAK timeout */
0438     CXN_CLOSED  = (1U << 12),   /* cxn closed w/out ack/nak */
0439     OPEN_TO     = (1U << 11),   /* I_T nexus lost, open cxn timeout */
0440     PATH_BLOCKED    = (1U << 10),   /* I_T nexus lost, pathway blocked */
0441     NO_DEST     = (1U << 9),    /* I_T nexus lost, no destination */
0442     STP_RES_BSY = (1U << 8),    /* STP resources busy */
0443     BREAK       = (1U << 7),    /* break received */
0444     BAD_DEST    = (1U << 6),    /* bad destination */
0445     BAD_PROTO   = (1U << 5),    /* protocol not supported */
0446     BAD_RATE    = (1U << 4),    /* cxn rate not supported */
0447     WRONG_DEST  = (1U << 3),    /* wrong destination error */
0448     CREDIT_TO   = (1U << 2),    /* credit timeout */
0449     WDOG_TO     = (1U << 1),    /* watchdog timeout */
0450     BUF_PAR     = (1U << 0),    /* buffer parity error */
0451 };
0452 
0453 enum error_info_rec_2 {
0454     SLOT_BSY_ERR    = (1U << 31),   /* Slot Busy Error */
0455     GRD_CHK_ERR = (1U << 14),   /* Guard Check Error */
0456     APP_CHK_ERR = (1U << 13),   /* Application Check error */
0457     REF_CHK_ERR = (1U << 12),   /* Reference Check Error */
0458     USR_BLK_NM  = (1U << 0),    /* User Block Number */
0459 };
0460 
0461 enum pci_cfg_register_bits {
0462     PCTL_PWR_OFF    = (0xFU << 24),
0463     PCTL_COM_ON = (0xFU << 20),
0464     PCTL_LINK_RST   = (0xFU << 16),
0465     PCTL_LINK_OFFS  = (16),
0466     PCTL_PHY_DSBL   = (0xFU << 12),
0467     PCTL_PHY_DSBL_OFFS  = (12),
0468     PRD_REQ_SIZE    = (0x4000),
0469     PRD_REQ_MASK    = (0x00007000),
0470     PLS_NEG_LINK_WD     = (0x3FU << 4),
0471     PLS_NEG_LINK_WD_OFFS    = 4,
0472     PLS_LINK_SPD        = (0x0FU << 0),
0473     PLS_LINK_SPD_OFFS   = 0,
0474 };
0475 
0476 enum open_frame_protocol {
0477     PROTOCOL_SMP    = 0x0,
0478     PROTOCOL_SSP    = 0x1,
0479     PROTOCOL_STP    = 0x2,
0480 };
0481 
0482 /* define for response frame datapres field */
0483 enum datapres_field {
0484     NO_DATA     = 0,
0485     RESPONSE_DATA   = 1,
0486     SENSE_DATA  = 2,
0487 };
0488 
0489 #endif
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